base.cc revision 2422
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147338SAli.Saidi@ARM.com * this software without specific prior written permission. 151762SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#include <cmath> 302SN/A#include <cstdio> 312SN/A#include <cstdlib> 322SN/A#include <iostream> 332SN/A#include <iomanip> 342SN/A#include <list> 352SN/A#include <sstream> 362SN/A#include <string> 372SN/A 382SN/A#include "base/cprintf.hh" 392SN/A#include "base/inifile.hh" 402665Ssaidi@eecs.umich.edu#include "base/loader/symtab.hh" 412665Ssaidi@eecs.umich.edu#include "base/misc.hh" 422SN/A#include "base/pollevent.hh" 432SN/A#include "base/range.hh" 448779Sgblack@eecs.umich.edu#include "base/stats/events.hh" 458779Sgblack@eecs.umich.edu#include "base/trace.hh" 468779Sgblack@eecs.umich.edu#include "cpu/base.hh" 472439SN/A#include "cpu/cpu_exec_context.hh" 488779Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 498229Snate@binkert.org#include "cpu/exetrace.hh" 506216Snate@binkert.org#include "cpu/profile.hh" 51146SN/A#include "cpu/sampler/sampler.hh" 52146SN/A#include "cpu/simple/cpu.hh" 53146SN/A#include "cpu/smt.hh" 54146SN/A#include "cpu/static_inst.hh" 55146SN/A#include "kern/kernel_stats.hh" 566216Snate@binkert.org#include "sim/byteswap.hh" 576658Snate@binkert.org#include "sim/builder.hh" 588229Snate@binkert.org#include "sim/debug.hh" 591717SN/A#include "sim/host.hh" 608887Sgeoffrey.blake@arm.com#include "sim/sim_events.hh" 618887Sgeoffrey.blake@arm.com#include "sim/sim_object.hh" 62146SN/A#include "sim/stats.hh" 6310061Sandreas@sandberg.pp.se 641977SN/A#if FULL_SYSTEM 652683Sktlim@umich.edu#include "base/remote_gdb.hh" 661717SN/A#include "mem/functional/memory_control.hh" 67146SN/A#include "mem/functional/physical.hh" 682683Sktlim@umich.edu#include "sim/system.hh" 698232Snate@binkert.org#include "arch/tlb.hh" 708232Snate@binkert.org#include "arch/stacktrace.hh" 718232Snate@binkert.org#include "arch/vtophys.hh" 728779Sgblack@eecs.umich.edu#else // !FULL_SYSTEM 733348Sbinkertn@umich.edu#include "mem/memory.hh" 746105Ssteve.reinhardt@amd.com#endif // FULL_SYSTEM 756216Snate@binkert.org 762036SN/Ausing namespace std; 77146SN/A//The SimpleCPU does alpha only 788817Sgblack@eecs.umich.eduusing namespace AlphaISA; 798793Sgblack@eecs.umich.edu 8056SN/A 8156SN/ASimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) 82695SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) 832901Ssaidi@eecs.umich.edu{ 842SN/A} 852SN/A 862449SN/A 871355SN/Avoid 885529Snate@binkert.orgSimpleCPU::init() 8910061Sandreas@sandberg.pp.se{ 9010061Sandreas@sandberg.pp.se BaseCPU::init(); 9110061Sandreas@sandberg.pp.se#if FULL_SYSTEM 92224SN/A for (int i = 0; i < execContexts.size(); ++i) { 938793Sgblack@eecs.umich.edu ExecContext *xc = execContexts[i]; 949384SAndreas.Sandberg@arm.com 959384SAndreas.Sandberg@arm.com // initialize CPU, including PC 968793Sgblack@eecs.umich.edu TheISA::initCPU(xc, xc->readCpuId()); 978820Sgblack@eecs.umich.edu } 989384SAndreas.Sandberg@arm.com#endif 992SN/A} 1006029Ssteve.reinhardt@amd.com 1012672Sktlim@umich.eduvoid 1022683Sktlim@umich.eduSimpleCPU::TickEvent::process() 1032SN/A{ 1048733Sgeoffrey.blake@arm.com int count = width; 1058733Sgeoffrey.blake@arm.com do { 1068733Sgeoffrey.blake@arm.com cpu->tick(); 1078733Sgeoffrey.blake@arm.com } while (--count > 0 && cpu->status() == Running); 1088733Sgeoffrey.blake@arm.com} 1098733Sgeoffrey.blake@arm.com 1108733Sgeoffrey.blake@arm.comconst char * 1118733Sgeoffrey.blake@arm.comSimpleCPU::TickEvent::description() 1128733Sgeoffrey.blake@arm.com{ 1138733Sgeoffrey.blake@arm.com return "SimpleCPU tick event"; 1148733Sgeoffrey.blake@arm.com} 1152SN/A 116334SN/A 1178834Satgutier@umich.edubool 1188834Satgutier@umich.eduSimpleCPU::CpuPort::recvTiming(Packet &pkt) 119140SN/A{ 120334SN/A cpu->processResponse(pkt); 1212SN/A return true; 1222SN/A} 1232SN/A 1242680Sktlim@umich.eduTick 1254377Sgblack@eecs.umich.eduSimpleCPU::CpuPort::recvAtomic(Packet &pkt) 1265169Ssaidi@eecs.umich.edu{ 1274377Sgblack@eecs.umich.edu panic("CPU doesn't expect callback!"); 1284377Sgblack@eecs.umich.edu return curTick; 1292SN/A} 1302SN/A 1312623SN/Avoid 1322SN/ASimpleCPU::CpuPort::recvFunctional(Packet &pkt) 1332SN/A{ 1342SN/A panic("CPU doesn't expect callback!"); 135180SN/A} 1368737Skoansin.tan@gmail.com 137393SN/Avoid 138393SN/ASimpleCPU::CpuPort::recvStatusChange(Status status) 139393SN/A{ 140393SN/A cpu->recvStatusChange(status); 141384SN/A} 142384SN/A 143393SN/APacket * 1448737Skoansin.tan@gmail.comSimpleCPU::CpuPort::recvRetry() 145393SN/A{ 146393SN/A return cpu->processRetry(); 147393SN/A} 148393SN/A 149384SN/ASimpleCPU::SimpleCPU(Params *p) 150189SN/A : BaseCPU(p), icachePort(this), 151189SN/A dcachePort(this), tickEvent(this, p->width), cpuXC(NULL) 1522623SN/A{ 1532SN/A _status = Idle; 154729SN/A 155334SN/A //Create Memory Ports (conect them up) 1562SN/A p->mem->addPort("DCACHE"); 1572SN/A dcachePort.setPeer(p->mem->getPort("DCACHE")); 1582SN/A (p->mem->getPort("DCACHE"))->setPeer(&dcachePort); 1598834Satgutier@umich.edu 1608834Satgutier@umich.edu p->mem->addPort("ICACHE"); 1618834Satgutier@umich.edu icachePort.setPeer(p->mem->getPort("ICACHE")); 1628834Satgutier@umich.edu (p->mem->getPort("ICACHE"))->setPeer(&icachePort); 1638834Satgutier@umich.edu 1648834Satgutier@umich.edu#if FULL_SYSTEM 1658834Satgutier@umich.edu cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); 1662SN/A#else 1672SN/A cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0, 1687897Shestness@cs.utexas.edu &dcachePort); 1697897Shestness@cs.utexas.edu#endif // !FULL_SYSTEM 1707897Shestness@cs.utexas.edu 1717897Shestness@cs.utexas.edu xcProxy = cpuXC->getProxy(); 1727897Shestness@cs.utexas.edu 1737897Shestness@cs.utexas.edu#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE 1747897Shestness@cs.utexas.edu ifetch_req = new CpuRequest; 1757897Shestness@cs.utexas.edu ifetch_req->asid = 0; 1767897Shestness@cs.utexas.edu ifetch_req->size = sizeof(MachInst); 1777897Shestness@cs.utexas.edu ifetch_pkt = new Packet; 1787897Shestness@cs.utexas.edu ifetch_pkt->cmd = Read; 1797897Shestness@cs.utexas.edu ifetch_pkt->data = (uint8_t *)&inst; 1807897Shestness@cs.utexas.edu ifetch_pkt->req = ifetch_req; 1817897Shestness@cs.utexas.edu ifetch_pkt->size = sizeof(MachInst); 1827897Shestness@cs.utexas.edu 1837897Shestness@cs.utexas.edu data_read_req = new CpuRequest; 1847897Shestness@cs.utexas.edu data_read_req->asid = 0; 1857897Shestness@cs.utexas.edu data_read_pkt = new Packet; 1867897Shestness@cs.utexas.edu data_read_pkt->cmd = Read; 1877897Shestness@cs.utexas.edu data_read_pkt->data = new uint8_t[8]; 1887897Shestness@cs.utexas.edu data_read_pkt->req = data_read_req; 1897897Shestness@cs.utexas.edu 1907897Shestness@cs.utexas.edu data_write_req = new CpuRequest; 1917897Shestness@cs.utexas.edu data_write_req->asid = 0; 1927897Shestness@cs.utexas.edu data_write_pkt = new Packet; 1937897Shestness@cs.utexas.edu data_write_pkt->cmd = Write; 1947897Shestness@cs.utexas.edu data_write_pkt->req = data_write_req; 1957897Shestness@cs.utexas.edu#endif 1967897Shestness@cs.utexas.edu 1977897Shestness@cs.utexas.edu numInst = 0; 1987897Shestness@cs.utexas.edu startNumInst = 0; 1997897Shestness@cs.utexas.edu numLoad = 0; 2007897Shestness@cs.utexas.edu startNumLoad = 0; 2017897Shestness@cs.utexas.edu lastIcacheStall = 0; 2027897Shestness@cs.utexas.edu lastDcacheStall = 0; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu execContexts.push_back(xcProxy); 2057897Shestness@cs.utexas.edu} 2067897Shestness@cs.utexas.edu 2077897Shestness@cs.utexas.eduSimpleCPU::~SimpleCPU() 2087897Shestness@cs.utexas.edu{ 2097897Shestness@cs.utexas.edu} 2107897Shestness@cs.utexas.edu 2117897Shestness@cs.utexas.eduvoid 2127897Shestness@cs.utexas.eduSimpleCPU::switchOut(Sampler *s) 2137897Shestness@cs.utexas.edu{ 2147897Shestness@cs.utexas.edu sampler = s; 2157897Shestness@cs.utexas.edu if (status() == DcacheWaitResponse) { 2167897Shestness@cs.utexas.edu DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n"); 2177897Shestness@cs.utexas.edu _status = DcacheWaitSwitch; 2189920Syasuko.eckert@amd.com } 2199920Syasuko.eckert@amd.com else { 2209920Syasuko.eckert@amd.com _status = SwitchedOut; 2219920Syasuko.eckert@amd.com 2229920Syasuko.eckert@amd.com if (tickEvent.scheduled()) 2239920Syasuko.eckert@amd.com tickEvent.squash(); 2249920Syasuko.eckert@amd.com 2259920Syasuko.eckert@amd.com sampler->signalSwitched(); 2269920Syasuko.eckert@amd.com } 2279920Syasuko.eckert@amd.com} 2289920Syasuko.eckert@amd.com 2299920Syasuko.eckert@amd.com 2302SN/Avoid 2317897Shestness@cs.utexas.eduSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2327897Shestness@cs.utexas.edu{ 2337897Shestness@cs.utexas.edu BaseCPU::takeOverFrom(oldCPU); 2347897Shestness@cs.utexas.edu 2357897Shestness@cs.utexas.edu assert(!tickEvent.scheduled()); 2367897Shestness@cs.utexas.edu 2377897Shestness@cs.utexas.edu // if any of this CPU's ExecContexts are active, mark the CPU as 2387897Shestness@cs.utexas.edu // running and schedule its tick event. 2397897Shestness@cs.utexas.edu for (int i = 0; i < execContexts.size(); ++i) { 2407897Shestness@cs.utexas.edu ExecContext *xc = execContexts[i]; 2417897Shestness@cs.utexas.edu if (xc->status() == ExecContext::Active && _status != Running) { 2427897Shestness@cs.utexas.edu _status = Running; 2432SN/A tickEvent.schedule(curTick); 2442SN/A } 2451001SN/A } 2461001SN/A} 2471001SN/A 2481001SN/A 2491001SN/Avoid 2502SN/ASimpleCPU::activateContext(int thread_num, int delay) 2512SN/A{ 2522SN/A assert(thread_num == 0); 2532SN/A assert(cpuXC); 2542SN/A 2557897Shestness@cs.utexas.edu assert(_status == Idle); 2567897Shestness@cs.utexas.edu notIdleFraction++; 2577897Shestness@cs.utexas.edu scheduleTickEvent(delay); 2587897Shestness@cs.utexas.edu _status = Running; 2597897Shestness@cs.utexas.edu} 2607897Shestness@cs.utexas.edu 2617897Shestness@cs.utexas.edu 2627897Shestness@cs.utexas.eduvoid 2637897Shestness@cs.utexas.eduSimpleCPU::suspendContext(int thread_num) 2647897Shestness@cs.utexas.edu{ 2652SN/A assert(thread_num == 0); 2662SN/A assert(cpuXC); 2672SN/A 2682SN/A assert(_status == Running); 2692SN/A notIdleFraction--; 2702SN/A unscheduleTickEvent(); 2712SN/A _status = Idle; 2722SN/A} 2732SN/A 2742SN/A 2752SN/Avoid 2762SN/ASimpleCPU::deallocateContext(int thread_num) 2772390SN/A{ 2782390SN/A // for now, these are equivalent 2792390SN/A suspendContext(thread_num); 2802390SN/A} 2812390SN/A 2822390SN/A 2832390SN/Avoid 2842390SN/ASimpleCPU::haltContext(int thread_num) 2852390SN/A{ 2862390SN/A // for now, these are equivalent 2872390SN/A suspendContext(thread_num); 2882390SN/A} 289385SN/A 2907897Shestness@cs.utexas.edu 2917897Shestness@cs.utexas.eduvoid 29210061Sandreas@sandberg.pp.seSimpleCPU::regStats() 29310061Sandreas@sandberg.pp.se{ 29410061Sandreas@sandberg.pp.se using namespace Stats; 29510061Sandreas@sandberg.pp.se 29610061Sandreas@sandberg.pp.se BaseCPU::regStats(); 29710061Sandreas@sandberg.pp.se 29810061Sandreas@sandberg.pp.se numInsts 29910061Sandreas@sandberg.pp.se .name(name() + ".num_insts") 30010061Sandreas@sandberg.pp.se .desc("Number of instructions executed") 30110061Sandreas@sandberg.pp.se ; 30210061Sandreas@sandberg.pp.se 30310061Sandreas@sandberg.pp.se numMemRefs 30410061Sandreas@sandberg.pp.se .name(name() + ".num_refs") 30510061Sandreas@sandberg.pp.se .desc("Number of memory references") 30610061Sandreas@sandberg.pp.se ; 3072SN/A 3082SN/A notIdleFraction 3092SN/A .name(name() + ".not_idle_fraction") 3102623SN/A .desc("Percentage of non-idle cycles") 311334SN/A ; 3122361SN/A 3135496Ssaidi@eecs.umich.edu idleFraction 314334SN/A .name(name() + ".idle_fraction") 315334SN/A .desc("Percentage of idle cycles") 316334SN/A ; 3179448SAndreas.Sandberg@ARM.com 3182SN/A icacheStallCycles 3199448SAndreas.Sandberg@ARM.com .name(name() + ".icache_stall_cycles") 3209448SAndreas.Sandberg@ARM.com .desc("ICache total stall cycles") 3219448SAndreas.Sandberg@ARM.com .prereq(icacheStallCycles) 3222683Sktlim@umich.edu ; 3232SN/A 3242SN/A dcacheStallCycles 3252SN/A .name(name() + ".dcache_stall_cycles") 3269448SAndreas.Sandberg@ARM.com .desc("DCache total stall cycles") 3279448SAndreas.Sandberg@ARM.com .prereq(dcacheStallCycles) 3282SN/A ; 3299448SAndreas.Sandberg@ARM.com 3309448SAndreas.Sandberg@ARM.com icacheRetryCycles 3319448SAndreas.Sandberg@ARM.com .name(name() + ".icache_retry_cycles") 3322SN/A .desc("ICache total retry cycles") 3332SN/A .prereq(icacheRetryCycles) 3342SN/A ; 3356221Snate@binkert.org 3362SN/A dcacheRetryCycles 3372SN/A .name(name() + ".dcache_retry_cycles") 3382SN/A .desc("DCache total retry cycles") 3392SN/A .prereq(dcacheRetryCycles) 3402623SN/A ; 3412SN/A 3422680Sktlim@umich.edu idleFraction = constant(1.0) - notIdleFraction; 3432SN/A} 3442SN/A 3452SN/Avoid 3465807Snate@binkert.orgSimpleCPU::resetStats() 3472SN/A{ 3485807Snate@binkert.org startNumInst = numInst; 3495807Snate@binkert.org notIdleFraction = (_status != Idle); 3502SN/A} 3515807Snate@binkert.org 3525807Snate@binkert.orgvoid 3532SN/ASimpleCPU::serialize(ostream &os) 3542SN/A{ 3552SN/A BaseCPU::serialize(os); 3562623SN/A SERIALIZE_ENUM(_status); 3572SN/A SERIALIZE_SCALAR(inst); 3585704Snate@binkert.org nameOut(os, csprintf("%s.xc", name())); 3595647Sgblack@eecs.umich.edu cpuXC->serialize(os); 3602SN/A nameOut(os, csprintf("%s.tickEvent", name())); 3613520Sgblack@eecs.umich.edu tickEvent.serialize(os); 3627338SAli.Saidi@ARM.com nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 3635647Sgblack@eecs.umich.edu} 3643520Sgblack@eecs.umich.edu 3659023Sgblack@eecs.umich.eduvoid 3662SN/ASimpleCPU::unserialize(Checkpoint *cp, const string §ion) 3672SN/A{ 3682623SN/A BaseCPU::unserialize(cp, section); 3692SN/A UNSERIALIZE_ENUM(_status); 3702623SN/A UNSERIALIZE_SCALAR(inst); 3715894Sgblack@eecs.umich.edu cpuXC->unserialize(cp, csprintf("%s.xc", section)); 3722662Sstever@eecs.umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 3732623SN/A} 3747720Sgblack@eecs.umich.edu 3754495Sacolyte@umich.eduvoid 3762623SN/Achange_thread_state(int thread_number, int activate, int priority) 3777720Sgblack@eecs.umich.edu{ 3782623SN/A} 3797720Sgblack@eecs.umich.edu 3808832SAli.Saidi@ARM.comFault 3818832SAli.Saidi@ARM.comSimpleCPU::copySrcTranslate(Addr src) 3822623SN/A{ 3832623SN/A#if 0 3842623SN/A static bool no_warn = true; 3852623SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3862623SN/A // Only support block sizes of 64 atm. 3872623SN/A assert(blk_size == 64); 3882SN/A int offset = src & (blk_size - 1); 3892683Sktlim@umich.edu 3902427SN/A // Make sure block doesn't span page 3912683Sktlim@umich.edu if (no_warn && 3922427SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 3932SN/A (src >> 40) != 0xfffffc) { 3942623SN/A warn("Copied block source spans pages %x.", src); 3952623SN/A no_warn = false; 3967897Shestness@cs.utexas.edu } 3972SN/A 3982623SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 3992623SN/A 4004377Sgblack@eecs.umich.edu // translate to physical address Fault fault = cpuXC->translateDataReadReq(req); 4017720Sgblack@eecs.umich.edu 4024377Sgblack@eecs.umich.edu if (fault == NoFault) { 4037720Sgblack@eecs.umich.edu cpuXC->copySrcAddr = src; 4045665Sgblack@eecs.umich.edu cpuXC->copySrcPhysAddr = memReq->paddr + offset; 4057720Sgblack@eecs.umich.edu } else { 4067720Sgblack@eecs.umich.edu assert(!fault->isAlignmentFault()); 4075665Sgblack@eecs.umich.edu 4085665Sgblack@eecs.umich.edu cpuXC->copySrcAddr = 0; 4094181Sgblack@eecs.umich.edu cpuXC->copySrcPhysAddr = 0; 4104181Sgblack@eecs.umich.edu } 4119023Sgblack@eecs.umich.edu return fault; 4129023Sgblack@eecs.umich.edu#else 4134181Sgblack@eecs.umich.edu return No_Fault; 4144182Sgblack@eecs.umich.edu#endif 4157720Sgblack@eecs.umich.edu} 4169023Sgblack@eecs.umich.edu 4179023Sgblack@eecs.umich.eduFault 4184593Sgblack@eecs.umich.eduSimpleCPU::copy(Addr dest) 4199023Sgblack@eecs.umich.edu{ 4204377Sgblack@eecs.umich.edu#if 0 4219023Sgblack@eecs.umich.edu static bool no_warn = true; 4224377Sgblack@eecs.umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 4239023Sgblack@eecs.umich.edu // Only support block sizes of 64 atm. 4249023Sgblack@eecs.umich.edu assert(blk_size == 64); 4254377Sgblack@eecs.umich.edu uint8_t data[blk_size]; 4267720Sgblack@eecs.umich.edu //assert(cpuXC->copySrcAddr); 4274377Sgblack@eecs.umich.edu int offset = dest & (blk_size - 1); 4284377Sgblack@eecs.umich.edu 4294377Sgblack@eecs.umich.edu // Make sure block doesn't span page 4304377Sgblack@eecs.umich.edu if (no_warn && 4314181Sgblack@eecs.umich.edu (dest & PageMask) != ((dest + blk_size) & PageMask) && 4324181Sgblack@eecs.umich.edu (dest >> 40) != 0xfffffc) { 4334181Sgblack@eecs.umich.edu no_warn = false; 4344539Sgblack@eecs.umich.edu warn("Copied block destination spans pages %x. ", dest); 4353276Sgblack@eecs.umich.edu } 4367720Sgblack@eecs.umich.edu 4373280Sgblack@eecs.umich.edu memReq->reset(dest & ~(blk_size -1), blk_size); 4383280Sgblack@eecs.umich.edu // translate to physical address 4393276Sgblack@eecs.umich.edu Fault fault = cpuXC->translateDataWriteReq(req); 4403276Sgblack@eecs.umich.edu 4413276Sgblack@eecs.umich.edu if (fault == NoFault) { 4427720Sgblack@eecs.umich.edu Addr dest_addr = memReq->paddr + offset; 4433276Sgblack@eecs.umich.edu // Need to read straight from memory since we have more than 8 bytes. 4443276Sgblack@eecs.umich.edu memReq->paddr = cpuXC->copySrcPhysAddr; 4454181Sgblack@eecs.umich.edu cpuXC->mem->read(memReq, data); 4468955Sgblack@eecs.umich.edu memReq->paddr = dest_addr; 4474522Ssaidi@eecs.umich.edu cpuXC->mem->write(memReq, data); 4487823Ssteve.reinhardt@amd.com if (dcacheInterface) { 4497720Sgblack@eecs.umich.edu memReq->cmd = Copy; 4502470SN/A memReq->completionEvent = NULL; 4518955Sgblack@eecs.umich.edu memReq->paddr = cpuXC->copySrcPhysAddr; 4524181Sgblack@eecs.umich.edu memReq->dest = dest_addr; 4534522Ssaidi@eecs.umich.edu memReq->size = 64; 4544181Sgblack@eecs.umich.edu memReq->time = curTick; 45510061Sandreas@sandberg.pp.se memReq->flags &= ~INST_READ; 45610061Sandreas@sandberg.pp.se dcacheInterface->access(memReq); 45710061Sandreas@sandberg.pp.se } 45810061Sandreas@sandberg.pp.se } 45910061Sandreas@sandberg.pp.se else 46010061Sandreas@sandberg.pp.se assert(!fault->isAlignmentFault()); 46110061Sandreas@sandberg.pp.se 46210061Sandreas@sandberg.pp.se return fault; 46310061Sandreas@sandberg.pp.se#else 46410061Sandreas@sandberg.pp.se panic("copy not implemented"); 46510061Sandreas@sandberg.pp.se return No_Fault; 46610061Sandreas@sandberg.pp.se#endif 46710061Sandreas@sandberg.pp.se} 4682623SN/A 4692623SN/A// precise architected memory state accessor macros 4702623SN/Atemplate <class T> 4712623SN/AFault 4722623SN/ASimpleCPU::read(Addr addr, T &data, unsigned flags) 4737720Sgblack@eecs.umich.edu{ 4747720Sgblack@eecs.umich.edu if (status() == DcacheWaitResponse || status() == DcacheWaitSwitch) { 4757720Sgblack@eecs.umich.edu// Fault fault = xc->read(memReq,data); 4767720Sgblack@eecs.umich.edu // Not sure what to check for no fault... 4778780Sgblack@eecs.umich.edu if (data_read_pkt->result == Success) { 4783577Sgblack@eecs.umich.edu memcpy(&data, data_read_pkt->data, sizeof(T)); 4797720Sgblack@eecs.umich.edu } 4805086Sgblack@eecs.umich.edu 4812623SN/A if (traceData) { 4822683Sktlim@umich.edu traceData->setAddr(addr); 4832623SN/A } 4842SN/A 4852623SN/A // @todo: Figure out a way to create a Fault from the packet result. 4862623SN/A return No_Fault; 4872SN/A } 4882SN/A 4892623SN/A// memReq->reset(addr, sizeof(T), flags); 4902623SN/A 4912623SN/A#if SIMPLE_CPU_MEM_TIMING 4922623SN/A CpuRequest *data_read_req = new CpuRequest; 4932SN/A#endif 4945953Ssaidi@eecs.umich.edu 4957720Sgblack@eecs.umich.edu data_read_req->vaddr = addr; 4965953Ssaidi@eecs.umich.edu data_read_req->size = sizeof(T); 4975953Ssaidi@eecs.umich.edu data_read_req->flags = flags; 49810061Sandreas@sandberg.pp.se data_read_req->time = curTick; 49910061Sandreas@sandberg.pp.se 50010061Sandreas@sandberg.pp.se // translate to physical address 50110061Sandreas@sandberg.pp.se Fault fault = cpuXC->translateDataReadReq(data_read_req); 5027897Shestness@cs.utexas.edu 5037897Shestness@cs.utexas.edu // Now do the access. 5047897Shestness@cs.utexas.edu if (fault == No_Fault) { 5057897Shestness@cs.utexas.edu#if SIMPLE_CPU_MEM_TIMING 5067897Shestness@cs.utexas.edu data_read_pkt = new Packet; 5077897Shestness@cs.utexas.edu data_read_pkt->cmd = Read; 5087897Shestness@cs.utexas.edu data_read_pkt->req = data_read_req; 5097897Shestness@cs.utexas.edu data_read_pkt->data = new uint8_t[8]; 5107897Shestness@cs.utexas.edu#endif 5117897Shestness@cs.utexas.edu data_read_pkt->addr = data_read_req->paddr; 5127897Shestness@cs.utexas.edu data_read_pkt->size = sizeof(T); 5137897Shestness@cs.utexas.edu 5147897Shestness@cs.utexas.edu sendDcacheRequest(data_read_pkt); 5157897Shestness@cs.utexas.edu 5167897Shestness@cs.utexas.edu#if SIMPLE_CPU_MEM_IMMEDIATE 5177897Shestness@cs.utexas.edu // Need to find a way to not duplicate code above. 5187897Shestness@cs.utexas.edu 5197897Shestness@cs.utexas.edu if (data_read_pkt->result == Success) { 5207897Shestness@cs.utexas.edu memcpy(&data, data_read_pkt->data, sizeof(T)); 5217897Shestness@cs.utexas.edu } 5227897Shestness@cs.utexas.edu 5237897Shestness@cs.utexas.edu if (traceData) { 5247897Shestness@cs.utexas.edu traceData->setAddr(addr); 5257897Shestness@cs.utexas.edu } 5267897Shestness@cs.utexas.edu 5277897Shestness@cs.utexas.edu // @todo: Figure out a way to create a Fault from the packet result. 5287897Shestness@cs.utexas.edu return No_Fault; 5297897Shestness@cs.utexas.edu#endif 5307897Shestness@cs.utexas.edu } 5317897Shestness@cs.utexas.edu/* 5327897Shestness@cs.utexas.edu memReq->cmd = Read; 5337897Shestness@cs.utexas.edu memReq->completionEvent = NULL; 5347897Shestness@cs.utexas.edu memReq->time = curTick; 5358780Sgblack@eecs.umich.edu memReq->flags &= ~INST_READ; 5368780Sgblack@eecs.umich.edu MemAccessResult result = dcacheInterface->access(memReq); 5372644Sstever@eecs.umich.edu 5382644Sstever@eecs.umich.edu // Ugly hack to get an event scheduled *only* if the access is 5394046Sbinkertn@umich.edu // a miss. We really should add first-class support for this 5404046Sbinkertn@umich.edu // at some point. 5414046Sbinkertn@umich.edu if (result != MA_HIT && dcacheInterface->doEvents()) { 5422644Sstever@eecs.umich.edu memReq->completionEvent = &cacheCompletionEvent; 5432623SN/A lastDcacheStall = curTick; 5442SN/A unscheduleTickEvent(); 5452623SN/A _status = DcacheMissStall; 5462623SN/A } else { 5472623SN/A // do functional access 54810061Sandreas@sandberg.pp.se fault = cpuXC->read(memReq, data); 54910061Sandreas@sandberg.pp.se 5504377Sgblack@eecs.umich.edu } 5514377Sgblack@eecs.umich.edu } else if(fault == NoFault) { 5522090SN/A // do functional access 5533905Ssaidi@eecs.umich.edu fault = cpuXC->read(memReq, data); 5547678Sgblack@eecs.umich.edu 5559023Sgblack@eecs.umich.edu } 5564377Sgblack@eecs.umich.edu*/ 5577720Sgblack@eecs.umich.edu // This will need a new way to tell if it has a dcache attached. 5587720Sgblack@eecs.umich.edu if (data_read_req->flags & UNCACHEABLE) 5597720Sgblack@eecs.umich.edu recordEvent("Uncached Read"); 5607720Sgblack@eecs.umich.edu 5617720Sgblack@eecs.umich.edu return fault; 5627720Sgblack@eecs.umich.edu} 5633276Sgblack@eecs.umich.edu 5642SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 56510061Sandreas@sandberg.pp.se 56610061Sandreas@sandberg.pp.setemplate 56710061Sandreas@sandberg.pp.seFault 56810061Sandreas@sandberg.pp.seSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 56910061Sandreas@sandberg.pp.se 57010061Sandreas@sandberg.pp.setemplate 57110061Sandreas@sandberg.pp.seFault 57210061Sandreas@sandberg.pp.seSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 57310061Sandreas@sandberg.pp.se 57410061Sandreas@sandberg.pp.setemplate 57510061Sandreas@sandberg.pp.seFault 57610061Sandreas@sandberg.pp.seSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 57710061Sandreas@sandberg.pp.se 57810061Sandreas@sandberg.pp.setemplate 57910061Sandreas@sandberg.pp.seFault 58010061Sandreas@sandberg.pp.seSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 58110061Sandreas@sandberg.pp.se 5822SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5832SN/A 5849461Snilay@cs.wisc.edutemplate<> 5859461Snilay@cs.wisc.eduFault 5869461Snilay@cs.wisc.eduSimpleCPU::read(Addr addr, double &data, unsigned flags) 5879461Snilay@cs.wisc.edu{ 5889461Snilay@cs.wisc.edu return read(addr, *(uint64_t*)&data, flags); 5899461Snilay@cs.wisc.edu} 590 591template<> 592Fault 593SimpleCPU::read(Addr addr, float &data, unsigned flags) 594{ 595 return read(addr, *(uint32_t*)&data, flags); 596} 597 598 599template<> 600Fault 601SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 602{ 603 return read(addr, (uint32_t&)data, flags); 604} 605 606 607template <class T> 608Fault 609SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 610{ 611 data_write_req->vaddr = addr; 612 data_write_req->time = curTick; 613 data_write_req->size = sizeof(T); 614 data_write_req->flags = flags; 615 616 // translate to physical address 617 Fault fault = cpuXC->translateDataWriteReq(data_write_req); 618 // Now do the access. 619 if (fault == No_Fault) { 620#if SIMPLE_CPU_MEM_TIMING 621 data_write_pkt = new Packet; 622 data_write_pkt->cmd = Write; 623 data_write_pkt->req = data_write_req; 624 data_write_pkt->data = new uint8_t[64]; 625 memcpy(data_write_pkt->data, &data, sizeof(T)); 626#else 627 data_write_pkt->data = (uint8_t *)&data; 628#endif 629 data_write_pkt->addr = data_write_req->paddr; 630 data_write_pkt->size = sizeof(T); 631 632 sendDcacheRequest(data_write_pkt); 633 } 634 635/* 636 // do functional access 637 if (fault == NoFault) 638 fault = cpuXC->write(memReq, data); 639 640 if (fault == NoFault && dcacheInterface) { 641 memReq->cmd = Write; 642 memcpy(memReq->data,(uint8_t *)&data,memReq->size); 643 memReq->completionEvent = NULL; 644 memReq->time = curTick; 645 memReq->flags &= ~INST_READ; 646 MemAccessResult result = dcacheInterface->access(memReq); 647 648 // Ugly hack to get an event scheduled *only* if the access is 649 // a miss. We really should add first-class support for this 650 // at some point. 651 if (result != MA_HIT && dcacheInterface->doEvents()) { 652 memReq->completionEvent = &cacheCompletionEvent; 653 lastDcacheStall = curTick; 654 unscheduleTickEvent(); 655 _status = DcacheMissStall; 656 } 657 } 658*/ 659 if (res && (fault == NoFault)) 660 *res = data_write_pkt->result; 661 662 // This will need a new way to tell if it's hooked up to a cache or not. 663 if (data_write_req->flags & UNCACHEABLE) 664 recordEvent("Uncached Write"); 665 666 // If the write needs to have a fault on the access, consider calling 667 // changeStatus() and changing it to "bad addr write" or something. 668 return fault; 669} 670 671 672#ifndef DOXYGEN_SHOULD_SKIP_THIS 673template 674Fault 675SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 676 677template 678Fault 679SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 680 681template 682Fault 683SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 684 685template 686Fault 687SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 688 689#endif //DOXYGEN_SHOULD_SKIP_THIS 690 691template<> 692Fault 693SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 694{ 695 return write(*(uint64_t*)&data, addr, flags, res); 696} 697 698template<> 699Fault 700SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 701{ 702 return write(*(uint32_t*)&data, addr, flags, res); 703} 704 705 706template<> 707Fault 708SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 709{ 710 return write((uint32_t)data, addr, flags, res); 711} 712 713 714#if FULL_SYSTEM 715Addr 716SimpleCPU::dbg_vtophys(Addr addr) 717{ 718 return vtophys(xcProxy, addr); 719} 720#endif // FULL_SYSTEM 721 722void 723SimpleCPU::sendIcacheRequest(Packet *pkt) 724{ 725 assert(!tickEvent.scheduled()); 726#if SIMPLE_CPU_MEM_TIMING 727 retry_pkt = pkt; 728 bool success = icachePort.sendTiming(*pkt); 729 730 unscheduleTickEvent(); 731 732 lastIcacheStall = curTick; 733 734 if (!success) { 735 // Need to wait for retry 736 _status = IcacheRetry; 737 } else { 738 // Need to wait for cache to respond 739 _status = IcacheWaitResponse; 740 } 741#elif SIMPLE_CPU_MEM_ATOMIC 742 Tick latency = icachePort.sendAtomic(*pkt); 743 744 unscheduleTickEvent(); 745 scheduleTickEvent(latency); 746 747 // Note that Icache miss cycles will be incorrect. Unless 748 // we check the status of the packet sent (is this valid?), 749 // we won't know if the latency is a hit or a miss. 750 icacheStallCycles += latency; 751 752 _status = IcacheAccessComplete; 753#elif SIMPLE_CPU_MEM_IMMEDIATE 754 icachePort.sendAtomic(*pkt); 755#else 756#error "SimpleCPU has no mem model set" 757#endif 758} 759 760void 761SimpleCPU::sendDcacheRequest(Packet *pkt) 762{ 763 assert(!tickEvent.scheduled()); 764#if SIMPLE_CPU_MEM_TIMING 765 unscheduleTickEvent(); 766 767 retry_pkt = pkt; 768 bool success = dcachePort.sendTiming(*pkt); 769 770 lastDcacheStall = curTick; 771 772 if (!success) { 773 _status = DcacheRetry; 774 } else { 775 _status = DcacheWaitResponse; 776 } 777#elif SIMPLE_CPU_MEM_ATOMIC 778 unscheduleTickEvent(); 779 780 Tick latency = dcachePort.sendAtomic(*pkt); 781 782 scheduleTickEvent(latency); 783 784 // Note that Dcache miss cycles will be incorrect. Unless 785 // we check the status of the packet sent (is this valid?), 786 // we won't know if the latency is a hit or a miss. 787 dcacheStallCycles += latency; 788#elif SIMPLE_CPU_MEM_IMMEDIATE 789 dcachePort.sendAtomic(*pkt); 790#else 791#error "SimpleCPU has no mem model set" 792#endif 793} 794 795void 796SimpleCPU::processResponse(Packet &response) 797{ 798 assert(SIMPLE_CPU_MEM_TIMING); 799 800 // For what things is the CPU the consumer of the packet it sent 801 // out? This may create a memory leak if that's the case and it's 802 // expected of the SimpleCPU to delete its own packet. 803 Packet *pkt = &response; 804 805 switch (status()) { 806 case IcacheWaitResponse: 807 icacheStallCycles += curTick - lastIcacheStall; 808 809 _status = IcacheAccessComplete; 810 scheduleTickEvent(1); 811 812 // Copy the icache data into the instruction itself. 813 memcpy(&inst, pkt->data, sizeof(inst)); 814 815 delete pkt; 816 break; 817 case DcacheWaitResponse: 818 if (pkt->cmd == Read) { 819 curStaticInst->execute(this,traceData); 820 if (traceData) 821 traceData->finalize(); 822 } 823 824 delete pkt; 825 826 dcacheStallCycles += curTick - lastDcacheStall; 827 _status = Running; 828 scheduleTickEvent(1); 829 break; 830 case DcacheWaitSwitch: 831 if (pkt->cmd == Read) { 832 curStaticInst->execute(this,traceData); 833 if (traceData) 834 traceData->finalize(); 835 } 836 837 delete pkt; 838 839 _status = SwitchedOut; 840 sampler->signalSwitched(); 841 case SwitchedOut: 842 // If this CPU has been switched out due to sampling/warm-up, 843 // ignore any further status changes (e.g., due to cache 844 // misses outstanding at the time of the switch). 845 delete pkt; 846 847 return; 848 default: 849 panic("SimpleCPU::processCacheCompletion: bad state"); 850 break; 851 } 852} 853 854Packet * 855SimpleCPU::processRetry() 856{ 857#if SIMPLE_CPU_MEM_TIMING 858 switch(status()) { 859 case IcacheRetry: 860 icacheRetryCycles += curTick - lastIcacheStall; 861 return retry_pkt; 862 break; 863 case DcacheRetry: 864 dcacheRetryCycles += curTick - lastDcacheStall; 865 return retry_pkt; 866 break; 867 default: 868 panic("SimpleCPU::processRetry: bad state"); 869 break; 870 } 871#else 872 panic("shouldn't be here"); 873#endif 874} 875 876#if FULL_SYSTEM 877void 878SimpleCPU::post_interrupt(int int_num, int index) 879{ 880 BaseCPU::post_interrupt(int_num, index); 881 882 if (cpuXC->status() == ExecContext::Suspended) { 883 DPRINTF(IPI,"Suspended Processor awoke\n"); 884 cpuXC->activate(); 885 } 886} 887#endif // FULL_SYSTEM 888 889/* start simulation, program loaded, processor precise state initialized */ 890void 891SimpleCPU::tick() 892{ 893 numCycles++; 894 895 traceData = NULL; 896 897 Fault fault = NoFault; 898 899#if FULL_SYSTEM 900 if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && 901 status() != IcacheMissComplete) { 902 int ipl = 0; 903 int summary = 0; 904 checkInterrupts = false; 905 906 if (cpuXC->readMiscReg(IPR_SIRR)) { 907 for (int i = INTLEVEL_SOFTWARE_MIN; 908 i < INTLEVEL_SOFTWARE_MAX; i++) { 909 if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 910 // See table 4-19 of 21164 hardware reference 911 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 912 summary |= (ULL(1) << i); 913 } 914 } 915 } 916 917 uint64_t interrupts = cpuXC->cpu->intr_status(); 918 for (int i = INTLEVEL_EXTERNAL_MIN; 919 i < INTLEVEL_EXTERNAL_MAX; i++) { 920 if (interrupts & (ULL(1) << i)) { 921 // See table 4-19 of 21164 hardware reference 922 ipl = i; 923 summary |= (ULL(1) << i); 924 } 925 } 926 927 if (cpuXC->readMiscReg(IPR_ASTRR)) 928 panic("asynchronous traps not implemented\n"); 929 930 if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) { 931 cpuXC->setMiscReg(IPR_ISR, summary); 932 cpuXC->setMiscReg(IPR_INTID, ipl); 933 934 Fault(new InterruptFault)->invoke(xcProxy); 935 936 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 937 cpuXC->readMiscReg(IPR_IPLR), ipl, summary); 938 } 939 } 940#endif 941 942 // maintain $r0 semantics 943 cpuXC->setIntReg(ZeroReg, 0); 944#ifdef TARGET_ALPHA 945 cpuXC->setFloatRegDouble(ZeroReg, 0.0); 946#endif // TARGET_ALPHA 947 948 if (status() == IcacheAccessComplete) { 949 // We've already fetched an instruction and were stalled on an 950 // I-cache miss. No need to fetch it again. 951 952 // Set status to running; tick event will get rescheduled if 953 // necessary at end of tick() function. 954 _status = Running; 955 } else { 956 // Try to fetch an instruction 957 958 // set up memory request for instruction fetch 959#if FULL_SYSTEM 960#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 961#else 962#define IFETCH_FLAGS(pc) 0 963#endif 964 965#if SIMPLE_CPU_MEM_TIMING 966 CpuRequest *ifetch_req = new CpuRequest(); 967 ifetch_req->size = sizeof(MachInst); 968#endif 969 970 ifetch_req->vaddr = cpuXC->readPC() & ~3; 971 ifetch_req->time = curTick; 972 973/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 974 IFETCH_FLAGS(xc->regs.pc)); 975*/ 976 977 fault = xc->translateInstReq(ifetch_req); 978 979 if (fault == NoFault) { 980#if SIMPLE_CPU_MEM_TIMING 981 Packet *ifetch_pkt = new Packet; 982 ifetch_pkt->cmd = Read; 983 ifetch_pkt->data = (uint8_t *)&inst; 984 ifetch_pkt->req = ifetch_req; 985 ifetch_pkt->size = sizeof(MachInst); 986#endif 987 ifetch_pkt->addr = ifetch_req->paddr; 988 989 sendIcacheRequest(ifetch_pkt); 990#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC 991 return; 992#endif 993/* 994 if (icacheInterface && fault == NoFault) { 995 memReq->completionEvent = NULL; 996 997 memReq->time = curTick; 998 memReq->flags |= INST_READ; 999 MemAccessResult result = icacheInterface->access(memReq); 1000 1001 // Ugly hack to get an event scheduled *only* if the access is 1002 // a miss. We really should add first-class support for this 1003 // at some point. 1004 if (result != MA_HIT && icacheInterface->doEvents()) { 1005 memReq->completionEvent = &cacheCompletionEvent; 1006 lastIcacheStall = curTick; 1007 unscheduleTickEvent(); 1008 _status = IcacheMissStall; 1009 return; 1010 } 1011 } 1012*/ 1013 } 1014 } 1015 1016 // If we've got a valid instruction (i.e., no fault on instruction 1017 // fetch), then execute it. 1018 if (fault == NoFault) { 1019 1020 // keep an instruction count 1021 numInst++; 1022 numInsts++; 1023 1024 // check for instruction-count-based events 1025 comInstEventQueue[0]->serviceEvents(numInst); 1026 1027 // decode the instruction 1028 inst = gtoh(inst); 1029 curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC())); 1030 1031 traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, 1032 cpuXC->readPC()); 1033 1034#if FULL_SYSTEM 1035 cpuXC->setInst(inst); 1036#endif // FULL_SYSTEM 1037 1038 cpuXC->func_exe_inst++; 1039 1040 fault = curStaticInst->execute(this, traceData); 1041 1042#if FULL_SYSTEM 1043 if (system->kernelBinning->fnbin) { 1044 assert(kernelStats); 1045 system->kernelBinning->execute(xcProxy, inst); 1046 } 1047 1048 if (cpuXC->profile) { 1049 bool usermode = 1050 (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 1051 cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); 1052 ProfileNode *node = cpuXC->profile->consume(xcProxy, inst); 1053 if (node) 1054 cpuXC->profileNode = node; 1055 } 1056#endif 1057 1058 if (curStaticInst->isMemRef()) { 1059 numMemRefs++; 1060 } 1061 1062 if (curStaticInst->isLoad()) { 1063 ++numLoad; 1064 comLoadEventQueue[0]->serviceEvents(numLoad); 1065 } 1066 1067 // If we have a dcache miss, then we can't finialize the instruction 1068 // trace yet because we want to populate it with the data later 1069 if (traceData && (status() != DcacheWaitResponse)) { 1070 traceData->finalize(); 1071 } 1072 1073 traceFunctions(cpuXC->readPC()); 1074 1075 } // if (fault == NoFault) 1076 1077 if (fault != NoFault) { 1078#if FULL_SYSTEM 1079 fault->invoke(xcProxy); 1080#else // !FULL_SYSTEM 1081 fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC()); 1082#endif // FULL_SYSTEM 1083 } 1084 else { 1085#if THE_ISA != MIPS_ISA 1086 // go to the next instruction 1087 cpuXC->setPC(cpuXC->readNextPC()); 1088 cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); 1089#else 1090 // go to the next instruction 1091 cpuXC->setPC(cpuXC->readNextPC()); 1092 cpuXC->setNextPC(cpuXC->readNextNPC()); 1093 cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); 1094#endif 1095 1096 } 1097 1098#if FULL_SYSTEM 1099 Addr oldpc; 1100 do { 1101 oldpc = cpuXC->readPC(); 1102 system->pcEventQueue.service(xcProxy); 1103 } while (oldpc != cpuXC->readPC()); 1104#endif 1105 1106 assert(status() == Running || 1107 status() == Idle || 1108 status() == DcacheWaitResponse); 1109 1110 if (status() == Running && !tickEvent.scheduled()) 1111 tickEvent.schedule(curTick + cycles(1)); 1112} 1113 1114//////////////////////////////////////////////////////////////////////// 1115// 1116// SimpleCPU Simulation Object 1117// 1118BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 1119 1120 Param<Counter> max_insts_any_thread; 1121 Param<Counter> max_insts_all_threads; 1122 Param<Counter> max_loads_any_thread; 1123 Param<Counter> max_loads_all_threads; 1124 1125#if FULL_SYSTEM 1126 SimObjectParam<AlphaITB *> itb; 1127 SimObjectParam<AlphaDTB *> dtb; 1128 SimObjectParam<System *> system; 1129 Param<int> cpu_id; 1130 Param<Tick> profile; 1131#else 1132 SimObjectParam<Memory *> mem; 1133 SimObjectParam<Process *> workload; 1134#endif // FULL_SYSTEM 1135 1136 Param<int> clock; 1137 1138 Param<bool> defer_registration; 1139 Param<int> width; 1140 Param<bool> function_trace; 1141 Param<Tick> function_trace_start; 1142 1143END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 1144 1145BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 1146 1147 INIT_PARAM(max_insts_any_thread, 1148 "terminate when any thread reaches this inst count"), 1149 INIT_PARAM(max_insts_all_threads, 1150 "terminate when all threads have reached this inst count"), 1151 INIT_PARAM(max_loads_any_thread, 1152 "terminate when any thread reaches this load count"), 1153 INIT_PARAM(max_loads_all_threads, 1154 "terminate when all threads have reached this load count"), 1155 1156#if FULL_SYSTEM 1157 INIT_PARAM(itb, "Instruction TLB"), 1158 INIT_PARAM(dtb, "Data TLB"), 1159 INIT_PARAM(system, "system object"), 1160 INIT_PARAM(cpu_id, "processor ID"), 1161 INIT_PARAM(profile, ""), 1162#else 1163 INIT_PARAM(mem, "memory"), 1164 INIT_PARAM(workload, "processes to run"), 1165#endif // FULL_SYSTEM 1166 1167 INIT_PARAM(clock, "clock speed"), 1168 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 1169 INIT_PARAM(width, "cpu width"), 1170 INIT_PARAM(function_trace, "Enable function trace"), 1171 INIT_PARAM(function_trace_start, "Cycle to start function trace") 1172 1173END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 1174 1175 1176CREATE_SIM_OBJECT(SimpleCPU) 1177{ 1178 SimpleCPU::Params *params = new SimpleCPU::Params(); 1179 params->name = getInstanceName(); 1180 params->numberOfThreads = 1; 1181 params->max_insts_any_thread = max_insts_any_thread; 1182 params->max_insts_all_threads = max_insts_all_threads; 1183 params->max_loads_any_thread = max_loads_any_thread; 1184 params->max_loads_all_threads = max_loads_all_threads; 1185 params->deferRegistration = defer_registration; 1186 params->clock = clock; 1187 params->functionTrace = function_trace; 1188 params->functionTraceStart = function_trace_start; 1189 params->width = width; 1190 1191#if FULL_SYSTEM 1192 params->itb = itb; 1193 params->dtb = dtb; 1194 params->system = system; 1195 params->cpu_id = cpu_id; 1196 params->profile = profile; 1197#else 1198 params->mem = mem; 1199 params->process = workload; 1200#endif 1201 1202 SimpleCPU *cpu = new SimpleCPU(params); 1203 return cpu; 1204} 1205 1206REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 1207 1208