base.cc revision 2251
1360SN/A/* 21458SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#include <cmath> 30360SN/A#include <cstdio> 31360SN/A#include <cstdlib> 322093SN/A#include <iostream> 33360SN/A#include <iomanip> 34360SN/A#include <list> 35360SN/A#include <sstream> 36360SN/A#include <string> 37360SN/A 38360SN/A#include "base/cprintf.hh" 392474SN/A#include "base/inifile.hh" 40360SN/A#include "base/loader/symtab.hh" 416658Snate@binkert.org#include "base/misc.hh" 422680Sktlim@umich.edu#include "base/pollevent.hh" 431717SN/A#include "base/range.hh" 442474SN/A#include "base/stats/events.hh" 45360SN/A#include "base/trace.hh" 466029Ssteve.reinhardt@amd.com#include "cpu/base.hh" 472667Sstever@eecs.umich.edu#include "cpu/exec_context.hh" 48360SN/A#include "cpu/exetrace.hh" 49360SN/A#include "cpu/profile.hh" 502107SN/A#include "cpu/sampler/sampler.hh" 51360SN/A#include "cpu/simple/cpu.hh" 52360SN/A#include "cpu/smt.hh" 533114Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 54360SN/A#include "kern/kernel_stats.hh" 556702Sgblack@eecs.umich.edu#include "mem/base_mem.hh" 566701Sgblack@eecs.umich.edu#include "mem/mem_interface.hh" 576702Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 586111Ssteve.reinhardt@amd.com#include "sim/builder.hh" 596111Ssteve.reinhardt@amd.com#include "sim/debug.hh" 606111Ssteve.reinhardt@amd.com#include "sim/host.hh" 616701Sgblack@eecs.umich.edu#include "sim/sim_events.hh" 626701Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 636701Sgblack@eecs.umich.edu#include "sim/stats.hh" 646701Sgblack@eecs.umich.edu 65360SN/A#if FULL_SYSTEM 662680Sktlim@umich.edu#include "base/remote_gdb.hh" 67360SN/A#include "mem/functional/memory_control.hh" 682495SN/A#include "mem/functional/physical.hh" 692680Sktlim@umich.edu#include "sim/system.hh" 70360SN/A#include "arch/tlb.hh" 711450SN/A#include "arch/stacktrace.hh" 725958Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 73360SN/A#else // !FULL_SYSTEM 74360SN/A#include "mem/functional/functional.hh" 75360SN/A#endif // FULL_SYSTEM 761450SN/A 773114Sgblack@eecs.umich.eduusing namespace std; 782680Sktlim@umich.edu//The SimpleCPU does alpha only 79360SN/Ausing namespace AlphaISA; 801969SN/A 812484SN/A 822484SN/ASimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) 83360SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) 84360SN/A{ 85360SN/A} 861450SN/A 873114Sgblack@eecs.umich.edu 882680Sktlim@umich.eduvoid 89360SN/ASimpleCPU::init() 906701Sgblack@eecs.umich.edu{ 911969SN/A BaseCPU::init(); 926701Sgblack@eecs.umich.edu#if FULL_SYSTEM 93360SN/A for (int i = 0; i < execContexts.size(); ++i) { 941458SN/A ExecContext *xc = execContexts[i]; 95360SN/A 96360SN/A // initialize CPU, including PC 97360SN/A TheISA::initCPU(&xc->regs, xc->cpu_id); 981450SN/A } 993114Sgblack@eecs.umich.edu#endif 1002680Sktlim@umich.edu} 101360SN/A 1026029Ssteve.reinhardt@amd.comvoid 1036029Ssteve.reinhardt@amd.comSimpleCPU::TickEvent::process() 1046701Sgblack@eecs.umich.edu{ 1055958Sgblack@eecs.umich.edu int count = width; 1066701Sgblack@eecs.umich.edu do { 1076029Ssteve.reinhardt@amd.com cpu->tick(); 1086029Ssteve.reinhardt@amd.com } while (--count > 0 && cpu->status() == Running); 1096029Ssteve.reinhardt@amd.com} 1102834Sksewell@umich.edu 111360SN/Aconst char * 1121458SN/ASimpleCPU::TickEvent::description() 113360SN/A{ 114360SN/A return "SimpleCPU tick event"; 115360SN/A} 1161450SN/A 1176109Ssanchezd@stanford.edu 1186109Ssanchezd@stanford.eduSimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) 1196109Ssanchezd@stanford.edu : Event(&mainEventQueue), cpu(_cpu) 1206109Ssanchezd@stanford.edu{ 1216109Ssanchezd@stanford.edu} 1226701Sgblack@eecs.umich.edu 1236109Ssanchezd@stanford.eduvoid SimpleCPU::CacheCompletionEvent::process() 1246701Sgblack@eecs.umich.edu{ 1256109Ssanchezd@stanford.edu cpu->processCacheCompletion(); 1266109Ssanchezd@stanford.edu} 1276109Ssanchezd@stanford.edu 1286109Ssanchezd@stanford.educonst char * 1296109Ssanchezd@stanford.eduSimpleCPU::CacheCompletionEvent::description() 1306109Ssanchezd@stanford.edu{ 1313114Sgblack@eecs.umich.edu return "SimpleCPU cache completion event"; 132360SN/A} 1332107SN/A 134360SN/ASimpleCPU::SimpleCPU(Params *p) 135360SN/A : BaseCPU(p), tickEvent(this, p->width), xc(NULL), 136360SN/A cacheCompletionEvent(this) 1371450SN/A{ 1385748SSteve.Reinhardt@amd.com _status = Idle; 139360SN/A#if FULL_SYSTEM 140360SN/A xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); 1416701Sgblack@eecs.umich.edu 1426701Sgblack@eecs.umich.edu#else 1435748SSteve.Reinhardt@amd.com xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); 1445748SSteve.Reinhardt@amd.com#endif // !FULL_SYSTEM 1455748SSteve.Reinhardt@amd.com 1465748SSteve.Reinhardt@amd.com icacheInterface = p->icache_interface; 1475748SSteve.Reinhardt@amd.com dcacheInterface = p->dcache_interface; 1485748SSteve.Reinhardt@amd.com 1495748SSteve.Reinhardt@amd.com memReq = new MemReq(); 1505748SSteve.Reinhardt@amd.com memReq->xc = xc; 1512474SN/A memReq->asid = 0; 1522474SN/A memReq->data = new uint8_t[64]; 1535748SSteve.Reinhardt@amd.com 1542474SN/A numInst = 0; 1552474SN/A startNumInst = 0; 1566687Stjones1@inf.ed.ac.uk numLoad = 0; 1576687Stjones1@inf.ed.ac.uk startNumLoad = 0; 1586687Stjones1@inf.ed.ac.uk lastIcacheStall = 0; 1596687Stjones1@inf.ed.ac.uk lastDcacheStall = 0; 1606687Stjones1@inf.ed.ac.uk 1616687Stjones1@inf.ed.ac.uk execContexts.push_back(xc); 1626687Stjones1@inf.ed.ac.uk} 1636687Stjones1@inf.ed.ac.uk 1646687Stjones1@inf.ed.ac.ukSimpleCPU::~SimpleCPU() 1656687Stjones1@inf.ed.ac.uk{ 1666687Stjones1@inf.ed.ac.uk} 1676687Stjones1@inf.ed.ac.uk 1686687Stjones1@inf.ed.ac.ukvoid 1696687Stjones1@inf.ed.ac.ukSimpleCPU::switchOut(Sampler *s) 1706687Stjones1@inf.ed.ac.uk{ 1716687Stjones1@inf.ed.ac.uk sampler = s; 1726687Stjones1@inf.ed.ac.uk if (status() == DcacheMissStall) { 1736687Stjones1@inf.ed.ac.uk DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n"); 1742474SN/A _status = DcacheMissSwitch; 1751450SN/A } 1765748SSteve.Reinhardt@amd.com else { 1775748SSteve.Reinhardt@amd.com _status = SwitchedOut; 1781458SN/A 1791458SN/A if (tickEvent.scheduled()) 180360SN/A tickEvent.squash(); 181360SN/A 182360SN/A sampler->signalSwitched(); 1831450SN/A } 1843114Sgblack@eecs.umich.edu} 185360SN/A 1866701Sgblack@eecs.umich.edu 1876701Sgblack@eecs.umich.eduvoid 1881970SN/ASimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1891970SN/A{ 1901970SN/A BaseCPU::takeOverFrom(oldCPU); 1911970SN/A 192360SN/A assert(!tickEvent.scheduled()); 193360SN/A 194360SN/A // if any of this CPU's ExecContexts are active, mark the CPU as 1951450SN/A // running and schedule its tick event. 1963114Sgblack@eecs.umich.edu for (int i = 0; i < execContexts.size(); ++i) { 197360SN/A ExecContext *xc = execContexts[i]; 1986701Sgblack@eecs.umich.edu if (xc->status() == ExecContext::Active && _status != Running) { 1996701Sgblack@eecs.umich.edu _status = Running; 2006701Sgblack@eecs.umich.edu tickEvent.schedule(curTick); 2016701Sgblack@eecs.umich.edu } 2026701Sgblack@eecs.umich.edu } 203360SN/A} 204360SN/A 205360SN/A 206360SN/Avoid 2072680Sktlim@umich.eduSimpleCPU::activateContext(int thread_num, int delay) 208360SN/A{ 2091458SN/A assert(thread_num == 0); 210360SN/A assert(xc); 211360SN/A 2121450SN/A assert(_status == Idle); 2133114Sgblack@eecs.umich.edu notIdleFraction++; 214360SN/A scheduleTickEvent(delay); 2156701Sgblack@eecs.umich.edu _status = Running; 2166701Sgblack@eecs.umich.edu} 2176701Sgblack@eecs.umich.edu 2186701Sgblack@eecs.umich.edu 2196701Sgblack@eecs.umich.eduvoid 220360SN/ASimpleCPU::suspendContext(int thread_num) 2212680Sktlim@umich.edu{ 222360SN/A assert(thread_num == 0); 223360SN/A assert(xc); 224360SN/A 225360SN/A assert(_status == Running); 226360SN/A notIdleFraction--; 2271458SN/A unscheduleTickEvent(); 228360SN/A _status = Idle; 229360SN/A} 230360SN/A 2311450SN/A 2323114Sgblack@eecs.umich.eduvoid 233360SN/ASimpleCPU::deallocateContext(int thread_num) 2346701Sgblack@eecs.umich.edu{ 2356701Sgblack@eecs.umich.edu // for now, these are equivalent 2366701Sgblack@eecs.umich.edu suspendContext(thread_num); 2376701Sgblack@eecs.umich.edu} 238360SN/A 239360SN/A 240360SN/Avoid 2411458SN/ASimpleCPU::haltContext(int thread_num) 242360SN/A{ 243360SN/A // for now, these are equivalent 244360SN/A suspendContext(thread_num); 2451450SN/A} 2464118Sgblack@eecs.umich.edu 2474118Sgblack@eecs.umich.edu 2486701Sgblack@eecs.umich.eduvoid 2496701Sgblack@eecs.umich.eduSimpleCPU::regStats() 2506701Sgblack@eecs.umich.edu{ 2516701Sgblack@eecs.umich.edu using namespace Stats; 2526701Sgblack@eecs.umich.edu 2536701Sgblack@eecs.umich.edu BaseCPU::regStats(); 2544118Sgblack@eecs.umich.edu 2554118Sgblack@eecs.umich.edu numInsts 2564118Sgblack@eecs.umich.edu .name(name() + ".num_insts") 2574118Sgblack@eecs.umich.edu .desc("Number of instructions executed") 2584118Sgblack@eecs.umich.edu ; 2594118Sgblack@eecs.umich.edu 2604118Sgblack@eecs.umich.edu numMemRefs 2614118Sgblack@eecs.umich.edu .name(name() + ".num_refs") 2624118Sgblack@eecs.umich.edu .desc("Number of memory references") 2634118Sgblack@eecs.umich.edu ; 2646111Ssteve.reinhardt@amd.com 2656111Ssteve.reinhardt@amd.com notIdleFraction 2666111Ssteve.reinhardt@amd.com .name(name() + ".not_idle_fraction") 2676111Ssteve.reinhardt@amd.com .desc("Percentage of non-idle cycles") 2684118Sgblack@eecs.umich.edu ; 2694118Sgblack@eecs.umich.edu 2704118Sgblack@eecs.umich.edu idleFraction 2714118Sgblack@eecs.umich.edu .name(name() + ".idle_fraction") 2724118Sgblack@eecs.umich.edu .desc("Percentage of idle cycles") 2734118Sgblack@eecs.umich.edu ; 2744118Sgblack@eecs.umich.edu 2754118Sgblack@eecs.umich.edu icacheStallCycles 2764118Sgblack@eecs.umich.edu .name(name() + ".icache_stall_cycles") 2774118Sgblack@eecs.umich.edu .desc("ICache total stall cycles") 2784118Sgblack@eecs.umich.edu .prereq(icacheStallCycles) 2794118Sgblack@eecs.umich.edu ; 2803114Sgblack@eecs.umich.edu 281360SN/A dcacheStallCycles 282360SN/A .name(name() + ".dcache_stall_cycles") 2831458SN/A .desc("DCache total stall cycles") 284360SN/A .prereq(dcacheStallCycles) 285360SN/A ; 286360SN/A 287360SN/A idleFraction = constant(1.0) - notIdleFraction; 288360SN/A} 2891450SN/A 2903114Sgblack@eecs.umich.eduvoid 291360SN/ASimpleCPU::resetStats() 2926701Sgblack@eecs.umich.edu{ 2936701Sgblack@eecs.umich.edu startNumInst = numInst; 2946701Sgblack@eecs.umich.edu notIdleFraction = (_status != Idle); 2956701Sgblack@eecs.umich.edu} 296360SN/A 297360SN/Avoid 298360SN/ASimpleCPU::serialize(ostream &os) 2992680Sktlim@umich.edu{ 300360SN/A BaseCPU::serialize(os); 3011458SN/A SERIALIZE_ENUM(_status); 302360SN/A SERIALIZE_SCALAR(inst); 303360SN/A nameOut(os, csprintf("%s.xc", name())); 3041450SN/A xc->serialize(os); 3055513SMichael.Adler@intel.com nameOut(os, csprintf("%s.tickEvent", name())); 3065513SMichael.Adler@intel.com tickEvent.serialize(os); 3075513SMichael.Adler@intel.com nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 3086701Sgblack@eecs.umich.edu cacheCompletionEvent.serialize(os); 3096701Sgblack@eecs.umich.edu} 3106701Sgblack@eecs.umich.edu 3116701Sgblack@eecs.umich.eduvoid 3125513SMichael.Adler@intel.comSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 3135513SMichael.Adler@intel.com{ 3145513SMichael.Adler@intel.com BaseCPU::unserialize(cp, section); 3155513SMichael.Adler@intel.com UNSERIALIZE_ENUM(_status); 3165513SMichael.Adler@intel.com UNSERIALIZE_SCALAR(inst); 3175513SMichael.Adler@intel.com xc->unserialize(cp, csprintf("%s.xc", section)); 3185513SMichael.Adler@intel.com tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 3195513SMichael.Adler@intel.com cacheCompletionEvent 3205513SMichael.Adler@intel.com .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); 3215513SMichael.Adler@intel.com} 3225513SMichael.Adler@intel.com 3235513SMichael.Adler@intel.comvoid 3245513SMichael.Adler@intel.comchange_thread_state(int thread_number, int activate, int priority) 3255513SMichael.Adler@intel.com{ 3265513SMichael.Adler@intel.com} 3275513SMichael.Adler@intel.com 3285513SMichael.Adler@intel.comFault 3295513SMichael.Adler@intel.comSimpleCPU::copySrcTranslate(Addr src) 3305513SMichael.Adler@intel.com{ 3315513SMichael.Adler@intel.com static bool no_warn = true; 3325513SMichael.Adler@intel.com int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3335513SMichael.Adler@intel.com // Only support block sizes of 64 atm. 3345513SMichael.Adler@intel.com assert(blk_size == 64); 3355513SMichael.Adler@intel.com int offset = src & (blk_size - 1); 3365513SMichael.Adler@intel.com 3375513SMichael.Adler@intel.com // Make sure block doesn't span page 3385513SMichael.Adler@intel.com if (no_warn && 3395513SMichael.Adler@intel.com (src & PageMask) != ((src + blk_size) & PageMask) && 3405513SMichael.Adler@intel.com (src >> 40) != 0xfffffc) { 3415513SMichael.Adler@intel.com warn("Copied block source spans pages %x.", src); 3425513SMichael.Adler@intel.com no_warn = false; 3436701Sgblack@eecs.umich.edu } 3446701Sgblack@eecs.umich.edu 3455513SMichael.Adler@intel.com memReq->reset(src & ~(blk_size - 1), blk_size); 3465513SMichael.Adler@intel.com 3475513SMichael.Adler@intel.com // translate to physical address 3485513SMichael.Adler@intel.com Fault fault = xc->translateDataReadReq(memReq); 3495513SMichael.Adler@intel.com 3506701Sgblack@eecs.umich.edu if (fault == NoFault) { 3516701Sgblack@eecs.umich.edu xc->copySrcAddr = src; 3526701Sgblack@eecs.umich.edu xc->copySrcPhysAddr = memReq->paddr + offset; 3536701Sgblack@eecs.umich.edu } else { 3545513SMichael.Adler@intel.com assert(!fault->isAlignmentFault()); 3555513SMichael.Adler@intel.com 3565513SMichael.Adler@intel.com xc->copySrcAddr = 0; 3575513SMichael.Adler@intel.com xc->copySrcPhysAddr = 0; 3585513SMichael.Adler@intel.com } 3595513SMichael.Adler@intel.com return fault; 3605513SMichael.Adler@intel.com} 3615513SMichael.Adler@intel.com 3625513SMichael.Adler@intel.comFault 3633114Sgblack@eecs.umich.eduSimpleCPU::copy(Addr dest) 364511SN/A{ 3651706SN/A static bool no_warn = true; 366360SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3676701Sgblack@eecs.umich.edu // Only support block sizes of 64 atm. 3686701Sgblack@eecs.umich.edu assert(blk_size == 64); 3691450SN/A uint8_t data[blk_size]; 370511SN/A //assert(xc->copySrcAddr); 3713669Sbinkertn@umich.edu int offset = dest & (blk_size - 1); 3723669Sbinkertn@umich.edu 3733669Sbinkertn@umich.edu // Make sure block doesn't span page 374511SN/A if (no_warn && 3751458SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 376511SN/A (dest >> 40) != 0xfffffc) { 377511SN/A no_warn = false; 3785513SMichael.Adler@intel.com warn("Copied block destination spans pages %x. ", dest); 3795513SMichael.Adler@intel.com } 3805513SMichael.Adler@intel.com 3815513SMichael.Adler@intel.com memReq->reset(dest & ~(blk_size -1), blk_size); 3825513SMichael.Adler@intel.com // translate to physical address 3835513SMichael.Adler@intel.com Fault fault = xc->translateDataWriteReq(memReq); 3846701Sgblack@eecs.umich.edu 3856701Sgblack@eecs.umich.edu if (fault == NoFault) { 3865513SMichael.Adler@intel.com Addr dest_addr = memReq->paddr + offset; 3875513SMichael.Adler@intel.com // Need to read straight from memory since we have more than 8 bytes. 3885513SMichael.Adler@intel.com memReq->paddr = xc->copySrcPhysAddr; 3895513SMichael.Adler@intel.com xc->mem->read(memReq, data); 3905513SMichael.Adler@intel.com memReq->paddr = dest_addr; 3916701Sgblack@eecs.umich.edu xc->mem->write(memReq, data); 3925513SMichael.Adler@intel.com if (dcacheInterface) { 3935513SMichael.Adler@intel.com memReq->cmd = Copy; 3945513SMichael.Adler@intel.com memReq->completionEvent = NULL; 3955513SMichael.Adler@intel.com memReq->paddr = xc->copySrcPhysAddr; 3965513SMichael.Adler@intel.com memReq->dest = dest_addr; 3971450SN/A memReq->size = 64; 3983114Sgblack@eecs.umich.edu memReq->time = curTick; 399511SN/A memReq->flags &= ~INST_READ; 4001706SN/A dcacheInterface->access(memReq); 401511SN/A } 4026701Sgblack@eecs.umich.edu } 4036701Sgblack@eecs.umich.edu else 4041458SN/A assert(!fault->isAlignmentFault()); 405511SN/A 4061706SN/A return fault; 407511SN/A} 4086701Sgblack@eecs.umich.edu 4091458SN/A// precise architected memory state accessor macros 410511SN/Atemplate <class T> 4113669Sbinkertn@umich.eduFault 4123669Sbinkertn@umich.eduSimpleCPU::read(Addr addr, T &data, unsigned flags) 4133669Sbinkertn@umich.edu{ 4143669Sbinkertn@umich.edu if (status() == DcacheMissStall || status() == DcacheMissSwitch) { 4151706SN/A Fault fault = xc->read(memReq,data); 4161458SN/A 417511SN/A if (traceData) { 418511SN/A traceData->setAddr(addr); 4191706SN/A } 4203114Sgblack@eecs.umich.edu return fault; 4211706SN/A } 4221706SN/A 4231706SN/A memReq->reset(addr, sizeof(T), flags); 4246701Sgblack@eecs.umich.edu 4256701Sgblack@eecs.umich.edu // translate to physical address 4261706SN/A Fault fault = xc->translateDataReadReq(memReq); 4271706SN/A 4286701Sgblack@eecs.umich.edu // if we have a cache, do cache access too 4291706SN/A if (fault == NoFault && dcacheInterface) { 4303669Sbinkertn@umich.edu memReq->cmd = Read; 4313669Sbinkertn@umich.edu memReq->completionEvent = NULL; 4323669Sbinkertn@umich.edu memReq->time = curTick; 4331706SN/A memReq->flags &= ~INST_READ; 4341706SN/A MemAccessResult result = dcacheInterface->access(memReq); 4351706SN/A 4361706SN/A // Ugly hack to get an event scheduled *only* if the access is 4371706SN/A // a miss. We really should add first-class support for this 4386111Ssteve.reinhardt@amd.com // at some point. 4396111Ssteve.reinhardt@amd.com if (result != MA_HIT && dcacheInterface->doEvents()) { 4401706SN/A memReq->completionEvent = &cacheCompletionEvent; 4416701Sgblack@eecs.umich.edu lastDcacheStall = curTick; 4426701Sgblack@eecs.umich.edu unscheduleTickEvent(); 4431706SN/A _status = DcacheMissStall; 4441706SN/A } else { 4451706SN/A // do functional access 4461706SN/A fault = xc->read(memReq, data); 4476701Sgblack@eecs.umich.edu 4481706SN/A } 4491706SN/A } else if(fault == NoFault) { 4501706SN/A // do functional access 4511706SN/A fault = xc->read(memReq, data); 4521999SN/A 4531999SN/A } 4546685Stjones1@inf.ed.ac.uk 4556685Stjones1@inf.ed.ac.uk if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 4566685Stjones1@inf.ed.ac.uk recordEvent("Uncached Read"); 4576701Sgblack@eecs.umich.edu 4586701Sgblack@eecs.umich.edu return fault; 4596685Stjones1@inf.ed.ac.uk} 4606685Stjones1@inf.ed.ac.uk 4616685Stjones1@inf.ed.ac.uk#ifndef DOXYGEN_SHOULD_SKIP_THIS 4626685Stjones1@inf.ed.ac.uk 4636701Sgblack@eecs.umich.edutemplate 4646685Stjones1@inf.ed.ac.ukFault 4656685Stjones1@inf.ed.ac.ukSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4666685Stjones1@inf.ed.ac.uk 4676685Stjones1@inf.ed.ac.uktemplate 4686685Stjones1@inf.ed.ac.ukFault 4696685Stjones1@inf.ed.ac.ukSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4705513SMichael.Adler@intel.com 4715513SMichael.Adler@intel.comtemplate 4725513SMichael.Adler@intel.comFault 4735513SMichael.Adler@intel.comSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4745513SMichael.Adler@intel.com 4755513SMichael.Adler@intel.comtemplate 4765513SMichael.Adler@intel.comFault 4775521Snate@binkert.orgSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4785513SMichael.Adler@intel.com 4795513SMichael.Adler@intel.com#endif //DOXYGEN_SHOULD_SKIP_THIS 4805513SMichael.Adler@intel.com 4813114Sgblack@eecs.umich.edutemplate<> 4821999SN/AFault 4831999SN/ASimpleCPU::read(Addr addr, double &data, unsigned flags) 4841999SN/A{ 4856701Sgblack@eecs.umich.edu return read(addr, *(uint64_t*)&data, flags); 4866701Sgblack@eecs.umich.edu} 4871999SN/A 4881999SN/Atemplate<> 4891999SN/AFault 4906701Sgblack@eecs.umich.eduSimpleCPU::read(Addr addr, float &data, unsigned flags) 4911999SN/A{ 4926701Sgblack@eecs.umich.edu return read(addr, *(uint32_t*)&data, flags); 4931999SN/A} 4941999SN/A 4953669Sbinkertn@umich.edu 4963669Sbinkertn@umich.edutemplate<> 4973669Sbinkertn@umich.eduFault 4981999SN/ASimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4991999SN/A{ 5001999SN/A return read(addr, (uint32_t&)data, flags); 5011999SN/A} 5021999SN/A 5033114Sgblack@eecs.umich.edu 5041999SN/Atemplate <class T> 5056701Sgblack@eecs.umich.eduFault 5066701Sgblack@eecs.umich.eduSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 5071999SN/A{ 5081999SN/A memReq->reset(addr, sizeof(T), flags); 5091999SN/A 5101999SN/A // translate to physical address 5111999SN/A Fault fault = xc->translateDataWriteReq(memReq); 5126701Sgblack@eecs.umich.edu 5131999SN/A // do functional access 5146701Sgblack@eecs.umich.edu if (fault == NoFault) 5151999SN/A fault = xc->write(memReq, data); 5161999SN/A 5171999SN/A if (fault == NoFault && dcacheInterface) { 5181999SN/A memReq->cmd = Write; 5191999SN/A memcpy(memReq->data,(uint8_t *)&data,memReq->size); 5202093SN/A memReq->completionEvent = NULL; 5212093SN/A memReq->time = curTick; 5222093SN/A memReq->flags &= ~INST_READ; 5233114Sgblack@eecs.umich.edu MemAccessResult result = dcacheInterface->access(memReq); 5243079Sstever@eecs.umich.edu 5256701Sgblack@eecs.umich.edu // Ugly hack to get an event scheduled *only* if the access is 5266701Sgblack@eecs.umich.edu // a miss. We really should add first-class support for this 5273079Sstever@eecs.umich.edu // at some point. 5283079Sstever@eecs.umich.edu if (result != MA_HIT && dcacheInterface->doEvents()) { 5293079Sstever@eecs.umich.edu memReq->completionEvent = &cacheCompletionEvent; 5306701Sgblack@eecs.umich.edu lastDcacheStall = curTick; 5315282Srstrong@cs.ucsd.edu unscheduleTickEvent(); 5323079Sstever@eecs.umich.edu _status = DcacheMissStall; 5336111Ssteve.reinhardt@amd.com } 5346111Ssteve.reinhardt@amd.com } 5353079Sstever@eecs.umich.edu 5363079Sstever@eecs.umich.edu if (res && (fault == NoFault)) 5373079Sstever@eecs.umich.edu *res = memReq->result; 5383079Sstever@eecs.umich.edu 5393114Sgblack@eecs.umich.edu if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 5402680Sktlim@umich.edu recordEvent("Uncached Write"); 5412093SN/A 5426701Sgblack@eecs.umich.edu return fault; 5436701Sgblack@eecs.umich.edu} 5442093SN/A 5452093SN/A 5462093SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 5472093SN/Atemplate 5486701Sgblack@eecs.umich.eduFault 5492093SN/ASimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 5502093SN/A 5512093SN/Atemplate 5522093SN/AFault 5532093SN/ASimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 5542093SN/A 5552093SN/Atemplate 5562093SN/AFault 5572093SN/ASimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 5582093SN/A 5592093SN/Atemplate 5602093SN/AFault 5612093SN/ASimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 5622093SN/A 5632093SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 5642093SN/A 5652093SN/Atemplate<> 5662093SN/AFault 5672093SN/ASimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5682093SN/A{ 5692093SN/A return write(*(uint64_t*)&data, addr, flags, res); 5702093SN/A} 5712093SN/A 5722093SN/Atemplate<> 5732093SN/AFault 5742093SN/ASimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5752093SN/A{ 5762093SN/A return write(*(uint32_t*)&data, addr, flags, res); 5772093SN/A} 5782093SN/A 5792093SN/A 5802093SN/Atemplate<> 5812238SN/AFault 5823114Sgblack@eecs.umich.eduSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5832687Sksewell@umich.edu{ 5842687Sksewell@umich.edu return write((uint32_t)data, addr, flags, res); 5856701Sgblack@eecs.umich.edu} 5866701Sgblack@eecs.umich.edu 5872687Sksewell@umich.edu 5882687Sksewell@umich.edu#if FULL_SYSTEM 5892687Sksewell@umich.eduAddr 5902687Sksewell@umich.eduSimpleCPU::dbg_vtophys(Addr addr) 5916701Sgblack@eecs.umich.edu{ 5922687Sksewell@umich.edu return vtophys(xc, addr); 5932687Sksewell@umich.edu} 5942687Sksewell@umich.edu#endif // FULL_SYSTEM 5952687Sksewell@umich.edu 5962687Sksewell@umich.eduvoid 5972687Sksewell@umich.eduSimpleCPU::processCacheCompletion() 5982687Sksewell@umich.edu{ 5992687Sksewell@umich.edu switch (status()) { 6002687Sksewell@umich.edu case IcacheMissStall: 6012687Sksewell@umich.edu icacheStallCycles += curTick - lastIcacheStall; 6022687Sksewell@umich.edu _status = IcacheMissComplete; 6032687Sksewell@umich.edu scheduleTickEvent(1); 6042687Sksewell@umich.edu break; 6052687Sksewell@umich.edu case DcacheMissStall: 6062687Sksewell@umich.edu if (memReq->cmd.isRead()) { 6072687Sksewell@umich.edu curStaticInst->execute(this,traceData); 6082687Sksewell@umich.edu if (traceData) 6092687Sksewell@umich.edu traceData->finalize(); 6102687Sksewell@umich.edu } 6112687Sksewell@umich.edu dcacheStallCycles += curTick - lastDcacheStall; 6123114Sgblack@eecs.umich.edu _status = Running; 6132680Sktlim@umich.edu scheduleTickEvent(1); 6142238SN/A break; 6152238SN/A case DcacheMissSwitch: 6162238SN/A if (memReq->cmd.isRead()) { 6172093SN/A curStaticInst->execute(this,traceData); 6182238SN/A if (traceData) 6192238SN/A traceData->finalize(); 6202238SN/A } 6212238SN/A _status = SwitchedOut; 6222238SN/A sampler->signalSwitched(); 6235282Srstrong@cs.ucsd.edu case SwitchedOut: 6245282Srstrong@cs.ucsd.edu // If this CPU has been switched out due to sampling/warm-up, 6252238SN/A // ignore any further status changes (e.g., due to cache 6265282Srstrong@cs.ucsd.edu // misses outstanding at the time of the switch). 6272238SN/A return; 6282238SN/A default: 6292680Sktlim@umich.edu panic("SimpleCPU::processCacheCompletion: bad state"); 6302238SN/A break; 6312238SN/A } 6322238SN/A} 6332238SN/A 6342238SN/A#if FULL_SYSTEM 6353114Sgblack@eecs.umich.eduvoid 6362680Sktlim@umich.eduSimpleCPU::post_interrupt(int int_num, int index) 6372238SN/A{ 6382238SN/A BaseCPU::post_interrupt(int_num, index); 6392238SN/A 6402238SN/A if (xc->status() == ExecContext::Suspended) { 6412238SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 6423114Sgblack@eecs.umich.edu xc->activate(); 6433114Sgblack@eecs.umich.edu } 6442238SN/A} 6452238SN/A#endif // FULL_SYSTEM 6462238SN/A 6472238SN/A/* start simulation, program loaded, processor precise state initialized */ 6483114Sgblack@eecs.umich.eduvoid 6492680Sktlim@umich.eduSimpleCPU::tick() 6502238SN/A{ 6512238SN/A numCycles++; 6522238SN/A 6532238SN/A traceData = NULL; 6542238SN/A 6553114Sgblack@eecs.umich.edu Fault fault = NoFault; 6565543Ssaidi@eecs.umich.edu 6572238SN/A#if FULL_SYSTEM 6582238SN/A if (checkInterrupts && check_interrupts() && !xc->inPalMode() && 6592238SN/A status() != IcacheMissComplete) { 6602238SN/A int ipl = 0; 6613114Sgblack@eecs.umich.edu int summary = 0; 6622680Sktlim@umich.edu checkInterrupts = false; 6632238SN/A 6642238SN/A if (xc->readMiscReg(IPR_SIRR)) { 6653114Sgblack@eecs.umich.edu for (int i = INTLEVEL_SOFTWARE_MIN; 6663114Sgblack@eecs.umich.edu i < INTLEVEL_SOFTWARE_MAX; i++) { 6672238SN/A if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 6682238SN/A // See table 4-19 of 21164 hardware reference 6692238SN/A ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 6702238SN/A summary |= (ULL(1) << i); 6713114Sgblack@eecs.umich.edu } 6722680Sktlim@umich.edu } 6732238SN/A } 6742238SN/A 6756701Sgblack@eecs.umich.edu uint64_t interrupts = xc->cpu->intr_status(); 6766701Sgblack@eecs.umich.edu for (int i = INTLEVEL_EXTERNAL_MIN; 6772238SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 6782238SN/A if (interrupts & (ULL(1) << i)) { 6792238SN/A // See table 4-19 of 21164 hardware reference 6802238SN/A ipl = i; 6813114Sgblack@eecs.umich.edu summary |= (ULL(1) << i); 6822680Sktlim@umich.edu } 6832238SN/A } 6842238SN/A 6852238SN/A if (xc->readMiscReg(IPR_ASTRR)) 6862238SN/A panic("asynchronous traps not implemented\n"); 6872238SN/A 6883114Sgblack@eecs.umich.edu if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) { 6893114Sgblack@eecs.umich.edu xc->setMiscReg(IPR_ISR, summary); 6902238SN/A xc->setMiscReg(IPR_INTID, ipl); 6912238SN/A Fault(new InterruptFault)->invoke(xc); 6922238SN/A 6933114Sgblack@eecs.umich.edu DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 6942680Sktlim@umich.edu xc->readMiscReg(IPR_IPLR), ipl, summary); 6952238SN/A } 6963114Sgblack@eecs.umich.edu } 6972238SN/A#endif 6982238SN/A 6992238SN/A // maintain $r0 semantics 7003114Sgblack@eecs.umich.edu xc->regs.intRegFile[ZeroReg] = 0; 7012680Sktlim@umich.edu#ifdef TARGET_ALPHA 7022238SN/A xc->regs.floatRegFile.d[ZeroReg] = 0.0; 7035543Ssaidi@eecs.umich.edu#endif // TARGET_ALPHA 7042238SN/A 7052238SN/A if (status() == IcacheMissComplete) { 7062238SN/A // We've already fetched an instruction and were stalled on an 7073114Sgblack@eecs.umich.edu // I-cache miss. No need to fetch it again. 7082680Sktlim@umich.edu 7092238SN/A // Set status to running; tick event will get rescheduled if 7105543Ssaidi@eecs.umich.edu // necessary at end of tick() function. 7112238SN/A _status = Running; 7122238SN/A } 7132238SN/A else { 7143114Sgblack@eecs.umich.edu // Try to fetch an instruction 7152680Sktlim@umich.edu 7162238SN/A // set up memory request for instruction fetch 7173114Sgblack@eecs.umich.edu#if FULL_SYSTEM 7182238SN/A#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 7192238SN/A#else 7202238SN/A#define IFETCH_FLAGS(pc) 0 7213114Sgblack@eecs.umich.edu#endif 7222680Sktlim@umich.edu 7232238SN/A memReq->cmd = Read; 7243114Sgblack@eecs.umich.edu memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 7252238SN/A IFETCH_FLAGS(xc->regs.pc)); 7262238SN/A 7272238SN/A fault = xc->translateInstReq(memReq); 7286109Ssanchezd@stanford.edu 7296109Ssanchezd@stanford.edu if (fault == NoFault) 7306109Ssanchezd@stanford.edu fault = xc->mem->read(memReq, inst); 7316109Ssanchezd@stanford.edu 7326701Sgblack@eecs.umich.edu if (icacheInterface && fault == NoFault) { 7336701Sgblack@eecs.umich.edu memReq->completionEvent = NULL; 7346701Sgblack@eecs.umich.edu 7356701Sgblack@eecs.umich.edu memReq->time = curTick; 7366109Ssanchezd@stanford.edu memReq->flags |= INST_READ; 7376701Sgblack@eecs.umich.edu MemAccessResult result = icacheInterface->access(memReq); 7386701Sgblack@eecs.umich.edu 7396109Ssanchezd@stanford.edu // Ugly hack to get an event scheduled *only* if the access is 7406109Ssanchezd@stanford.edu // a miss. We really should add first-class support for this 7416701Sgblack@eecs.umich.edu // at some point. 7426111Ssteve.reinhardt@amd.com if (result != MA_HIT && icacheInterface->doEvents()) { 7436111Ssteve.reinhardt@amd.com memReq->completionEvent = &cacheCompletionEvent; 7446111Ssteve.reinhardt@amd.com lastIcacheStall = curTick; 7456701Sgblack@eecs.umich.edu unscheduleTickEvent(); 7466109Ssanchezd@stanford.edu _status = IcacheMissStall; 7476109Ssanchezd@stanford.edu return; 7486111Ssteve.reinhardt@amd.com } 7496109Ssanchezd@stanford.edu } 7506109Ssanchezd@stanford.edu } 7516109Ssanchezd@stanford.edu 7526109Ssanchezd@stanford.edu // If we've got a valid instruction (i.e., no fault on instruction 7536109Ssanchezd@stanford.edu // fetch), then execute it. 7546111Ssteve.reinhardt@amd.com if (fault == NoFault) { 7556109Ssanchezd@stanford.edu 7566111Ssteve.reinhardt@amd.com // keep an instruction count 7576109Ssanchezd@stanford.edu numInst++; 7586109Ssanchezd@stanford.edu numInsts++; 7596109Ssanchezd@stanford.edu 7606109Ssanchezd@stanford.edu // check for instruction-count-based events 7616111Ssteve.reinhardt@amd.com comInstEventQueue[0]->serviceEvents(numInst); 7626109Ssanchezd@stanford.edu 7636109Ssanchezd@stanford.edu // decode the instruction 7646109Ssanchezd@stanford.edu inst = gtoh(inst); 7656109Ssanchezd@stanford.edu curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC())); 7666337Sgblack@eecs.umich.edu 7676109Ssanchezd@stanford.edu traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, 7686109Ssanchezd@stanford.edu xc->regs.pc); 7696109Ssanchezd@stanford.edu 7706109Ssanchezd@stanford.edu#if FULL_SYSTEM 7716109Ssanchezd@stanford.edu xc->setInst(inst); 7726109Ssanchezd@stanford.edu#endif // FULL_SYSTEM 7736109Ssanchezd@stanford.edu 7746109Ssanchezd@stanford.edu xc->func_exe_inst++; 7756109Ssanchezd@stanford.edu 7766109Ssanchezd@stanford.edu fault = curStaticInst->execute(this, traceData); 7776111Ssteve.reinhardt@amd.com 7786701Sgblack@eecs.umich.edu#if FULL_SYSTEM 7796109Ssanchezd@stanford.edu if (xc->fnbin) { 7806111Ssteve.reinhardt@amd.com assert(xc->kernelStats); 7816111Ssteve.reinhardt@amd.com system->kernelBinning->execute(xc, inst); 7826109Ssanchezd@stanford.edu } 7836111Ssteve.reinhardt@amd.com 7846109Ssanchezd@stanford.edu if (xc->profile) { 7856110Ssteve.reinhardt@amd.com bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 7866109Ssanchezd@stanford.edu xc->profilePC = usermode ? 1 : xc->regs.pc; 7876109Ssanchezd@stanford.edu ProfileNode *node = xc->profile->consume(xc, inst); 7886111Ssteve.reinhardt@amd.com if (node) 7896111Ssteve.reinhardt@amd.com xc->profileNode = node; 7906109Ssanchezd@stanford.edu } 7916109Ssanchezd@stanford.edu#endif 7926109Ssanchezd@stanford.edu 7936109Ssanchezd@stanford.edu if (curStaticInst->isMemRef()) { 7946109Ssanchezd@stanford.edu numMemRefs++; 7956109Ssanchezd@stanford.edu } 7966109Ssanchezd@stanford.edu 7976134Sgblack@eecs.umich.edu if (curStaticInst->isLoad()) { 7986109Ssanchezd@stanford.edu ++numLoad; 7996109Ssanchezd@stanford.edu comLoadEventQueue[0]->serviceEvents(numLoad); 8006109Ssanchezd@stanford.edu } 8016109Ssanchezd@stanford.edu 8026109Ssanchezd@stanford.edu // If we have a dcache miss, then we can't finialize the instruction 8036109Ssanchezd@stanford.edu // trace yet because we want to populate it with the data later 8046109Ssanchezd@stanford.edu if (traceData && 8056109Ssanchezd@stanford.edu !(status() == DcacheMissStall && memReq->cmd.isRead())) { 8066109Ssanchezd@stanford.edu traceData->finalize(); 8076109Ssanchezd@stanford.edu } 8086109Ssanchezd@stanford.edu 8096109Ssanchezd@stanford.edu traceFunctions(xc->regs.pc); 810 811 } // if (fault == NoFault) 812 813 if (fault != NoFault) { 814#if FULL_SYSTEM 815 fault->invoke(xc); 816#else // !FULL_SYSTEM 817 fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); 818#endif // FULL_SYSTEM 819 } 820 else { 821#if THE_ISA != MIPS_ISA 822 // go to the next instruction 823 xc->regs.pc = xc->regs.npc; 824 xc->regs.npc += sizeof(MachInst); 825#else 826 // go to the next instruction 827 xc->regs.pc = xc->regs.npc; 828 xc->regs.npc = xc->regs.nnpc; 829 xc->regs.nnpc += sizeof(MachInst); 830#endif 831 832 } 833 834#if FULL_SYSTEM 835 Addr oldpc; 836 do { 837 oldpc = xc->regs.pc; 838 system->pcEventQueue.service(xc); 839 } while (oldpc != xc->regs.pc); 840#endif 841 842 assert(status() == Running || 843 status() == Idle || 844 status() == DcacheMissStall); 845 846 if (status() == Running && !tickEvent.scheduled()) 847 tickEvent.schedule(curTick + cycles(1)); 848} 849 850//////////////////////////////////////////////////////////////////////// 851// 852// SimpleCPU Simulation Object 853// 854BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 855 856 Param<Counter> max_insts_any_thread; 857 Param<Counter> max_insts_all_threads; 858 Param<Counter> max_loads_any_thread; 859 Param<Counter> max_loads_all_threads; 860 861#if FULL_SYSTEM 862 SimObjectParam<AlphaITB *> itb; 863 SimObjectParam<AlphaDTB *> dtb; 864 SimObjectParam<FunctionalMemory *> mem; 865 SimObjectParam<System *> system; 866 Param<int> cpu_id; 867 Param<Tick> profile; 868#else 869 SimObjectParam<Process *> workload; 870#endif // FULL_SYSTEM 871 872 Param<int> clock; 873 SimObjectParam<BaseMem *> icache; 874 SimObjectParam<BaseMem *> dcache; 875 876 Param<bool> defer_registration; 877 Param<int> width; 878 Param<bool> function_trace; 879 Param<Tick> function_trace_start; 880 881END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 882 883BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 884 885 INIT_PARAM(max_insts_any_thread, 886 "terminate when any thread reaches this inst count"), 887 INIT_PARAM(max_insts_all_threads, 888 "terminate when all threads have reached this inst count"), 889 INIT_PARAM(max_loads_any_thread, 890 "terminate when any thread reaches this load count"), 891 INIT_PARAM(max_loads_all_threads, 892 "terminate when all threads have reached this load count"), 893 894#if FULL_SYSTEM 895 INIT_PARAM(itb, "Instruction TLB"), 896 INIT_PARAM(dtb, "Data TLB"), 897 INIT_PARAM(mem, "memory"), 898 INIT_PARAM(system, "system object"), 899 INIT_PARAM(cpu_id, "processor ID"), 900 INIT_PARAM(profile, ""), 901#else 902 INIT_PARAM(workload, "processes to run"), 903#endif // FULL_SYSTEM 904 905 INIT_PARAM(clock, "clock speed"), 906 INIT_PARAM(icache, "L1 instruction cache object"), 907 INIT_PARAM(dcache, "L1 data cache object"), 908 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 909 INIT_PARAM(width, "cpu width"), 910 INIT_PARAM(function_trace, "Enable function trace"), 911 INIT_PARAM(function_trace_start, "Cycle to start function trace") 912 913END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 914 915 916CREATE_SIM_OBJECT(SimpleCPU) 917{ 918 SimpleCPU::Params *params = new SimpleCPU::Params(); 919 params->name = getInstanceName(); 920 params->numberOfThreads = 1; 921 params->max_insts_any_thread = max_insts_any_thread; 922 params->max_insts_all_threads = max_insts_all_threads; 923 params->max_loads_any_thread = max_loads_any_thread; 924 params->max_loads_all_threads = max_loads_all_threads; 925 params->deferRegistration = defer_registration; 926 params->clock = clock; 927 params->functionTrace = function_trace; 928 params->functionTraceStart = function_trace_start; 929 params->icache_interface = (icache) ? icache->getInterface() : NULL; 930 params->dcache_interface = (dcache) ? dcache->getInterface() : NULL; 931 params->width = width; 932 933#if FULL_SYSTEM 934 params->itb = itb; 935 params->dtb = dtb; 936 params->mem = mem; 937 params->system = system; 938 params->cpu_id = cpu_id; 939 params->profile = profile; 940#else 941 params->process = workload; 942#endif 943 944 SimpleCPU *cpu = new SimpleCPU(params); 945 return cpu; 946} 947 948REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 949 950