base.cc revision 1717 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/stats/events.hh"
45#include "base/trace.hh"
46#include "cpu/base.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/sampler/sampler.hh"
50#include "cpu/simple/cpu.hh"
51#include "cpu/smt.hh"
52#include "cpu/static_inst.hh"
53#include "mem/base_mem.hh"
54#include "mem/mem_interface.hh"
55#include "sim/builder.hh"
56#include "sim/debug.hh"
57#include "sim/host.hh"
58#include "sim/sim_events.hh"
59#include "sim/sim_object.hh"
60#include "sim/stats.hh"
61
62#ifdef FULL_SYSTEM
63#include "base/remote_gdb.hh"
64#include "mem/functional/memory_control.hh"
65#include "mem/functional/physical.hh"
66#include "sim/system.hh"
67#include "targetarch/alpha_memory.hh"
68#include "targetarch/vtophys.hh"
69#else // !FULL_SYSTEM
70#include "eio/eio.hh"
71#include "mem/functional/functional.hh"
72#endif // FULL_SYSTEM
73
74using namespace std;
75
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = width;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue), cpu(_cpu)
100{
101}
102
103void SimpleCPU::CacheCompletionEvent::process()
104{
105    cpu->processCacheCompletion();
106}
107
108const char *
109SimpleCPU::CacheCompletionEvent::description()
110{
111    return "SimpleCPU cache completion event";
112}
113
114SimpleCPU::SimpleCPU(Params *p)
115    : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
116      cacheCompletionEvent(this)
117{
118    _status = Idle;
119#ifdef FULL_SYSTEM
120    xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
121
122    // initialize CPU, including PC
123    TheISA::initCPU(&xc->regs);
124#else
125    xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
126#endif // !FULL_SYSTEM
127
128    icacheInterface = p->icache_interface;
129    dcacheInterface = p->dcache_interface;
130
131    memReq = new MemReq();
132    memReq->xc = xc;
133    memReq->asid = 0;
134    memReq->data = new uint8_t[64];
135
136    numInst = 0;
137    startNumInst = 0;
138    numLoad = 0;
139    startNumLoad = 0;
140    lastIcacheStall = 0;
141    lastDcacheStall = 0;
142
143    execContexts.push_back(xc);
144}
145
146SimpleCPU::~SimpleCPU()
147{
148}
149
150void
151SimpleCPU::switchOut(SamplingCPU *s)
152{
153    sampler = s;
154    if (status() == DcacheMissStall) {
155        DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
156        _status = DcacheMissSwitch;
157    }
158    else {
159        _status = SwitchedOut;
160
161        if (tickEvent.scheduled())
162            tickEvent.squash();
163
164        sampler->signalSwitched();
165    }
166}
167
168
169void
170SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
171{
172    BaseCPU::takeOverFrom(oldCPU);
173
174    assert(!tickEvent.scheduled());
175
176    // if any of this CPU's ExecContexts are active, mark the CPU as
177    // running and schedule its tick event.
178    for (int i = 0; i < execContexts.size(); ++i) {
179        ExecContext *xc = execContexts[i];
180        if (xc->status() == ExecContext::Active && _status != Running) {
181            _status = Running;
182            tickEvent.schedule(curTick);
183        }
184    }
185}
186
187
188void
189SimpleCPU::activateContext(int thread_num, int delay)
190{
191    assert(thread_num == 0);
192    assert(xc);
193
194    assert(_status == Idle);
195    notIdleFraction++;
196    scheduleTickEvent(delay);
197    _status = Running;
198}
199
200
201void
202SimpleCPU::suspendContext(int thread_num)
203{
204    assert(thread_num == 0);
205    assert(xc);
206
207    assert(_status == Running);
208    notIdleFraction--;
209    unscheduleTickEvent();
210    _status = Idle;
211}
212
213
214void
215SimpleCPU::deallocateContext(int thread_num)
216{
217    // for now, these are equivalent
218    suspendContext(thread_num);
219}
220
221
222void
223SimpleCPU::haltContext(int thread_num)
224{
225    // for now, these are equivalent
226    suspendContext(thread_num);
227}
228
229
230void
231SimpleCPU::regStats()
232{
233    using namespace Stats;
234
235    BaseCPU::regStats();
236
237    numInsts
238        .name(name() + ".num_insts")
239        .desc("Number of instructions executed")
240        ;
241
242    numMemRefs
243        .name(name() + ".num_refs")
244        .desc("Number of memory references")
245        ;
246
247    notIdleFraction
248        .name(name() + ".not_idle_fraction")
249        .desc("Percentage of non-idle cycles")
250        ;
251
252    idleFraction
253        .name(name() + ".idle_fraction")
254        .desc("Percentage of idle cycles")
255        ;
256
257    icacheStallCycles
258        .name(name() + ".icache_stall_cycles")
259        .desc("ICache total stall cycles")
260        .prereq(icacheStallCycles)
261        ;
262
263    dcacheStallCycles
264        .name(name() + ".dcache_stall_cycles")
265        .desc("DCache total stall cycles")
266        .prereq(dcacheStallCycles)
267        ;
268
269    idleFraction = constant(1.0) - notIdleFraction;
270}
271
272void
273SimpleCPU::resetStats()
274{
275    startNumInst = numInst;
276    notIdleFraction = (_status != Idle);
277}
278
279void
280SimpleCPU::serialize(ostream &os)
281{
282    BaseCPU::serialize(os);
283    SERIALIZE_ENUM(_status);
284    SERIALIZE_SCALAR(inst);
285    nameOut(os, csprintf("%s.xc", name()));
286    xc->serialize(os);
287    nameOut(os, csprintf("%s.tickEvent", name()));
288    tickEvent.serialize(os);
289    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
290    cacheCompletionEvent.serialize(os);
291}
292
293void
294SimpleCPU::unserialize(Checkpoint *cp, const string &section)
295{
296    BaseCPU::unserialize(cp, section);
297    UNSERIALIZE_ENUM(_status);
298    UNSERIALIZE_SCALAR(inst);
299    xc->unserialize(cp, csprintf("%s.xc", section));
300    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
301    cacheCompletionEvent
302        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
303}
304
305void
306change_thread_state(int thread_number, int activate, int priority)
307{
308}
309
310Fault
311SimpleCPU::copySrcTranslate(Addr src)
312{
313    static bool no_warn = true;
314    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
315    // Only support block sizes of 64 atm.
316    assert(blk_size == 64);
317    int offset = src & (blk_size - 1);
318
319    // Make sure block doesn't span page
320    if (no_warn &&
321        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
322        (src >> 40) != 0xfffffc) {
323        warn("Copied block source spans pages %x.", src);
324        no_warn = false;
325    }
326
327    memReq->reset(src & ~(blk_size - 1), blk_size);
328
329    // translate to physical address
330    Fault fault = xc->translateDataReadReq(memReq);
331
332    assert(fault != Alignment_Fault);
333
334    if (fault == No_Fault) {
335        xc->copySrcAddr = src;
336        xc->copySrcPhysAddr = memReq->paddr + offset;
337    } else {
338        xc->copySrcAddr = 0;
339        xc->copySrcPhysAddr = 0;
340    }
341    return fault;
342}
343
344Fault
345SimpleCPU::copy(Addr dest)
346{
347    static bool no_warn = true;
348    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
349    // Only support block sizes of 64 atm.
350    assert(blk_size == 64);
351    uint8_t data[blk_size];
352    //assert(xc->copySrcAddr);
353    int offset = dest & (blk_size - 1);
354
355    // Make sure block doesn't span page
356    if (no_warn &&
357        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
358        (dest >> 40) != 0xfffffc) {
359        no_warn = false;
360        warn("Copied block destination spans pages %x. ", dest);
361    }
362
363    memReq->reset(dest & ~(blk_size -1), blk_size);
364    // translate to physical address
365    Fault fault = xc->translateDataWriteReq(memReq);
366
367    assert(fault != Alignment_Fault);
368
369    if (fault == No_Fault) {
370        Addr dest_addr = memReq->paddr + offset;
371        // Need to read straight from memory since we have more than 8 bytes.
372        memReq->paddr = xc->copySrcPhysAddr;
373        xc->mem->read(memReq, data);
374        memReq->paddr = dest_addr;
375        xc->mem->write(memReq, data);
376        if (dcacheInterface) {
377            memReq->cmd = Copy;
378            memReq->completionEvent = NULL;
379            memReq->paddr = xc->copySrcPhysAddr;
380            memReq->dest = dest_addr;
381            memReq->size = 64;
382            memReq->time = curTick;
383            dcacheInterface->access(memReq);
384        }
385    }
386    return fault;
387}
388
389// precise architected memory state accessor macros
390template <class T>
391Fault
392SimpleCPU::read(Addr addr, T &data, unsigned flags)
393{
394    if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
395        Fault fault = xc->read(memReq,data);
396
397        if (traceData) {
398            traceData->setAddr(addr);
399        }
400        return fault;
401    }
402
403    memReq->reset(addr, sizeof(T), flags);
404
405    // translate to physical address
406    Fault fault = xc->translateDataReadReq(memReq);
407
408    // if we have a cache, do cache access too
409    if (fault == No_Fault && dcacheInterface) {
410        memReq->cmd = Read;
411        memReq->completionEvent = NULL;
412        memReq->time = curTick;
413        MemAccessResult result = dcacheInterface->access(memReq);
414
415        // Ugly hack to get an event scheduled *only* if the access is
416        // a miss.  We really should add first-class support for this
417        // at some point.
418        if (result != MA_HIT && dcacheInterface->doEvents()) {
419            memReq->completionEvent = &cacheCompletionEvent;
420            lastDcacheStall = curTick;
421            unscheduleTickEvent();
422            _status = DcacheMissStall;
423        } else {
424            // do functional access
425            fault = xc->read(memReq, data);
426
427        }
428    } else if(fault == No_Fault) {
429        // do functional access
430        fault = xc->read(memReq, data);
431
432    }
433
434    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
435        recordEvent("Uncached Read");
436
437    return fault;
438}
439
440#ifndef DOXYGEN_SHOULD_SKIP_THIS
441
442template
443Fault
444SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
445
446template
447Fault
448SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
449
450template
451Fault
452SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
453
454template
455Fault
456SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
457
458#endif //DOXYGEN_SHOULD_SKIP_THIS
459
460template<>
461Fault
462SimpleCPU::read(Addr addr, double &data, unsigned flags)
463{
464    return read(addr, *(uint64_t*)&data, flags);
465}
466
467template<>
468Fault
469SimpleCPU::read(Addr addr, float &data, unsigned flags)
470{
471    return read(addr, *(uint32_t*)&data, flags);
472}
473
474
475template<>
476Fault
477SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
478{
479    return read(addr, (uint32_t&)data, flags);
480}
481
482
483template <class T>
484Fault
485SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
486{
487    memReq->reset(addr, sizeof(T), flags);
488
489    // translate to physical address
490    Fault fault = xc->translateDataWriteReq(memReq);
491
492    // do functional access
493    if (fault == No_Fault)
494        fault = xc->write(memReq, data);
495
496    if (fault == No_Fault && dcacheInterface) {
497        memReq->cmd = Write;
498        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
499        memReq->completionEvent = NULL;
500        memReq->time = curTick;
501        MemAccessResult result = dcacheInterface->access(memReq);
502
503        // Ugly hack to get an event scheduled *only* if the access is
504        // a miss.  We really should add first-class support for this
505        // at some point.
506        if (result != MA_HIT && dcacheInterface->doEvents()) {
507            memReq->completionEvent = &cacheCompletionEvent;
508            lastDcacheStall = curTick;
509            unscheduleTickEvent();
510            _status = DcacheMissStall;
511        }
512    }
513
514    if (res && (fault == No_Fault))
515        *res = memReq->result;
516
517    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
518        recordEvent("Uncached Write");
519
520    return fault;
521}
522
523
524#ifndef DOXYGEN_SHOULD_SKIP_THIS
525template
526Fault
527SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
528
529template
530Fault
531SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
532
533template
534Fault
535SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
536
537template
538Fault
539SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
540
541#endif //DOXYGEN_SHOULD_SKIP_THIS
542
543template<>
544Fault
545SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
546{
547    return write(*(uint64_t*)&data, addr, flags, res);
548}
549
550template<>
551Fault
552SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
553{
554    return write(*(uint32_t*)&data, addr, flags, res);
555}
556
557
558template<>
559Fault
560SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
561{
562    return write((uint32_t)data, addr, flags, res);
563}
564
565
566#ifdef FULL_SYSTEM
567Addr
568SimpleCPU::dbg_vtophys(Addr addr)
569{
570    return vtophys(xc, addr);
571}
572#endif // FULL_SYSTEM
573
574void
575SimpleCPU::processCacheCompletion()
576{
577    switch (status()) {
578      case IcacheMissStall:
579        icacheStallCycles += curTick - lastIcacheStall;
580        _status = IcacheMissComplete;
581        scheduleTickEvent(1);
582        break;
583      case DcacheMissStall:
584        if (memReq->cmd.isRead()) {
585            curStaticInst->execute(this,traceData);
586            if (traceData)
587                traceData->finalize();
588        }
589        dcacheStallCycles += curTick - lastDcacheStall;
590        _status = Running;
591        scheduleTickEvent(1);
592        break;
593      case DcacheMissSwitch:
594        if (memReq->cmd.isRead()) {
595            curStaticInst->execute(this,traceData);
596            if (traceData)
597                traceData->finalize();
598        }
599        _status = SwitchedOut;
600        sampler->signalSwitched();
601      case SwitchedOut:
602        // If this CPU has been switched out due to sampling/warm-up,
603        // ignore any further status changes (e.g., due to cache
604        // misses outstanding at the time of the switch).
605        return;
606      default:
607        panic("SimpleCPU::processCacheCompletion: bad state");
608        break;
609    }
610}
611
612#ifdef FULL_SYSTEM
613void
614SimpleCPU::post_interrupt(int int_num, int index)
615{
616    BaseCPU::post_interrupt(int_num, index);
617
618    if (xc->status() == ExecContext::Suspended) {
619                DPRINTF(IPI,"Suspended Processor awoke\n");
620        xc->activate();
621    }
622}
623#endif // FULL_SYSTEM
624
625/* start simulation, program loaded, processor precise state initialized */
626void
627SimpleCPU::tick()
628{
629    numCycles++;
630
631    traceData = NULL;
632
633    Fault fault = No_Fault;
634
635#ifdef FULL_SYSTEM
636    if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
637        status() != IcacheMissComplete) {
638        int ipl = 0;
639        int summary = 0;
640        checkInterrupts = false;
641        IntReg *ipr = xc->regs.ipr;
642
643        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
644            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
645                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
646                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
647                    // See table 4-19 of 21164 hardware reference
648                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
649                    summary |= (ULL(1) << i);
650                }
651            }
652        }
653
654        uint64_t interrupts = xc->cpu->intr_status();
655        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
656            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
657            if (interrupts & (ULL(1) << i)) {
658                // See table 4-19 of 21164 hardware reference
659                ipl = i;
660                summary |= (ULL(1) << i);
661            }
662        }
663
664        if (ipr[TheISA::IPR_ASTRR])
665            panic("asynchronous traps not implemented\n");
666
667        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
668            ipr[TheISA::IPR_ISR] = summary;
669            ipr[TheISA::IPR_INTID] = ipl;
670            xc->ev5_trap(Interrupt_Fault);
671
672            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
673                    ipr[TheISA::IPR_IPLR], ipl, summary);
674        }
675    }
676#endif
677
678    // maintain $r0 semantics
679    xc->regs.intRegFile[ZeroReg] = 0;
680#ifdef TARGET_ALPHA
681    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
682#endif // TARGET_ALPHA
683
684    if (status() == IcacheMissComplete) {
685        // We've already fetched an instruction and were stalled on an
686        // I-cache miss.  No need to fetch it again.
687
688        // Set status to running; tick event will get rescheduled if
689        // necessary at end of tick() function.
690        _status = Running;
691    }
692    else {
693        // Try to fetch an instruction
694
695        // set up memory request for instruction fetch
696#ifdef FULL_SYSTEM
697#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
698#else
699#define IFETCH_FLAGS(pc)	0
700#endif
701
702        memReq->cmd = Read;
703        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
704                     IFETCH_FLAGS(xc->regs.pc));
705
706        fault = xc->translateInstReq(memReq);
707
708        if (fault == No_Fault)
709            fault = xc->mem->read(memReq, inst);
710
711        if (icacheInterface && fault == No_Fault) {
712            memReq->completionEvent = NULL;
713
714            memReq->time = curTick;
715            MemAccessResult result = icacheInterface->access(memReq);
716
717            // Ugly hack to get an event scheduled *only* if the access is
718            // a miss.  We really should add first-class support for this
719            // at some point.
720            if (result != MA_HIT && icacheInterface->doEvents()) {
721                memReq->completionEvent = &cacheCompletionEvent;
722                lastIcacheStall = curTick;
723                unscheduleTickEvent();
724                _status = IcacheMissStall;
725                return;
726            }
727        }
728    }
729
730    // If we've got a valid instruction (i.e., no fault on instruction
731    // fetch), then execute it.
732    if (fault == No_Fault) {
733
734        // keep an instruction count
735        numInst++;
736        numInsts++;
737
738        // check for instruction-count-based events
739        comInstEventQueue[0]->serviceEvents(numInst);
740
741        // decode the instruction
742        inst = htoa(inst);
743        curStaticInst = StaticInst<TheISA>::decode(inst);
744
745        traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
746                                         xc->regs.pc);
747
748#ifdef FULL_SYSTEM
749        xc->setInst(inst);
750#endif // FULL_SYSTEM
751
752        xc->func_exe_inst++;
753
754        fault = curStaticInst->execute(this, traceData);
755
756#ifdef FULL_SYSTEM
757        if (xc->fnbin)
758            xc->execute(curStaticInst.get());
759#endif
760
761        if (curStaticInst->isMemRef()) {
762            numMemRefs++;
763        }
764
765        if (curStaticInst->isLoad()) {
766            ++numLoad;
767            comLoadEventQueue[0]->serviceEvents(numLoad);
768        }
769
770        // If we have a dcache miss, then we can't finialize the instruction
771        // trace yet because we want to populate it with the data later
772        if (traceData &&
773                !(status() == DcacheMissStall && memReq->cmd.isRead())) {
774            traceData->finalize();
775        }
776
777        traceFunctions(xc->regs.pc);
778
779    }	// if (fault == No_Fault)
780
781    if (fault != No_Fault) {
782#ifdef FULL_SYSTEM
783        xc->ev5_trap(fault);
784#else // !FULL_SYSTEM
785        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
786#endif // FULL_SYSTEM
787    }
788    else {
789        // go to the next instruction
790        xc->regs.pc = xc->regs.npc;
791        xc->regs.npc += sizeof(MachInst);
792    }
793
794#ifdef FULL_SYSTEM
795    Addr oldpc;
796    do {
797        oldpc = xc->regs.pc;
798        system->pcEventQueue.service(xc);
799    } while (oldpc != xc->regs.pc);
800#endif
801
802    assert(status() == Running ||
803           status() == Idle ||
804           status() == DcacheMissStall);
805
806    if (status() == Running && !tickEvent.scheduled())
807        tickEvent.schedule(curTick + cycles(1));
808}
809
810
811////////////////////////////////////////////////////////////////////////
812//
813//  SimpleCPU Simulation Object
814//
815BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
816
817    Param<Counter> max_insts_any_thread;
818    Param<Counter> max_insts_all_threads;
819    Param<Counter> max_loads_any_thread;
820    Param<Counter> max_loads_all_threads;
821
822#ifdef FULL_SYSTEM
823    SimObjectParam<AlphaITB *> itb;
824    SimObjectParam<AlphaDTB *> dtb;
825    SimObjectParam<FunctionalMemory *> mem;
826    SimObjectParam<System *> system;
827    Param<int> mult;
828#else
829    SimObjectParam<Process *> workload;
830#endif // FULL_SYSTEM
831
832    Param<int> clock;
833    SimObjectParam<BaseMem *> icache;
834    SimObjectParam<BaseMem *> dcache;
835
836    Param<bool> defer_registration;
837    Param<int> width;
838    Param<bool> function_trace;
839    Param<Tick> function_trace_start;
840
841END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
842
843BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
844
845    INIT_PARAM(max_insts_any_thread,
846               "terminate when any thread reaches this inst count"),
847    INIT_PARAM(max_insts_all_threads,
848               "terminate when all threads have reached this inst count"),
849    INIT_PARAM(max_loads_any_thread,
850               "terminate when any thread reaches this load count"),
851    INIT_PARAM(max_loads_all_threads,
852               "terminate when all threads have reached this load count"),
853
854#ifdef FULL_SYSTEM
855    INIT_PARAM(itb, "Instruction TLB"),
856    INIT_PARAM(dtb, "Data TLB"),
857    INIT_PARAM(mem, "memory"),
858    INIT_PARAM(system, "system object"),
859    INIT_PARAM(mult, "system clock multiplier"),
860#else
861    INIT_PARAM(workload, "processes to run"),
862#endif // FULL_SYSTEM
863
864    INIT_PARAM(clock, "clock speed"),
865    INIT_PARAM(icache, "L1 instruction cache object"),
866    INIT_PARAM(dcache, "L1 data cache object"),
867    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
868    INIT_PARAM(width, "cpu width"),
869    INIT_PARAM(function_trace, "Enable function trace"),
870    INIT_PARAM(function_trace_start, "Cycle to start function trace")
871
872END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
873
874
875CREATE_SIM_OBJECT(SimpleCPU)
876{
877#ifdef FULL_SYSTEM
878    if (mult != 1)
879        panic("processor clock multiplier must be 1\n");
880#endif
881
882    SimpleCPU::Params *params = new SimpleCPU::Params();
883    params->name = getInstanceName();
884    params->numberOfThreads = 1;
885    params->max_insts_any_thread = max_insts_any_thread;
886    params->max_insts_all_threads = max_insts_all_threads;
887    params->max_loads_any_thread = max_loads_any_thread;
888    params->max_loads_all_threads = max_loads_all_threads;
889    params->deferRegistration = defer_registration;
890    params->clock = clock;
891    params->functionTrace = function_trace;
892    params->functionTraceStart = function_trace_start;
893    params->icache_interface = (icache) ? icache->getInterface() : NULL;
894    params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
895    params->width = width;
896
897#ifdef FULL_SYSTEM
898    params->itb = itb;
899    params->dtb = dtb;
900    params->mem = mem;
901    params->system = system;
902#else
903    params->process = workload;
904#endif
905
906    SimpleCPU *cpu = new SimpleCPU(params);
907    return cpu;
908}
909
910REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
911
912