base.cc revision 1129 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = multiplier;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue),
100      cpu(_cpu)
101{
102}
103
104void SimpleCPU::CacheCompletionEvent::process()
105{
106    cpu->processCacheCompletion();
107}
108
109const char *
110SimpleCPU::CacheCompletionEvent::description()
111{
112    return "SimpleCPU cache completion event";
113}
114
115#ifdef FULL_SYSTEM
116SimpleCPU::SimpleCPU(const string &_name,
117                     System *_system,
118                     Counter max_insts_any_thread,
119                     Counter max_insts_all_threads,
120                     Counter max_loads_any_thread,
121                     Counter max_loads_all_threads,
122                     AlphaITB *itb, AlphaDTB *dtb,
123                     FunctionalMemory *mem,
124                     MemInterface *icache_interface,
125                     MemInterface *dcache_interface,
126                     bool _def_reg, Tick freq)
127    : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
128              max_insts_any_thread, max_insts_all_threads,
129              max_loads_any_thread, max_loads_all_threads,
130              _system, freq),
131#else
132SimpleCPU::SimpleCPU(const string &_name, Process *_process,
133                     Counter max_insts_any_thread,
134                     Counter max_insts_all_threads,
135                     Counter max_loads_any_thread,
136                     Counter max_loads_all_threads,
137                     MemInterface *icache_interface,
138                     MemInterface *dcache_interface,
139                     bool _def_reg)
140    : BaseCPU(_name, /* number_of_threads */ 1, _def_reg,
141              max_insts_any_thread, max_insts_all_threads,
142              max_loads_any_thread, max_loads_all_threads),
143#endif
144      tickEvent(this), xc(NULL), cacheCompletionEvent(this)
145{
146    _status = Idle;
147#ifdef FULL_SYSTEM
148    xc = new ExecContext(this, 0, system, itb, dtb, mem);
149
150    // initialize CPU, including PC
151    TheISA::initCPU(&xc->regs);
152#else
153    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
154#endif // !FULL_SYSTEM
155
156    icacheInterface = icache_interface;
157    dcacheInterface = dcache_interface;
158
159    memReq = new MemReq();
160    memReq->xc = xc;
161    memReq->asid = 0;
162    memReq->data = new uint8_t[64];
163
164    numInst = 0;
165    startNumInst = 0;
166    numLoad = 0;
167    startNumLoad = 0;
168    lastIcacheStall = 0;
169    lastDcacheStall = 0;
170
171    execContexts.push_back(xc);
172}
173
174SimpleCPU::~SimpleCPU()
175{
176}
177
178void
179SimpleCPU::switchOut()
180{
181    _status = SwitchedOut;
182    if (tickEvent.scheduled())
183        tickEvent.squash();
184}
185
186
187void
188SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
189{
190    BaseCPU::takeOverFrom(oldCPU);
191
192    assert(!tickEvent.scheduled());
193
194    // if any of this CPU's ExecContexts are active, mark the CPU as
195    // running and schedule its tick event.
196    for (int i = 0; i < execContexts.size(); ++i) {
197        ExecContext *xc = execContexts[i];
198        if (xc->status() == ExecContext::Active && _status != Running) {
199            _status = Running;
200            tickEvent.schedule(curTick);
201        }
202    }
203
204    oldCPU->switchOut();
205}
206
207
208void
209SimpleCPU::activateContext(int thread_num, int delay)
210{
211    assert(thread_num == 0);
212    assert(xc);
213
214    assert(_status == Idle);
215    notIdleFraction++;
216    scheduleTickEvent(delay);
217    _status = Running;
218}
219
220
221void
222SimpleCPU::suspendContext(int thread_num)
223{
224    assert(thread_num == 0);
225    assert(xc);
226
227    assert(_status == Running);
228    notIdleFraction--;
229    unscheduleTickEvent();
230    _status = Idle;
231}
232
233
234void
235SimpleCPU::deallocateContext(int thread_num)
236{
237    // for now, these are equivalent
238    suspendContext(thread_num);
239}
240
241
242void
243SimpleCPU::haltContext(int thread_num)
244{
245    // for now, these are equivalent
246    suspendContext(thread_num);
247}
248
249
250void
251SimpleCPU::regStats()
252{
253    using namespace Stats;
254
255    BaseCPU::regStats();
256
257    numInsts
258        .name(name() + ".num_insts")
259        .desc("Number of instructions executed")
260        ;
261
262    numMemRefs
263        .name(name() + ".num_refs")
264        .desc("Number of memory references")
265        ;
266
267    notIdleFraction
268        .name(name() + ".not_idle_fraction")
269        .desc("Percentage of non-idle cycles")
270        ;
271
272    idleFraction
273        .name(name() + ".idle_fraction")
274        .desc("Percentage of idle cycles")
275        ;
276
277    icacheStallCycles
278        .name(name() + ".icache_stall_cycles")
279        .desc("ICache total stall cycles")
280        .prereq(icacheStallCycles)
281        ;
282
283    dcacheStallCycles
284        .name(name() + ".dcache_stall_cycles")
285        .desc("DCache total stall cycles")
286        .prereq(dcacheStallCycles)
287        ;
288
289    idleFraction = constant(1.0) - notIdleFraction;
290}
291
292void
293SimpleCPU::resetStats()
294{
295    startNumInst = numInst;
296    notIdleFraction = (_status != Idle);
297}
298
299void
300SimpleCPU::serialize(ostream &os)
301{
302    BaseCPU::serialize(os);
303    SERIALIZE_ENUM(_status);
304    SERIALIZE_SCALAR(inst);
305    nameOut(os, csprintf("%s.xc", name()));
306    xc->serialize(os);
307    nameOut(os, csprintf("%s.tickEvent", name()));
308    tickEvent.serialize(os);
309    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
310    cacheCompletionEvent.serialize(os);
311}
312
313void
314SimpleCPU::unserialize(Checkpoint *cp, const string &section)
315{
316    BaseCPU::unserialize(cp, section);
317    UNSERIALIZE_ENUM(_status);
318    UNSERIALIZE_SCALAR(inst);
319    xc->unserialize(cp, csprintf("%s.xc", section));
320    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
321    cacheCompletionEvent
322        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
323}
324
325void
326change_thread_state(int thread_number, int activate, int priority)
327{
328}
329
330Fault
331SimpleCPU::copySrcTranslate(Addr src)
332{
333    static bool no_warn = true;
334    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
335    // Only support block sizes of 64 atm.
336    assert(blk_size == 64);
337    int offset = src & (blk_size - 1);
338
339    // Make sure block doesn't span page
340    if (no_warn &&
341        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
342        (src >> 40) != 0xfffffc) {
343        warn("Copied block source spans pages %x.", src);
344        no_warn = false;
345    }
346
347    memReq->reset(src & ~(blk_size - 1), blk_size);
348
349    // translate to physical address
350    Fault fault = xc->translateDataReadReq(memReq);
351
352    assert(fault != Alignment_Fault);
353
354    if (fault == No_Fault) {
355        xc->copySrcAddr = src;
356        xc->copySrcPhysAddr = memReq->paddr + offset;
357    } else {
358        xc->copySrcAddr = 0;
359        xc->copySrcPhysAddr = 0;
360    }
361    return fault;
362}
363
364Fault
365SimpleCPU::copy(Addr dest)
366{
367    static bool no_warn = true;
368    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
369    // Only support block sizes of 64 atm.
370    assert(blk_size == 64);
371    uint8_t data[blk_size];
372    //assert(xc->copySrcAddr);
373    int offset = dest & (blk_size - 1);
374
375    // Make sure block doesn't span page
376    if (no_warn &&
377        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
378        (dest >> 40) != 0xfffffc) {
379        no_warn = false;
380        warn("Copied block destination spans pages %x. ", dest);
381    }
382
383    memReq->reset(dest & ~(blk_size -1), blk_size);
384    // translate to physical address
385    Fault fault = xc->translateDataWriteReq(memReq);
386
387    assert(fault != Alignment_Fault);
388
389    if (fault == No_Fault) {
390        Addr dest_addr = memReq->paddr + offset;
391        // Need to read straight from memory since we have more than 8 bytes.
392        memReq->paddr = xc->copySrcPhysAddr;
393        xc->mem->read(memReq, data);
394        memReq->paddr = dest_addr;
395        xc->mem->write(memReq, data);
396        if (dcacheInterface) {
397            memReq->cmd = Copy;
398            memReq->completionEvent = NULL;
399            memReq->paddr = xc->copySrcPhysAddr;
400            memReq->dest = dest_addr;
401            memReq->size = 64;
402            memReq->time = curTick;
403            dcacheInterface->access(memReq);
404        }
405    }
406    return fault;
407}
408
409// precise architected memory state accessor macros
410template <class T>
411Fault
412SimpleCPU::read(Addr addr, T &data, unsigned flags)
413{
414    memReq->reset(addr, sizeof(T), flags);
415
416    // translate to physical address
417    Fault fault = xc->translateDataReadReq(memReq);
418
419    // do functional access
420    if (fault == No_Fault)
421        fault = xc->read(memReq, data);
422
423    if (traceData) {
424        traceData->setAddr(addr);
425        if (fault == No_Fault)
426            traceData->setData(data);
427    }
428
429    // if we have a cache, do cache access too
430    if (fault == No_Fault && dcacheInterface) {
431        memReq->cmd = Read;
432        memReq->completionEvent = NULL;
433        memReq->time = curTick;
434        MemAccessResult result = dcacheInterface->access(memReq);
435
436        // Ugly hack to get an event scheduled *only* if the access is
437        // a miss.  We really should add first-class support for this
438        // at some point.
439        if (result != MA_HIT && dcacheInterface->doEvents()) {
440            memReq->completionEvent = &cacheCompletionEvent;
441            lastDcacheStall = curTick;
442            unscheduleTickEvent();
443            _status = DcacheMissStall;
444        }
445    }
446
447    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
448        recordEvent("Uncached Read");
449
450    return fault;
451}
452
453#ifndef DOXYGEN_SHOULD_SKIP_THIS
454
455template
456Fault
457SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
458
459template
460Fault
461SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
462
463template
464Fault
465SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
466
467template
468Fault
469SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
470
471#endif //DOXYGEN_SHOULD_SKIP_THIS
472
473template<>
474Fault
475SimpleCPU::read(Addr addr, double &data, unsigned flags)
476{
477    return read(addr, *(uint64_t*)&data, flags);
478}
479
480template<>
481Fault
482SimpleCPU::read(Addr addr, float &data, unsigned flags)
483{
484    return read(addr, *(uint32_t*)&data, flags);
485}
486
487
488template<>
489Fault
490SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
491{
492    return read(addr, (uint32_t&)data, flags);
493}
494
495
496template <class T>
497Fault
498SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
499{
500    if (traceData) {
501        traceData->setAddr(addr);
502        traceData->setData(data);
503    }
504
505    memReq->reset(addr, sizeof(T), flags);
506
507    // translate to physical address
508    Fault fault = xc->translateDataWriteReq(memReq);
509
510    // do functional access
511    if (fault == No_Fault)
512        fault = xc->write(memReq, data);
513
514    if (fault == No_Fault && dcacheInterface) {
515        memReq->cmd = Write;
516        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
517        memReq->completionEvent = NULL;
518        memReq->time = curTick;
519        MemAccessResult result = dcacheInterface->access(memReq);
520
521        // Ugly hack to get an event scheduled *only* if the access is
522        // a miss.  We really should add first-class support for this
523        // at some point.
524        if (result != MA_HIT && dcacheInterface->doEvents()) {
525            memReq->completionEvent = &cacheCompletionEvent;
526            lastDcacheStall = curTick;
527            unscheduleTickEvent();
528            _status = DcacheMissStall;
529        }
530    }
531
532    if (res && (fault == No_Fault))
533        *res = memReq->result;
534
535    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
536        recordEvent("Uncached Write");
537
538    return fault;
539}
540
541
542#ifndef DOXYGEN_SHOULD_SKIP_THIS
543template
544Fault
545SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
546
547template
548Fault
549SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
550
551template
552Fault
553SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
554
555template
556Fault
557SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
558
559#endif //DOXYGEN_SHOULD_SKIP_THIS
560
561template<>
562Fault
563SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
564{
565    return write(*(uint64_t*)&data, addr, flags, res);
566}
567
568template<>
569Fault
570SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
571{
572    return write(*(uint32_t*)&data, addr, flags, res);
573}
574
575
576template<>
577Fault
578SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
579{
580    return write((uint32_t)data, addr, flags, res);
581}
582
583
584#ifdef FULL_SYSTEM
585Addr
586SimpleCPU::dbg_vtophys(Addr addr)
587{
588    return vtophys(xc, addr);
589}
590#endif // FULL_SYSTEM
591
592Tick save_cycle = 0;
593
594
595void
596SimpleCPU::processCacheCompletion()
597{
598    switch (status()) {
599      case IcacheMissStall:
600        icacheStallCycles += curTick - lastIcacheStall;
601        _status = IcacheMissComplete;
602        scheduleTickEvent(1);
603        break;
604      case DcacheMissStall:
605        dcacheStallCycles += curTick - lastDcacheStall;
606        _status = Running;
607        scheduleTickEvent(1);
608        break;
609      case SwitchedOut:
610        // If this CPU has been switched out due to sampling/warm-up,
611        // ignore any further status changes (e.g., due to cache
612        // misses outstanding at the time of the switch).
613        return;
614      default:
615        panic("SimpleCPU::processCacheCompletion: bad state");
616        break;
617    }
618}
619
620#ifdef FULL_SYSTEM
621void
622SimpleCPU::post_interrupt(int int_num, int index)
623{
624    BaseCPU::post_interrupt(int_num, index);
625
626    if (xc->status() == ExecContext::Suspended) {
627                DPRINTF(IPI,"Suspended Processor awoke\n");
628        xc->activate();
629    }
630}
631#endif // FULL_SYSTEM
632
633/* start simulation, program loaded, processor precise state initialized */
634void
635SimpleCPU::tick()
636{
637    numCycles++;
638
639    traceData = NULL;
640
641    Fault fault = No_Fault;
642
643#ifdef FULL_SYSTEM
644    if (AlphaISA::check_interrupts &&
645        xc->cpu->check_interrupts() &&
646        !PC_PAL(xc->regs.pc) &&
647        status() != IcacheMissComplete) {
648        int ipl = 0;
649        int summary = 0;
650        AlphaISA::check_interrupts = 0;
651        IntReg *ipr = xc->regs.ipr;
652
653        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
654            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
655                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
656                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
657                    // See table 4-19 of 21164 hardware reference
658                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
659                    summary |= (ULL(1) << i);
660                }
661            }
662        }
663
664        uint64_t interrupts = xc->cpu->intr_status();
665        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
666            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
667            if (interrupts & (ULL(1) << i)) {
668                // See table 4-19 of 21164 hardware reference
669                ipl = i;
670                summary |= (ULL(1) << i);
671            }
672        }
673
674        if (ipr[TheISA::IPR_ASTRR])
675            panic("asynchronous traps not implemented\n");
676
677        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
678            ipr[TheISA::IPR_ISR] = summary;
679            ipr[TheISA::IPR_INTID] = ipl;
680            xc->ev5_trap(Interrupt_Fault);
681
682            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
683                    ipr[TheISA::IPR_IPLR], ipl, summary);
684        }
685    }
686#endif
687
688    // maintain $r0 semantics
689    xc->regs.intRegFile[ZeroReg] = 0;
690#ifdef TARGET_ALPHA
691    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
692#endif // TARGET_ALPHA
693
694    if (status() == IcacheMissComplete) {
695        // We've already fetched an instruction and were stalled on an
696        // I-cache miss.  No need to fetch it again.
697
698        // Set status to running; tick event will get rescheduled if
699        // necessary at end of tick() function.
700        _status = Running;
701    }
702    else {
703        // Try to fetch an instruction
704
705        // set up memory request for instruction fetch
706#ifdef FULL_SYSTEM
707#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
708#else
709#define IFETCH_FLAGS(pc)	0
710#endif
711
712        memReq->cmd = Read;
713        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
714                     IFETCH_FLAGS(xc->regs.pc));
715
716        fault = xc->translateInstReq(memReq);
717
718        if (fault == No_Fault)
719            fault = xc->mem->read(memReq, inst);
720
721        if (icacheInterface && fault == No_Fault) {
722            memReq->completionEvent = NULL;
723
724            memReq->time = curTick;
725            MemAccessResult result = icacheInterface->access(memReq);
726
727            // Ugly hack to get an event scheduled *only* if the access is
728            // a miss.  We really should add first-class support for this
729            // at some point.
730            if (result != MA_HIT && icacheInterface->doEvents()) {
731                memReq->completionEvent = &cacheCompletionEvent;
732                lastIcacheStall = curTick;
733                unscheduleTickEvent();
734                _status = IcacheMissStall;
735                return;
736            }
737        }
738    }
739
740    // If we've got a valid instruction (i.e., no fault on instruction
741    // fetch), then execute it.
742    if (fault == No_Fault) {
743
744        // keep an instruction count
745        numInst++;
746        numInsts++;
747
748        // check for instruction-count-based events
749        comInstEventQueue[0]->serviceEvents(numInst);
750
751        // decode the instruction
752    inst = htoa(inst);
753        StaticInstPtr<TheISA> si(inst);
754
755        traceData = Trace::getInstRecord(curTick, xc, this, si,
756                                         xc->regs.pc);
757
758#ifdef FULL_SYSTEM
759        xc->setInst(inst);
760#endif // FULL_SYSTEM
761
762        xc->func_exe_inst++;
763
764        fault = si->execute(this, traceData);
765
766#ifdef FULL_SYSTEM
767        if (xc->fnbin)
768            xc->execute(si.get());
769#endif
770
771        if (si->isMemRef()) {
772            numMemRefs++;
773        }
774
775        if (si->isLoad()) {
776            ++numLoad;
777            comLoadEventQueue[0]->serviceEvents(numLoad);
778        }
779
780        if (traceData)
781            traceData->finalize();
782
783    }	// if (fault == No_Fault)
784
785    if (fault != No_Fault) {
786#ifdef FULL_SYSTEM
787        xc->ev5_trap(fault);
788#else // !FULL_SYSTEM
789        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
790#endif // FULL_SYSTEM
791    }
792    else {
793        // go to the next instruction
794        xc->regs.pc = xc->regs.npc;
795        xc->regs.npc += sizeof(MachInst);
796    }
797
798#ifdef FULL_SYSTEM
799    Addr oldpc;
800    do {
801        oldpc = xc->regs.pc;
802        system->pcEventQueue.service(xc);
803    } while (oldpc != xc->regs.pc);
804#endif
805
806    assert(status() == Running ||
807           status() == Idle ||
808           status() == DcacheMissStall);
809
810    if (status() == Running && !tickEvent.scheduled())
811        tickEvent.schedule(curTick + 1);
812}
813
814
815////////////////////////////////////////////////////////////////////////
816//
817//  SimpleCPU Simulation Object
818//
819BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
820
821    Param<Counter> max_insts_any_thread;
822    Param<Counter> max_insts_all_threads;
823    Param<Counter> max_loads_any_thread;
824    Param<Counter> max_loads_all_threads;
825
826#ifdef FULL_SYSTEM
827    SimObjectParam<AlphaITB *> itb;
828    SimObjectParam<AlphaDTB *> dtb;
829    SimObjectParam<FunctionalMemory *> mem;
830    SimObjectParam<System *> system;
831    Param<int> mult;
832#else
833    SimObjectParam<Process *> workload;
834#endif // FULL_SYSTEM
835
836    SimObjectParam<BaseMem *> icache;
837    SimObjectParam<BaseMem *> dcache;
838
839    Param<bool> defer_registration;
840    Param<int> multiplier;
841
842END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
843
844BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
845
846    INIT_PARAM_DFLT(max_insts_any_thread,
847                    "terminate when any thread reaches this inst count",
848                    0),
849    INIT_PARAM_DFLT(max_insts_all_threads,
850                    "terminate when all threads have reached this inst count",
851                    0),
852    INIT_PARAM_DFLT(max_loads_any_thread,
853                    "terminate when any thread reaches this load count",
854                    0),
855    INIT_PARAM_DFLT(max_loads_all_threads,
856                    "terminate when all threads have reached this load count",
857                    0),
858
859#ifdef FULL_SYSTEM
860    INIT_PARAM(itb, "Instruction TLB"),
861    INIT_PARAM(dtb, "Data TLB"),
862    INIT_PARAM(mem, "memory"),
863    INIT_PARAM(system, "system object"),
864    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
865#else
866    INIT_PARAM(workload, "processes to run"),
867#endif // FULL_SYSTEM
868
869    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
870    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
871    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
872                    "(for sampling)", false),
873
874    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
875
876END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
877
878
879CREATE_SIM_OBJECT(SimpleCPU)
880{
881    SimpleCPU *cpu;
882#ifdef FULL_SYSTEM
883    if (mult != 1)
884        panic("processor clock multiplier must be 1\n");
885
886    cpu = new SimpleCPU(getInstanceName(), system,
887                        max_insts_any_thread, max_insts_all_threads,
888                        max_loads_any_thread, max_loads_all_threads,
889                        itb, dtb, mem,
890                        (icache) ? icache->getInterface() : NULL,
891                        (dcache) ? dcache->getInterface() : NULL,
892                        defer_registration,
893                        ticksPerSecond * mult);
894#else
895
896    cpu = new SimpleCPU(getInstanceName(), workload,
897                        max_insts_any_thread, max_insts_all_threads,
898                        max_loads_any_thread, max_loads_all_threads,
899                        (icache) ? icache->getInterface() : NULL,
900                        (dcache) ? dcache->getInterface() : NULL,
901                        defer_registration);
902
903#endif // FULL_SYSTEM
904
905    cpu->setTickMultiplier(multiplier);
906
907    return cpu;
908}
909
910REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
911
912