base.cc revision 1121
15081Sgblack@eecs.umich.edu/* 25081Sgblack@eecs.umich.edu * Copyright (c) 2002-2004 The Regents of The University of Michigan 35081Sgblack@eecs.umich.edu * All rights reserved. 47087Snate@binkert.org * 57087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org * modification, are permitted provided that the following conditions are 77087Snate@binkert.org * met: redistributions of source code must retain the above copyright 87087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org * documentation and/or other materials provided with the distribution; 125081Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137087Snate@binkert.org * contributors may be used to endorse or promote products derived from 147087Snate@binkert.org * this software without specific prior written permission. 157087Snate@binkert.org * 167087Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215081Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227087Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235081Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245081Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255081Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265081Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275081Sgblack@eecs.umich.edu */ 285081Sgblack@eecs.umich.edu 295081Sgblack@eecs.umich.edu#include <cmath> 305081Sgblack@eecs.umich.edu#include <cstdio> 315081Sgblack@eecs.umich.edu#include <cstdlib> 325081Sgblack@eecs.umich.edu#include <iostream> 335081Sgblack@eecs.umich.edu#include <iomanip> 345081Sgblack@eecs.umich.edu#include <list> 355081Sgblack@eecs.umich.edu#include <sstream> 365081Sgblack@eecs.umich.edu#include <string> 375081Sgblack@eecs.umich.edu 385081Sgblack@eecs.umich.edu#include "base/cprintf.hh" 395081Sgblack@eecs.umich.edu#include "base/inifile.hh" 405081Sgblack@eecs.umich.edu#include "base/loader/symtab.hh" 415081Sgblack@eecs.umich.edu#include "base/misc.hh" 425081Sgblack@eecs.umich.edu#include "base/pollevent.hh" 435081Sgblack@eecs.umich.edu#include "base/range.hh" 445081Sgblack@eecs.umich.edu#include "base/trace.hh" 455081Sgblack@eecs.umich.edu#include "base/stats/events.hh" 466463Sgblack@eecs.umich.edu#include "cpu/base_cpu.hh" 475081Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 486463Sgblack@eecs.umich.edu#include "cpu/exetrace.hh" 495081Sgblack@eecs.umich.edu#include "cpu/full_cpu/smt.hh" 505081Sgblack@eecs.umich.edu#include "cpu/simple_cpu/simple_cpu.hh" 515081Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 525081Sgblack@eecs.umich.edu#include "mem/base_mem.hh" 535081Sgblack@eecs.umich.edu#include "mem/mem_interface.hh" 546463Sgblack@eecs.umich.edu#include "sim/builder.hh" 555081Sgblack@eecs.umich.edu#include "sim/debug.hh" 566463Sgblack@eecs.umich.edu#include "sim/host.hh" 575081Sgblack@eecs.umich.edu#include "sim/sim_events.hh" 585081Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 595081Sgblack@eecs.umich.edu#include "sim/stats.hh" 605081Sgblack@eecs.umich.edu 615081Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 625081Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 636463Sgblack@eecs.umich.edu#include "dev/alpha_access.h" 645081Sgblack@eecs.umich.edu#include "dev/pciareg.h" 656463Sgblack@eecs.umich.edu#include "mem/functional_mem/memory_control.hh" 665081Sgblack@eecs.umich.edu#include "mem/functional_mem/physical_memory.hh" 675081Sgblack@eecs.umich.edu#include "sim/system.hh" 685081Sgblack@eecs.umich.edu#include "targetarch/alpha_memory.hh" 695081Sgblack@eecs.umich.edu#include "targetarch/vtophys.hh" 705081Sgblack@eecs.umich.edu#else // !FULL_SYSTEM 715081Sgblack@eecs.umich.edu#include "eio/eio.hh" 725081Sgblack@eecs.umich.edu#include "mem/functional_mem/functional_memory.hh" 735081Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 746463Sgblack@eecs.umich.edu 755081Sgblack@eecs.umich.eduusing namespace std; 766463Sgblack@eecs.umich.edu 775081Sgblack@eecs.umich.eduSimpleCPU::TickEvent::TickEvent(SimpleCPU *c) 785081Sgblack@eecs.umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) 795081Sgblack@eecs.umich.edu{ 805081Sgblack@eecs.umich.edu} 815081Sgblack@eecs.umich.edu 826463Sgblack@eecs.umich.eduvoid 835081Sgblack@eecs.umich.eduSimpleCPU::TickEvent::process() 846463Sgblack@eecs.umich.edu{ 855081Sgblack@eecs.umich.edu int count = multiplier; 865081Sgblack@eecs.umich.edu do { 875081Sgblack@eecs.umich.edu cpu->tick(); 885081Sgblack@eecs.umich.edu } while (--count > 0 && cpu->status() == Running); 895081Sgblack@eecs.umich.edu} 905081Sgblack@eecs.umich.edu 916463Sgblack@eecs.umich.educonst char * 925081Sgblack@eecs.umich.eduSimpleCPU::TickEvent::description() 936463Sgblack@eecs.umich.edu{ 945081Sgblack@eecs.umich.edu return "SimpleCPU tick event"; 955081Sgblack@eecs.umich.edu} 965081Sgblack@eecs.umich.edu 975081Sgblack@eecs.umich.edu 985081Sgblack@eecs.umich.eduSimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) 995081Sgblack@eecs.umich.edu : Event(&mainEventQueue), 1005081Sgblack@eecs.umich.edu cpu(_cpu) 1015081Sgblack@eecs.umich.edu{ 1026463Sgblack@eecs.umich.edu} 1035081Sgblack@eecs.umich.edu 1046463Sgblack@eecs.umich.eduvoid SimpleCPU::CacheCompletionEvent::process() 1055081Sgblack@eecs.umich.edu{ 1065081Sgblack@eecs.umich.edu cpu->processCacheCompletion(); 1075081Sgblack@eecs.umich.edu} 1085081Sgblack@eecs.umich.edu 1095081Sgblack@eecs.umich.educonst char * 1106463Sgblack@eecs.umich.eduSimpleCPU::CacheCompletionEvent::description() 1115081Sgblack@eecs.umich.edu{ 1126463Sgblack@eecs.umich.edu return "SimpleCPU cache completion event"; 1135081Sgblack@eecs.umich.edu} 1145081Sgblack@eecs.umich.edu 1155081Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1165081Sgblack@eecs.umich.eduSimpleCPU::SimpleCPU(const string &_name, 1175081Sgblack@eecs.umich.edu System *_system, 1185081Sgblack@eecs.umich.edu Counter max_insts_any_thread, 1196463Sgblack@eecs.umich.edu Counter max_insts_all_threads, 1205081Sgblack@eecs.umich.edu Counter max_loads_any_thread, 1216463Sgblack@eecs.umich.edu Counter max_loads_all_threads, 1225081Sgblack@eecs.umich.edu AlphaITB *itb, AlphaDTB *dtb, 1235081Sgblack@eecs.umich.edu FunctionalMemory *mem, 1245081Sgblack@eecs.umich.edu MemInterface *icache_interface, 1255081Sgblack@eecs.umich.edu MemInterface *dcache_interface, 1265081Sgblack@eecs.umich.edu bool _def_reg, Tick freq) 1275081Sgblack@eecs.umich.edu : BaseCPU(_name, /* number_of_threads */ 1, 1285081Sgblack@eecs.umich.edu max_insts_any_thread, max_insts_all_threads, 1295081Sgblack@eecs.umich.edu max_loads_any_thread, max_loads_all_threads, 1306463Sgblack@eecs.umich.edu _system, freq), 1315081Sgblack@eecs.umich.edu#else 1326463Sgblack@eecs.umich.eduSimpleCPU::SimpleCPU(const string &_name, Process *_process, 1335081Sgblack@eecs.umich.edu Counter max_insts_any_thread, 1345081Sgblack@eecs.umich.edu Counter max_insts_all_threads, 1355081Sgblack@eecs.umich.edu Counter max_loads_any_thread, 1365081Sgblack@eecs.umich.edu Counter max_loads_all_threads, 1375081Sgblack@eecs.umich.edu MemInterface *icache_interface, 1386463Sgblack@eecs.umich.edu MemInterface *dcache_interface, 1395081Sgblack@eecs.umich.edu bool _def_reg) 1406463Sgblack@eecs.umich.edu : BaseCPU(_name, /* number_of_threads */ 1, 1415081Sgblack@eecs.umich.edu max_insts_any_thread, max_insts_all_threads, 1425081Sgblack@eecs.umich.edu max_loads_any_thread, max_loads_all_threads), 1435081Sgblack@eecs.umich.edu#endif 1445081Sgblack@eecs.umich.edu tickEvent(this), xc(NULL), defer_registration(_def_reg), 1455081Sgblack@eecs.umich.edu cacheCompletionEvent(this) 1465081Sgblack@eecs.umich.edu{ 1476463Sgblack@eecs.umich.edu _status = Idle; 1485081Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1496463Sgblack@eecs.umich.edu xc = new ExecContext(this, 0, system, itb, dtb, mem); 1505081Sgblack@eecs.umich.edu 1515081Sgblack@eecs.umich.edu // initialize CPU, including PC 1525081Sgblack@eecs.umich.edu TheISA::initCPU(&xc->regs); 1535081Sgblack@eecs.umich.edu#else 1546463Sgblack@eecs.umich.edu xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0); 1555081Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 1566463Sgblack@eecs.umich.edu 1575081Sgblack@eecs.umich.edu icacheInterface = icache_interface; 1585081Sgblack@eecs.umich.edu dcacheInterface = dcache_interface; 1595081Sgblack@eecs.umich.edu 1605081Sgblack@eecs.umich.edu memReq = new MemReq(); 1615081Sgblack@eecs.umich.edu memReq->xc = xc; 1626463Sgblack@eecs.umich.edu memReq->asid = 0; 1635081Sgblack@eecs.umich.edu memReq->data = new uint8_t[64]; 1646463Sgblack@eecs.umich.edu 1655081Sgblack@eecs.umich.edu numInst = 0; 1665081Sgblack@eecs.umich.edu startNumInst = 0; 1675081Sgblack@eecs.umich.edu numLoad = 0; 1685081Sgblack@eecs.umich.edu startNumLoad = 0; 1695081Sgblack@eecs.umich.edu lastIcacheStall = 0; 1705081Sgblack@eecs.umich.edu lastDcacheStall = 0; 1716463Sgblack@eecs.umich.edu 1725081Sgblack@eecs.umich.edu execContexts.push_back(xc); 1736463Sgblack@eecs.umich.edu} 1745081Sgblack@eecs.umich.edu 1755081Sgblack@eecs.umich.eduSimpleCPU::~SimpleCPU() 1765081Sgblack@eecs.umich.edu{ 1775081Sgblack@eecs.umich.edu} 1785081Sgblack@eecs.umich.edu 1795081Sgblack@eecs.umich.eduvoid SimpleCPU::init() 1805081Sgblack@eecs.umich.edu{ 1815081Sgblack@eecs.umich.edu if (!defer_registration) { 1825081Sgblack@eecs.umich.edu this->registerExecContexts(); 1836463Sgblack@eecs.umich.edu } 1845081Sgblack@eecs.umich.edu} 1856463Sgblack@eecs.umich.edu 1865081Sgblack@eecs.umich.eduvoid 1875081Sgblack@eecs.umich.eduSimpleCPU::switchOut() 1885081Sgblack@eecs.umich.edu{ 1895081Sgblack@eecs.umich.edu _status = SwitchedOut; 1905081Sgblack@eecs.umich.edu if (tickEvent.scheduled()) 1915081Sgblack@eecs.umich.edu tickEvent.squash(); 1926463Sgblack@eecs.umich.edu} 1935081Sgblack@eecs.umich.edu 1946463Sgblack@eecs.umich.edu 1955081Sgblack@eecs.umich.eduvoid 1965081Sgblack@eecs.umich.eduSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1975081Sgblack@eecs.umich.edu{ 1985081Sgblack@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU); 1995081Sgblack@eecs.umich.edu 2005081Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 2018973Sgblack@eecs.umich.edu 2026463Sgblack@eecs.umich.edu // if any of this CPU's ExecContexts are active, mark the CPU as 2035081Sgblack@eecs.umich.edu // running and schedule its tick event. 2046463Sgblack@eecs.umich.edu for (int i = 0; i < execContexts.size(); ++i) { 2055081Sgblack@eecs.umich.edu ExecContext *xc = execContexts[i]; 2066514Sgblack@eecs.umich.edu if (xc->status() == ExecContext::Active && _status != Running) { 2076514Sgblack@eecs.umich.edu _status = Running; 2086514Sgblack@eecs.umich.edu tickEvent.schedule(curTick); 2096514Sgblack@eecs.umich.edu } 2106514Sgblack@eecs.umich.edu } 2116514Sgblack@eecs.umich.edu 2126514Sgblack@eecs.umich.edu oldCPU->switchOut(); 2136514Sgblack@eecs.umich.edu} 2146514Sgblack@eecs.umich.edu 2155081Sgblack@eecs.umich.edu 2165081Sgblack@eecs.umich.eduvoid 2175081Sgblack@eecs.umich.eduSimpleCPU::activateContext(int thread_num, int delay) 2185081Sgblack@eecs.umich.edu{ 2195081Sgblack@eecs.umich.edu assert(thread_num == 0); 2206514Sgblack@eecs.umich.edu assert(xc); 2216514Sgblack@eecs.umich.edu 2225081Sgblack@eecs.umich.edu assert(_status == Idle); 2236514Sgblack@eecs.umich.edu notIdleFraction++; 2245081Sgblack@eecs.umich.edu scheduleTickEvent(delay); 2256514Sgblack@eecs.umich.edu _status = Running; 2265081Sgblack@eecs.umich.edu} 2275081Sgblack@eecs.umich.edu 2285081Sgblack@eecs.umich.edu 2295081Sgblack@eecs.umich.eduvoid 2305081Sgblack@eecs.umich.eduSimpleCPU::suspendContext(int thread_num) 2315081Sgblack@eecs.umich.edu{ 2325081Sgblack@eecs.umich.edu assert(thread_num == 0); 2335081Sgblack@eecs.umich.edu assert(xc); 2345081Sgblack@eecs.umich.edu 2355081Sgblack@eecs.umich.edu assert(_status == Running); 2365661Sgblack@eecs.umich.edu notIdleFraction--; 2375081Sgblack@eecs.umich.edu unscheduleTickEvent(); 2385081Sgblack@eecs.umich.edu _status = Idle; 2395081Sgblack@eecs.umich.edu} 2406459Sgblack@eecs.umich.edu 2415081Sgblack@eecs.umich.edu 2426514Sgblack@eecs.umich.eduvoid 2435081Sgblack@eecs.umich.eduSimpleCPU::deallocateContext(int thread_num) 2445081Sgblack@eecs.umich.edu{ 2455081Sgblack@eecs.umich.edu // for now, these are equivalent 2465081Sgblack@eecs.umich.edu suspendContext(thread_num); 2475081Sgblack@eecs.umich.edu} 2486514Sgblack@eecs.umich.edu 2496514Sgblack@eecs.umich.edu 2505081Sgblack@eecs.umich.eduvoid 2516514Sgblack@eecs.umich.eduSimpleCPU::haltContext(int thread_num) 2525081Sgblack@eecs.umich.edu{ 2536514Sgblack@eecs.umich.edu // for now, these are equivalent 2545081Sgblack@eecs.umich.edu suspendContext(thread_num); 2555081Sgblack@eecs.umich.edu} 2565081Sgblack@eecs.umich.edu 2575081Sgblack@eecs.umich.edu 2585081Sgblack@eecs.umich.eduvoid 2595081Sgblack@eecs.umich.eduSimpleCPU::regStats() 2605081Sgblack@eecs.umich.edu{ 2615081Sgblack@eecs.umich.edu using namespace Stats; 2625081Sgblack@eecs.umich.edu 2635081Sgblack@eecs.umich.edu BaseCPU::regStats(); 2645081Sgblack@eecs.umich.edu 2655081Sgblack@eecs.umich.edu numInsts 2665081Sgblack@eecs.umich.edu .name(name() + ".num_insts") 2675661Sgblack@eecs.umich.edu .desc("Number of instructions executed") 2685081Sgblack@eecs.umich.edu ; 2695081Sgblack@eecs.umich.edu 2705081Sgblack@eecs.umich.edu numMemRefs 2715081Sgblack@eecs.umich.edu .name(name() + ".num_refs") 2725081Sgblack@eecs.umich.edu .desc("Number of memory references") 2736514Sgblack@eecs.umich.edu ; 2745081Sgblack@eecs.umich.edu 2755081Sgblack@eecs.umich.edu notIdleFraction 2765081Sgblack@eecs.umich.edu .name(name() + ".not_idle_fraction") 2775081Sgblack@eecs.umich.edu .desc("Percentage of non-idle cycles") 2785081Sgblack@eecs.umich.edu ; 2796514Sgblack@eecs.umich.edu 2806514Sgblack@eecs.umich.edu idleFraction 2815081Sgblack@eecs.umich.edu .name(name() + ".idle_fraction") 2825081Sgblack@eecs.umich.edu .desc("Percentage of idle cycles") 2835081Sgblack@eecs.umich.edu ; 2845081Sgblack@eecs.umich.edu 2856459Sgblack@eecs.umich.edu icacheStallCycles 2865081Sgblack@eecs.umich.edu .name(name() + ".icache_stall_cycles") 2875081Sgblack@eecs.umich.edu .desc("ICache total stall cycles") 2886514Sgblack@eecs.umich.edu .prereq(icacheStallCycles) 2896514Sgblack@eecs.umich.edu ; 2905081Sgblack@eecs.umich.edu 2916514Sgblack@eecs.umich.edu dcacheStallCycles 2925081Sgblack@eecs.umich.edu .name(name() + ".dcache_stall_cycles") 2935081Sgblack@eecs.umich.edu .desc("DCache total stall cycles") 2946514Sgblack@eecs.umich.edu .prereq(dcacheStallCycles) 2955081Sgblack@eecs.umich.edu ; 2966514Sgblack@eecs.umich.edu 2975081Sgblack@eecs.umich.edu idleFraction = constant(1.0) - notIdleFraction; 2985081Sgblack@eecs.umich.edu} 2996459Sgblack@eecs.umich.edu 3005081Sgblack@eecs.umich.eduvoid 3015081Sgblack@eecs.umich.eduSimpleCPU::resetStats() 3025081Sgblack@eecs.umich.edu{ 3036459Sgblack@eecs.umich.edu startNumInst = numInst; 3045081Sgblack@eecs.umich.edu notIdleFraction = (_status != Idle); 3055081Sgblack@eecs.umich.edu} 3065081Sgblack@eecs.umich.edu 3075081Sgblack@eecs.umich.eduvoid 3085081Sgblack@eecs.umich.eduSimpleCPU::serialize(ostream &os) 3095081Sgblack@eecs.umich.edu{ 3105081Sgblack@eecs.umich.edu BaseCPU::serialize(os); 3115081Sgblack@eecs.umich.edu SERIALIZE_ENUM(_status); 3125081Sgblack@eecs.umich.edu SERIALIZE_SCALAR(inst); 3135081Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.xc", name())); 3145081Sgblack@eecs.umich.edu xc->serialize(os); 3155081Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 3165081Sgblack@eecs.umich.edu tickEvent.serialize(os); 3175661Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 3185081Sgblack@eecs.umich.edu cacheCompletionEvent.serialize(os); 3195081Sgblack@eecs.umich.edu} 3205081Sgblack@eecs.umich.edu 3215081Sgblack@eecs.umich.eduvoid 3225081Sgblack@eecs.umich.eduSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 3235081Sgblack@eecs.umich.edu{ 3245081Sgblack@eecs.umich.edu BaseCPU::unserialize(cp, section); 3255081Sgblack@eecs.umich.edu UNSERIALIZE_ENUM(_status); 3265081Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(inst); 3275081Sgblack@eecs.umich.edu xc->unserialize(cp, csprintf("%s.xc", section)); 3285081Sgblack@eecs.umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 3295081Sgblack@eecs.umich.edu cacheCompletionEvent 3306459Sgblack@eecs.umich.edu .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); 3316459Sgblack@eecs.umich.edu} 3326459Sgblack@eecs.umich.edu 3336459Sgblack@eecs.umich.eduvoid 3345081Sgblack@eecs.umich.educhange_thread_state(int thread_number, int activate, int priority) 3355081Sgblack@eecs.umich.edu{ 3365081Sgblack@eecs.umich.edu} 3375081Sgblack@eecs.umich.edu 3385081Sgblack@eecs.umich.eduFault 3395081Sgblack@eecs.umich.eduSimpleCPU::copySrcTranslate(Addr src) 3405081Sgblack@eecs.umich.edu{ 3416514Sgblack@eecs.umich.edu static bool no_warn = true; 3425081Sgblack@eecs.umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3435081Sgblack@eecs.umich.edu // Only support block sizes of 64 atm. 3445081Sgblack@eecs.umich.edu assert(blk_size == 64); 3455081Sgblack@eecs.umich.edu int offset = src & (blk_size - 1); 3465081Sgblack@eecs.umich.edu 3475081Sgblack@eecs.umich.edu // Make sure block doesn't span page 3485081Sgblack@eecs.umich.edu if (no_warn && 3495081Sgblack@eecs.umich.edu (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) && 3506514Sgblack@eecs.umich.edu (src >> 40) != 0xfffffc) { 3515081Sgblack@eecs.umich.edu warn("Copied block source spans pages %x.", src); 3525081Sgblack@eecs.umich.edu no_warn = false; 3535081Sgblack@eecs.umich.edu } 3545081Sgblack@eecs.umich.edu 3555081Sgblack@eecs.umich.edu memReq->reset(src & ~(blk_size - 1), blk_size); 3566514Sgblack@eecs.umich.edu 3576514Sgblack@eecs.umich.edu // translate to physical address 3585081Sgblack@eecs.umich.edu Fault fault = xc->translateDataReadReq(memReq); 3595081Sgblack@eecs.umich.edu 3605081Sgblack@eecs.umich.edu assert(fault != Alignment_Fault); 3615081Sgblack@eecs.umich.edu 3625081Sgblack@eecs.umich.edu if (fault == No_Fault) { 3635081Sgblack@eecs.umich.edu xc->copySrcAddr = src; 3645081Sgblack@eecs.umich.edu xc->copySrcPhysAddr = memReq->paddr + offset; 3656514Sgblack@eecs.umich.edu } else { 3666514Sgblack@eecs.umich.edu xc->copySrcAddr = 0; 3675081Sgblack@eecs.umich.edu xc->copySrcPhysAddr = 0; 3686514Sgblack@eecs.umich.edu } 3695081Sgblack@eecs.umich.edu return fault; 3705081Sgblack@eecs.umich.edu} 3716514Sgblack@eecs.umich.edu 3725081Sgblack@eecs.umich.eduFault 3736514Sgblack@eecs.umich.eduSimpleCPU::copy(Addr dest) 3745081Sgblack@eecs.umich.edu{ 3755081Sgblack@eecs.umich.edu static bool no_warn = true; 3765081Sgblack@eecs.umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3775081Sgblack@eecs.umich.edu // Only support block sizes of 64 atm. 3785081Sgblack@eecs.umich.edu assert(blk_size == 64); 3795081Sgblack@eecs.umich.edu uint8_t data[blk_size]; 3805081Sgblack@eecs.umich.edu //assert(xc->copySrcAddr); 3815081Sgblack@eecs.umich.edu int offset = dest & (blk_size - 1); 3825081Sgblack@eecs.umich.edu 3835081Sgblack@eecs.umich.edu // Make sure block doesn't span page 3845081Sgblack@eecs.umich.edu if (no_warn && 3855081Sgblack@eecs.umich.edu (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) && 3865081Sgblack@eecs.umich.edu (dest >> 40) != 0xfffffc) { 3875081Sgblack@eecs.umich.edu no_warn = false; 3885081Sgblack@eecs.umich.edu warn("Copied block destination spans pages %x. ", dest); 3895081Sgblack@eecs.umich.edu } 3905081Sgblack@eecs.umich.edu 3915081Sgblack@eecs.umich.edu memReq->reset(dest & ~(blk_size -1), blk_size); 3925081Sgblack@eecs.umich.edu // translate to physical address 3935081Sgblack@eecs.umich.edu Fault fault = xc->translateDataWriteReq(memReq); 3945081Sgblack@eecs.umich.edu 3955081Sgblack@eecs.umich.edu assert(fault != Alignment_Fault); 3965661Sgblack@eecs.umich.edu 3975081Sgblack@eecs.umich.edu if (fault == No_Fault) { 3985081Sgblack@eecs.umich.edu Addr dest_addr = memReq->paddr + offset; 3995081Sgblack@eecs.umich.edu // Need to read straight from memory since we have more than 8 bytes. 4005081Sgblack@eecs.umich.edu memReq->paddr = xc->copySrcPhysAddr; 4015081Sgblack@eecs.umich.edu xc->mem->read(memReq, data); 4025081Sgblack@eecs.umich.edu memReq->paddr = dest_addr; 4035081Sgblack@eecs.umich.edu xc->mem->write(memReq, data); 4045081Sgblack@eecs.umich.edu if (dcacheInterface) { 4055081Sgblack@eecs.umich.edu memReq->cmd = Copy; 4065081Sgblack@eecs.umich.edu memReq->completionEvent = NULL; 4075081Sgblack@eecs.umich.edu memReq->paddr = xc->copySrcPhysAddr; 4085081Sgblack@eecs.umich.edu memReq->dest = dest_addr; 4095081Sgblack@eecs.umich.edu memReq->size = 64; 4105081Sgblack@eecs.umich.edu memReq->time = curTick; 4115081Sgblack@eecs.umich.edu dcacheInterface->access(memReq); 4125081Sgblack@eecs.umich.edu } 4135081Sgblack@eecs.umich.edu } 4145081Sgblack@eecs.umich.edu return fault; 4155081Sgblack@eecs.umich.edu} 4165081Sgblack@eecs.umich.edu 4175081Sgblack@eecs.umich.edu// precise architected memory state accessor macros 4185081Sgblack@eecs.umich.edutemplate <class T> 4195081Sgblack@eecs.umich.eduFault 4206514Sgblack@eecs.umich.eduSimpleCPU::read(Addr addr, T &data, unsigned flags) 4215081Sgblack@eecs.umich.edu{ 4225081Sgblack@eecs.umich.edu memReq->reset(addr, sizeof(T), flags); 4235081Sgblack@eecs.umich.edu 4245081Sgblack@eecs.umich.edu // translate to physical address 4255081Sgblack@eecs.umich.edu Fault fault = xc->translateDataReadReq(memReq); 4265081Sgblack@eecs.umich.edu 4275081Sgblack@eecs.umich.edu // do functional access 4285081Sgblack@eecs.umich.edu if (fault == No_Fault) 4295081Sgblack@eecs.umich.edu fault = xc->read(memReq, data); 4306514Sgblack@eecs.umich.edu 4316514Sgblack@eecs.umich.edu if (traceData) { 4326514Sgblack@eecs.umich.edu traceData->setAddr(addr); 4336514Sgblack@eecs.umich.edu if (fault == No_Fault) 4346514Sgblack@eecs.umich.edu traceData->setData(data); 4356514Sgblack@eecs.umich.edu } 4366514Sgblack@eecs.umich.edu 437 // if we have a cache, do cache access too 438 if (fault == No_Fault && dcacheInterface) { 439 memReq->cmd = Read; 440 memReq->completionEvent = NULL; 441 memReq->time = curTick; 442 MemAccessResult result = dcacheInterface->access(memReq); 443 444 // Ugly hack to get an event scheduled *only* if the access is 445 // a miss. We really should add first-class support for this 446 // at some point. 447 if (result != MA_HIT && dcacheInterface->doEvents()) { 448 memReq->completionEvent = &cacheCompletionEvent; 449 lastDcacheStall = curTick; 450 unscheduleTickEvent(); 451 _status = DcacheMissStall; 452 } 453 } 454 455 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 456 recordEvent("Uncached Read"); 457 458 return fault; 459} 460 461#ifndef DOXYGEN_SHOULD_SKIP_THIS 462 463template 464Fault 465SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 466 467template 468Fault 469SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 470 471template 472Fault 473SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 474 475template 476Fault 477SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 478 479#endif //DOXYGEN_SHOULD_SKIP_THIS 480 481template<> 482Fault 483SimpleCPU::read(Addr addr, double &data, unsigned flags) 484{ 485 return read(addr, *(uint64_t*)&data, flags); 486} 487 488template<> 489Fault 490SimpleCPU::read(Addr addr, float &data, unsigned flags) 491{ 492 return read(addr, *(uint32_t*)&data, flags); 493} 494 495 496template<> 497Fault 498SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 499{ 500 return read(addr, (uint32_t&)data, flags); 501} 502 503 504template <class T> 505Fault 506SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 507{ 508 if (traceData) { 509 traceData->setAddr(addr); 510 traceData->setData(data); 511 } 512 513 memReq->reset(addr, sizeof(T), flags); 514 515 // translate to physical address 516 Fault fault = xc->translateDataWriteReq(memReq); 517 518 // do functional access 519 if (fault == No_Fault) 520 fault = xc->write(memReq, data); 521 522 if (fault == No_Fault && dcacheInterface) { 523 memReq->cmd = Write; 524 memcpy(memReq->data,(uint8_t *)&data,memReq->size); 525 memReq->completionEvent = NULL; 526 memReq->time = curTick; 527 MemAccessResult result = dcacheInterface->access(memReq); 528 529 // Ugly hack to get an event scheduled *only* if the access is 530 // a miss. We really should add first-class support for this 531 // at some point. 532 if (result != MA_HIT && dcacheInterface->doEvents()) { 533 memReq->completionEvent = &cacheCompletionEvent; 534 lastDcacheStall = curTick; 535 unscheduleTickEvent(); 536 _status = DcacheMissStall; 537 } 538 } 539 540 if (res && (fault == No_Fault)) 541 *res = memReq->result; 542 543 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 544 recordEvent("Uncached Write"); 545 546 return fault; 547} 548 549 550#ifndef DOXYGEN_SHOULD_SKIP_THIS 551template 552Fault 553SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 554 555template 556Fault 557SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 558 559template 560Fault 561SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 562 563template 564Fault 565SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 566 567#endif //DOXYGEN_SHOULD_SKIP_THIS 568 569template<> 570Fault 571SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 572{ 573 return write(*(uint64_t*)&data, addr, flags, res); 574} 575 576template<> 577Fault 578SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 579{ 580 return write(*(uint32_t*)&data, addr, flags, res); 581} 582 583 584template<> 585Fault 586SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 587{ 588 return write((uint32_t)data, addr, flags, res); 589} 590 591 592#ifdef FULL_SYSTEM 593Addr 594SimpleCPU::dbg_vtophys(Addr addr) 595{ 596 return vtophys(xc, addr); 597} 598#endif // FULL_SYSTEM 599 600Tick save_cycle = 0; 601 602 603void 604SimpleCPU::processCacheCompletion() 605{ 606 switch (status()) { 607 case IcacheMissStall: 608 icacheStallCycles += curTick - lastIcacheStall; 609 _status = IcacheMissComplete; 610 scheduleTickEvent(1); 611 break; 612 case DcacheMissStall: 613 dcacheStallCycles += curTick - lastDcacheStall; 614 _status = Running; 615 scheduleTickEvent(1); 616 break; 617 case SwitchedOut: 618 // If this CPU has been switched out due to sampling/warm-up, 619 // ignore any further status changes (e.g., due to cache 620 // misses outstanding at the time of the switch). 621 return; 622 default: 623 panic("SimpleCPU::processCacheCompletion: bad state"); 624 break; 625 } 626} 627 628#ifdef FULL_SYSTEM 629void 630SimpleCPU::post_interrupt(int int_num, int index) 631{ 632 BaseCPU::post_interrupt(int_num, index); 633 634 if (xc->status() == ExecContext::Suspended) { 635 DPRINTF(IPI,"Suspended Processor awoke\n"); 636 xc->activate(); 637 } 638} 639#endif // FULL_SYSTEM 640 641/* start simulation, program loaded, processor precise state initialized */ 642void 643SimpleCPU::tick() 644{ 645 numCycles++; 646 647 traceData = NULL; 648 649 Fault fault = No_Fault; 650 651#ifdef FULL_SYSTEM 652 if (AlphaISA::check_interrupts && 653 xc->cpu->check_interrupts() && 654 !PC_PAL(xc->regs.pc) && 655 status() != IcacheMissComplete) { 656 int ipl = 0; 657 int summary = 0; 658 AlphaISA::check_interrupts = 0; 659 IntReg *ipr = xc->regs.ipr; 660 661 if (xc->regs.ipr[TheISA::IPR_SIRR]) { 662 for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; 663 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { 664 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { 665 // See table 4-19 of 21164 hardware reference 666 ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; 667 summary |= (ULL(1) << i); 668 } 669 } 670 } 671 672 uint64_t interrupts = xc->cpu->intr_status(); 673 for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; 674 i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { 675 if (interrupts & (ULL(1) << i)) { 676 // See table 4-19 of 21164 hardware reference 677 ipl = i; 678 summary |= (ULL(1) << i); 679 } 680 } 681 682 if (ipr[TheISA::IPR_ASTRR]) 683 panic("asynchronous traps not implemented\n"); 684 685 if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { 686 ipr[TheISA::IPR_ISR] = summary; 687 ipr[TheISA::IPR_INTID] = ipl; 688 xc->ev5_trap(Interrupt_Fault); 689 690 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 691 ipr[TheISA::IPR_IPLR], ipl, summary); 692 } 693 } 694#endif 695 696 // maintain $r0 semantics 697 xc->regs.intRegFile[ZeroReg] = 0; 698#ifdef TARGET_ALPHA 699 xc->regs.floatRegFile.d[ZeroReg] = 0.0; 700#endif // TARGET_ALPHA 701 702 if (status() == IcacheMissComplete) { 703 // We've already fetched an instruction and were stalled on an 704 // I-cache miss. No need to fetch it again. 705 706 // Set status to running; tick event will get rescheduled if 707 // necessary at end of tick() function. 708 _status = Running; 709 } 710 else { 711 // Try to fetch an instruction 712 713 // set up memory request for instruction fetch 714#ifdef FULL_SYSTEM 715#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 716#else 717#define IFETCH_FLAGS(pc) 0 718#endif 719 720 memReq->cmd = Read; 721 memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 722 IFETCH_FLAGS(xc->regs.pc)); 723 724 fault = xc->translateInstReq(memReq); 725 726 if (fault == No_Fault) 727 fault = xc->mem->read(memReq, inst); 728 729 if (icacheInterface && fault == No_Fault) { 730 memReq->completionEvent = NULL; 731 732 memReq->time = curTick; 733 MemAccessResult result = icacheInterface->access(memReq); 734 735 // Ugly hack to get an event scheduled *only* if the access is 736 // a miss. We really should add first-class support for this 737 // at some point. 738 if (result != MA_HIT && icacheInterface->doEvents()) { 739 memReq->completionEvent = &cacheCompletionEvent; 740 lastIcacheStall = curTick; 741 unscheduleTickEvent(); 742 _status = IcacheMissStall; 743 return; 744 } 745 } 746 } 747 748 // If we've got a valid instruction (i.e., no fault on instruction 749 // fetch), then execute it. 750 if (fault == No_Fault) { 751 752 // keep an instruction count 753 numInst++; 754 numInsts++; 755 756 // check for instruction-count-based events 757 comInstEventQueue[0]->serviceEvents(numInst); 758 759 // decode the instruction 760 inst = htoa(inst); 761 StaticInstPtr<TheISA> si(inst); 762 763 traceData = Trace::getInstRecord(curTick, xc, this, si, 764 xc->regs.pc); 765 766#ifdef FULL_SYSTEM 767 xc->setInst(inst); 768#endif // FULL_SYSTEM 769 770 xc->func_exe_inst++; 771 772 fault = si->execute(this, traceData); 773 774#ifdef FULL_SYSTEM 775 if (xc->fnbin) 776 xc->execute(si.get()); 777#endif 778 779 if (si->isMemRef()) { 780 numMemRefs++; 781 } 782 783 if (si->isLoad()) { 784 ++numLoad; 785 comLoadEventQueue[0]->serviceEvents(numLoad); 786 } 787 788 if (traceData) 789 traceData->finalize(); 790 791 } // if (fault == No_Fault) 792 793 if (fault != No_Fault) { 794#ifdef FULL_SYSTEM 795 xc->ev5_trap(fault); 796#else // !FULL_SYSTEM 797 fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); 798#endif // FULL_SYSTEM 799 } 800 else { 801 // go to the next instruction 802 xc->regs.pc = xc->regs.npc; 803 xc->regs.npc += sizeof(MachInst); 804 } 805 806#ifdef FULL_SYSTEM 807 Addr oldpc; 808 do { 809 oldpc = xc->regs.pc; 810 system->pcEventQueue.service(xc); 811 } while (oldpc != xc->regs.pc); 812#endif 813 814 assert(status() == Running || 815 status() == Idle || 816 status() == DcacheMissStall); 817 818 if (status() == Running && !tickEvent.scheduled()) 819 tickEvent.schedule(curTick + 1); 820} 821 822 823//////////////////////////////////////////////////////////////////////// 824// 825// SimpleCPU Simulation Object 826// 827BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 828 829 Param<Counter> max_insts_any_thread; 830 Param<Counter> max_insts_all_threads; 831 Param<Counter> max_loads_any_thread; 832 Param<Counter> max_loads_all_threads; 833 834#ifdef FULL_SYSTEM 835 SimObjectParam<AlphaITB *> itb; 836 SimObjectParam<AlphaDTB *> dtb; 837 SimObjectParam<FunctionalMemory *> mem; 838 SimObjectParam<System *> system; 839 Param<int> mult; 840#else 841 SimObjectParam<Process *> workload; 842#endif // FULL_SYSTEM 843 844 SimObjectParam<BaseMem *> icache; 845 SimObjectParam<BaseMem *> dcache; 846 847 Param<bool> defer_registration; 848 Param<int> multiplier; 849 850END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 851 852BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 853 854 INIT_PARAM_DFLT(max_insts_any_thread, 855 "terminate when any thread reaches this inst count", 856 0), 857 INIT_PARAM_DFLT(max_insts_all_threads, 858 "terminate when all threads have reached this inst count", 859 0), 860 INIT_PARAM_DFLT(max_loads_any_thread, 861 "terminate when any thread reaches this load count", 862 0), 863 INIT_PARAM_DFLT(max_loads_all_threads, 864 "terminate when all threads have reached this load count", 865 0), 866 867#ifdef FULL_SYSTEM 868 INIT_PARAM(itb, "Instruction TLB"), 869 INIT_PARAM(dtb, "Data TLB"), 870 INIT_PARAM(mem, "memory"), 871 INIT_PARAM(system, "system object"), 872 INIT_PARAM_DFLT(mult, "system clock multiplier", 1), 873#else 874 INIT_PARAM(workload, "processes to run"), 875#endif // FULL_SYSTEM 876 877 INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL), 878 INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL), 879 INIT_PARAM_DFLT(defer_registration, "defer registration with system " 880 "(for sampling)", false), 881 882 INIT_PARAM_DFLT(multiplier, "clock multiplier", 1) 883 884END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 885 886 887CREATE_SIM_OBJECT(SimpleCPU) 888{ 889 SimpleCPU *cpu; 890#ifdef FULL_SYSTEM 891 if (mult != 1) 892 panic("processor clock multiplier must be 1\n"); 893 894 cpu = new SimpleCPU(getInstanceName(), system, 895 max_insts_any_thread, max_insts_all_threads, 896 max_loads_any_thread, max_loads_all_threads, 897 itb, dtb, mem, 898 (icache) ? icache->getInterface() : NULL, 899 (dcache) ? dcache->getInterface() : NULL, 900 defer_registration, 901 ticksPerSecond * mult); 902#else 903 904 cpu = new SimpleCPU(getInstanceName(), workload, 905 max_insts_any_thread, max_insts_all_threads, 906 max_loads_any_thread, max_loads_all_threads, 907 (icache) ? icache->getInterface() : NULL, 908 (dcache) ? dcache->getInterface() : NULL, 909 defer_registration); 910 911#endif // FULL_SYSTEM 912 913 cpu->setTickMultiplier(multiplier); 914 915 return cpu; 916} 917 918REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 919 920