base.cc revision 1098 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = multiplier;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue),
100      cpu(_cpu)
101{
102}
103
104void SimpleCPU::CacheCompletionEvent::process()
105{
106    cpu->processCacheCompletion();
107}
108
109const char *
110SimpleCPU::CacheCompletionEvent::description()
111{
112    return "SimpleCPU cache completion event";
113}
114
115#ifdef FULL_SYSTEM
116SimpleCPU::SimpleCPU(const string &_name,
117                     System *_system,
118                     Counter max_insts_any_thread,
119                     Counter max_insts_all_threads,
120                     Counter max_loads_any_thread,
121                     Counter max_loads_all_threads,
122                     AlphaITB *itb, AlphaDTB *dtb,
123                     FunctionalMemory *mem,
124                     MemInterface *icache_interface,
125                     MemInterface *dcache_interface,
126                     bool _def_reg, Tick freq)
127    : BaseCPU(_name, /* number_of_threads */ 1,
128              max_insts_any_thread, max_insts_all_threads,
129              max_loads_any_thread, max_loads_all_threads,
130              _system, freq),
131#else
132SimpleCPU::SimpleCPU(const string &_name, Process *_process,
133                     Counter max_insts_any_thread,
134                     Counter max_insts_all_threads,
135                     Counter max_loads_any_thread,
136                     Counter max_loads_all_threads,
137                     MemInterface *icache_interface,
138                     MemInterface *dcache_interface,
139                     bool _def_reg)
140    : BaseCPU(_name, /* number_of_threads */ 1,
141              max_insts_any_thread, max_insts_all_threads,
142              max_loads_any_thread, max_loads_all_threads),
143#endif
144      tickEvent(this), xc(NULL), defer_registration(_def_reg),
145      cacheCompletionEvent(this)
146{
147    _status = Idle;
148#ifdef FULL_SYSTEM
149    xc = new ExecContext(this, 0, system, itb, dtb, mem);
150
151    // initialize CPU, including PC
152    TheISA::initCPU(&xc->regs);
153#else
154    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
155#endif // !FULL_SYSTEM
156
157    icacheInterface = icache_interface;
158    dcacheInterface = dcache_interface;
159
160    memReq = new MemReq();
161    memReq->xc = xc;
162    memReq->asid = 0;
163    memReq->data = new uint8_t[64];
164
165    numInst = 0;
166    startNumInst = 0;
167    numLoad = 0;
168    startNumLoad = 0;
169    lastIcacheStall = 0;
170    lastDcacheStall = 0;
171
172    execContexts.push_back(xc);
173}
174
175SimpleCPU::~SimpleCPU()
176{
177}
178
179void SimpleCPU::init()
180{
181    if (!defer_registration) {
182        this->registerExecContexts();
183    }
184}
185
186void
187SimpleCPU::switchOut()
188{
189    _status = SwitchedOut;
190    if (tickEvent.scheduled())
191        tickEvent.squash();
192}
193
194
195void
196SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
197{
198    BaseCPU::takeOverFrom(oldCPU);
199
200    assert(!tickEvent.scheduled());
201
202    // if any of this CPU's ExecContexts are active, mark the CPU as
203    // running and schedule its tick event.
204    for (int i = 0; i < execContexts.size(); ++i) {
205        ExecContext *xc = execContexts[i];
206        if (xc->status() == ExecContext::Active && _status != Running) {
207            _status = Running;
208            tickEvent.schedule(curTick);
209        }
210    }
211
212    oldCPU->switchOut();
213}
214
215
216void
217SimpleCPU::activateContext(int thread_num, int delay)
218{
219    assert(thread_num == 0);
220    assert(xc);
221
222    assert(_status == Idle);
223    notIdleFraction++;
224    scheduleTickEvent(delay);
225    _status = Running;
226}
227
228
229void
230SimpleCPU::suspendContext(int thread_num)
231{
232    assert(thread_num == 0);
233    assert(xc);
234
235    assert(_status == Running);
236    notIdleFraction--;
237    unscheduleTickEvent();
238    _status = Idle;
239}
240
241
242void
243SimpleCPU::deallocateContext(int thread_num)
244{
245    // for now, these are equivalent
246    suspendContext(thread_num);
247}
248
249
250void
251SimpleCPU::haltContext(int thread_num)
252{
253    // for now, these are equivalent
254    suspendContext(thread_num);
255}
256
257
258void
259SimpleCPU::regStats()
260{
261    using namespace Stats;
262
263    BaseCPU::regStats();
264
265    numInsts
266        .name(name() + ".num_insts")
267        .desc("Number of instructions executed")
268        ;
269
270    numMemRefs
271        .name(name() + ".num_refs")
272        .desc("Number of memory references")
273        ;
274
275    notIdleFraction
276        .name(name() + ".not_idle_fraction")
277        .desc("Percentage of non-idle cycles")
278        ;
279
280    idleFraction
281        .name(name() + ".idle_fraction")
282        .desc("Percentage of idle cycles")
283        ;
284
285    icacheStallCycles
286        .name(name() + ".icache_stall_cycles")
287        .desc("ICache total stall cycles")
288        .prereq(icacheStallCycles)
289        ;
290
291    dcacheStallCycles
292        .name(name() + ".dcache_stall_cycles")
293        .desc("DCache total stall cycles")
294        .prereq(dcacheStallCycles)
295        ;
296
297    idleFraction = constant(1.0) - notIdleFraction;
298}
299
300void
301SimpleCPU::resetStats()
302{
303    startNumInst = numInst;
304    notIdleFraction = (_status != Idle);
305}
306
307void
308SimpleCPU::serialize(ostream &os)
309{
310    BaseCPU::serialize(os);
311    SERIALIZE_ENUM(_status);
312    SERIALIZE_SCALAR(inst);
313    nameOut(os, csprintf("%s.xc", name()));
314    xc->serialize(os);
315    nameOut(os, csprintf("%s.tickEvent", name()));
316    tickEvent.serialize(os);
317    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
318    cacheCompletionEvent.serialize(os);
319}
320
321void
322SimpleCPU::unserialize(Checkpoint *cp, const string &section)
323{
324    BaseCPU::unserialize(cp, section);
325    UNSERIALIZE_ENUM(_status);
326    UNSERIALIZE_SCALAR(inst);
327    xc->unserialize(cp, csprintf("%s.xc", section));
328    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
329    cacheCompletionEvent
330        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
331}
332
333void
334change_thread_state(int thread_number, int activate, int priority)
335{
336}
337
338Fault
339SimpleCPU::copySrcTranslate(Addr src)
340{
341    static bool no_warn = true;
342    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
343    // Only support block sizes of 64 atm.
344    assert(blk_size == 64);
345    int offset = src & (blk_size - 1);
346
347    // Make sure block doesn't span page
348    if (no_warn && (src & (~8191)) != ((src + blk_size) & (~8191)) &&
349        (src >> 40) != 0xfffffc) {
350        warn("Copied block source spans pages %x.", src);
351        no_warn = false;
352    }
353
354
355    memReq->reset(src & ~(blk_size - 1), blk_size);
356
357    // translate to physical address
358    Fault fault = xc->translateDataReadReq(memReq);
359
360    assert(fault != Alignment_Fault);
361
362    if (fault == No_Fault) {
363        xc->copySrcAddr = src;
364        xc->copySrcPhysAddr = memReq->paddr + offset;
365    } else {
366        xc->copySrcAddr = 0;
367        xc->copySrcPhysAddr = 0;
368    }
369    return fault;
370}
371
372Fault
373SimpleCPU::copy(Addr dest)
374{
375    static bool no_warn = true;
376    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
377    // Only support block sizes of 64 atm.
378    assert(blk_size == 64);
379    uint8_t data[blk_size];
380    //assert(xc->copySrcAddr);
381    int offset = dest & (blk_size - 1);
382
383    // Make sure block doesn't span page
384    if (no_warn && (dest & (~8191)) != ((dest + blk_size) & (~8191)) &&
385        (dest >> 40) != 0xfffffc) {
386        no_warn = false;
387        warn("Copied block destination spans pages %x. ", dest);
388    }
389
390    memReq->reset(dest & ~(blk_size -1), blk_size);
391    // translate to physical address
392    Fault fault = xc->translateDataWriteReq(memReq);
393
394    assert(fault != Alignment_Fault);
395
396    if (fault == No_Fault) {
397        Addr dest_addr = memReq->paddr + offset;
398        // Need to read straight from memory since we have more than 8 bytes.
399        memReq->paddr = xc->copySrcPhysAddr;
400        xc->mem->read(memReq, data);
401        memReq->paddr = dest_addr;
402        xc->mem->write(memReq, data);
403        if (dcacheInterface) {
404            memReq->cmd = Copy;
405            memReq->completionEvent = NULL;
406            memReq->paddr = xc->copySrcPhysAddr;
407            memReq->dest = dest_addr;
408            memReq->size = 64;
409            memReq->time = curTick;
410            dcacheInterface->access(memReq);
411        }
412    }
413    return fault;
414}
415
416// precise architected memory state accessor macros
417template <class T>
418Fault
419SimpleCPU::read(Addr addr, T &data, unsigned flags)
420{
421    memReq->reset(addr, sizeof(T), flags);
422
423    // translate to physical address
424    Fault fault = xc->translateDataReadReq(memReq);
425
426    // do functional access
427    if (fault == No_Fault)
428        fault = xc->read(memReq, data);
429
430    if (traceData) {
431        traceData->setAddr(addr);
432        if (fault == No_Fault)
433            traceData->setData(data);
434    }
435
436    // if we have a cache, do cache access too
437    if (fault == No_Fault && dcacheInterface) {
438        memReq->cmd = Read;
439        memReq->completionEvent = NULL;
440        memReq->time = curTick;
441        MemAccessResult result = dcacheInterface->access(memReq);
442
443        // Ugly hack to get an event scheduled *only* if the access is
444        // a miss.  We really should add first-class support for this
445        // at some point.
446        if (result != MA_HIT && dcacheInterface->doEvents()) {
447            memReq->completionEvent = &cacheCompletionEvent;
448            lastDcacheStall = curTick;
449            unscheduleTickEvent();
450            _status = DcacheMissStall;
451        }
452    }
453
454    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
455        recordEvent("Uncached Read");
456
457    return fault;
458}
459
460#ifndef DOXYGEN_SHOULD_SKIP_THIS
461
462template
463Fault
464SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
465
466template
467Fault
468SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
469
470template
471Fault
472SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
473
474template
475Fault
476SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
477
478#endif //DOXYGEN_SHOULD_SKIP_THIS
479
480template<>
481Fault
482SimpleCPU::read(Addr addr, double &data, unsigned flags)
483{
484    return read(addr, *(uint64_t*)&data, flags);
485}
486
487template<>
488Fault
489SimpleCPU::read(Addr addr, float &data, unsigned flags)
490{
491    return read(addr, *(uint32_t*)&data, flags);
492}
493
494
495template<>
496Fault
497SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
498{
499    return read(addr, (uint32_t&)data, flags);
500}
501
502
503template <class T>
504Fault
505SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
506{
507    if (traceData) {
508        traceData->setAddr(addr);
509        traceData->setData(data);
510    }
511
512    memReq->reset(addr, sizeof(T), flags);
513
514    // translate to physical address
515    Fault fault = xc->translateDataWriteReq(memReq);
516
517    // do functional access
518    if (fault == No_Fault)
519        fault = xc->write(memReq, data);
520
521    if (fault == No_Fault && dcacheInterface) {
522        memReq->cmd = Write;
523        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
524        memReq->completionEvent = NULL;
525        memReq->time = curTick;
526        MemAccessResult result = dcacheInterface->access(memReq);
527
528        // Ugly hack to get an event scheduled *only* if the access is
529        // a miss.  We really should add first-class support for this
530        // at some point.
531        if (result != MA_HIT && dcacheInterface->doEvents()) {
532            memReq->completionEvent = &cacheCompletionEvent;
533            lastDcacheStall = curTick;
534            unscheduleTickEvent();
535            _status = DcacheMissStall;
536        }
537    }
538
539    if (res && (fault == No_Fault))
540        *res = memReq->result;
541
542    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
543        recordEvent("Uncached Write");
544
545    return fault;
546}
547
548
549#ifndef DOXYGEN_SHOULD_SKIP_THIS
550template
551Fault
552SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
553
554template
555Fault
556SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
557
558template
559Fault
560SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
561
562template
563Fault
564SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
565
566#endif //DOXYGEN_SHOULD_SKIP_THIS
567
568template<>
569Fault
570SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
571{
572    return write(*(uint64_t*)&data, addr, flags, res);
573}
574
575template<>
576Fault
577SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
578{
579    return write(*(uint32_t*)&data, addr, flags, res);
580}
581
582
583template<>
584Fault
585SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
586{
587    return write((uint32_t)data, addr, flags, res);
588}
589
590
591#ifdef FULL_SYSTEM
592Addr
593SimpleCPU::dbg_vtophys(Addr addr)
594{
595    return vtophys(xc, addr);
596}
597#endif // FULL_SYSTEM
598
599Tick save_cycle = 0;
600
601
602void
603SimpleCPU::processCacheCompletion()
604{
605    switch (status()) {
606      case IcacheMissStall:
607        icacheStallCycles += curTick - lastIcacheStall;
608        _status = IcacheMissComplete;
609        scheduleTickEvent(1);
610        break;
611      case DcacheMissStall:
612        dcacheStallCycles += curTick - lastDcacheStall;
613        _status = Running;
614        scheduleTickEvent(1);
615        break;
616      case SwitchedOut:
617        // If this CPU has been switched out due to sampling/warm-up,
618        // ignore any further status changes (e.g., due to cache
619        // misses outstanding at the time of the switch).
620        return;
621      default:
622        panic("SimpleCPU::processCacheCompletion: bad state");
623        break;
624    }
625}
626
627#ifdef FULL_SYSTEM
628void
629SimpleCPU::post_interrupt(int int_num, int index)
630{
631    BaseCPU::post_interrupt(int_num, index);
632
633    if (xc->status() == ExecContext::Suspended) {
634                DPRINTF(IPI,"Suspended Processor awoke\n");
635        xc->activate();
636    }
637}
638#endif // FULL_SYSTEM
639
640/* start simulation, program loaded, processor precise state initialized */
641void
642SimpleCPU::tick()
643{
644    numCycles++;
645
646    traceData = NULL;
647
648    Fault fault = No_Fault;
649
650#ifdef FULL_SYSTEM
651    if (AlphaISA::check_interrupts &&
652        xc->cpu->check_interrupts() &&
653        !PC_PAL(xc->regs.pc) &&
654        status() != IcacheMissComplete) {
655        int ipl = 0;
656        int summary = 0;
657        AlphaISA::check_interrupts = 0;
658        IntReg *ipr = xc->regs.ipr;
659
660        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
661            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
662                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
663                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
664                    // See table 4-19 of 21164 hardware reference
665                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
666                    summary |= (ULL(1) << i);
667                }
668            }
669        }
670
671        uint64_t interrupts = xc->cpu->intr_status();
672        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
673            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
674            if (interrupts & (ULL(1) << i)) {
675                // See table 4-19 of 21164 hardware reference
676                ipl = i;
677                summary |= (ULL(1) << i);
678            }
679        }
680
681        if (ipr[TheISA::IPR_ASTRR])
682            panic("asynchronous traps not implemented\n");
683
684        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
685            ipr[TheISA::IPR_ISR] = summary;
686            ipr[TheISA::IPR_INTID] = ipl;
687            xc->ev5_trap(Interrupt_Fault);
688
689            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
690                    ipr[TheISA::IPR_IPLR], ipl, summary);
691        }
692    }
693#endif
694
695    // maintain $r0 semantics
696    xc->regs.intRegFile[ZeroReg] = 0;
697#ifdef TARGET_ALPHA
698    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
699#endif // TARGET_ALPHA
700
701    if (status() == IcacheMissComplete) {
702        // We've already fetched an instruction and were stalled on an
703        // I-cache miss.  No need to fetch it again.
704
705        // Set status to running; tick event will get rescheduled if
706        // necessary at end of tick() function.
707        _status = Running;
708    }
709    else {
710        // Try to fetch an instruction
711
712        // set up memory request for instruction fetch
713#ifdef FULL_SYSTEM
714#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
715#else
716#define IFETCH_FLAGS(pc)	0
717#endif
718
719        memReq->cmd = Read;
720        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
721                     IFETCH_FLAGS(xc->regs.pc));
722
723        fault = xc->translateInstReq(memReq);
724
725        if (fault == No_Fault)
726            fault = xc->mem->read(memReq, inst);
727
728        if (icacheInterface && fault == No_Fault) {
729            memReq->completionEvent = NULL;
730
731            memReq->time = curTick;
732            MemAccessResult result = icacheInterface->access(memReq);
733
734            // Ugly hack to get an event scheduled *only* if the access is
735            // a miss.  We really should add first-class support for this
736            // at some point.
737            if (result != MA_HIT && icacheInterface->doEvents()) {
738                memReq->completionEvent = &cacheCompletionEvent;
739                lastIcacheStall = curTick;
740                unscheduleTickEvent();
741                _status = IcacheMissStall;
742                return;
743            }
744        }
745    }
746
747    // If we've got a valid instruction (i.e., no fault on instruction
748    // fetch), then execute it.
749    if (fault == No_Fault) {
750
751        // keep an instruction count
752        numInst++;
753        numInsts++;
754
755        // check for instruction-count-based events
756        comInstEventQueue[0]->serviceEvents(numInst);
757
758        // decode the instruction
759    inst = htoa(inst);
760        StaticInstPtr<TheISA> si(inst);
761
762        traceData = Trace::getInstRecord(curTick, xc, this, si,
763                                         xc->regs.pc);
764
765#ifdef FULL_SYSTEM
766        xc->setInst(inst);
767#endif // FULL_SYSTEM
768
769        xc->func_exe_inst++;
770
771        fault = si->execute(this, traceData);
772
773#ifdef FULL_SYSTEM
774        if (xc->fnbin)
775            xc->execute(si.get());
776#endif
777
778        if (si->isMemRef()) {
779            numMemRefs++;
780        }
781
782        if (si->isLoad()) {
783            ++numLoad;
784            comLoadEventQueue[0]->serviceEvents(numLoad);
785        }
786
787        if (traceData)
788            traceData->finalize();
789
790    }	// if (fault == No_Fault)
791
792    if (fault != No_Fault) {
793#ifdef FULL_SYSTEM
794        xc->ev5_trap(fault);
795#else // !FULL_SYSTEM
796        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
797#endif // FULL_SYSTEM
798    }
799    else {
800        // go to the next instruction
801        xc->regs.pc = xc->regs.npc;
802        xc->regs.npc += sizeof(MachInst);
803    }
804
805#ifdef FULL_SYSTEM
806    Addr oldpc;
807    do {
808        oldpc = xc->regs.pc;
809        system->pcEventQueue.service(xc);
810    } while (oldpc != xc->regs.pc);
811#endif
812
813    assert(status() == Running ||
814           status() == Idle ||
815           status() == DcacheMissStall);
816
817    if (status() == Running && !tickEvent.scheduled())
818        tickEvent.schedule(curTick + 1);
819}
820
821
822////////////////////////////////////////////////////////////////////////
823//
824//  SimpleCPU Simulation Object
825//
826BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
827
828    Param<Counter> max_insts_any_thread;
829    Param<Counter> max_insts_all_threads;
830    Param<Counter> max_loads_any_thread;
831    Param<Counter> max_loads_all_threads;
832
833#ifdef FULL_SYSTEM
834    SimObjectParam<AlphaITB *> itb;
835    SimObjectParam<AlphaDTB *> dtb;
836    SimObjectParam<FunctionalMemory *> mem;
837    SimObjectParam<System *> system;
838    Param<int> mult;
839#else
840    SimObjectParam<Process *> workload;
841#endif // FULL_SYSTEM
842
843    SimObjectParam<BaseMem *> icache;
844    SimObjectParam<BaseMem *> dcache;
845
846    Param<bool> defer_registration;
847    Param<int> multiplier;
848
849END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
850
851BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
852
853    INIT_PARAM_DFLT(max_insts_any_thread,
854                    "terminate when any thread reaches this inst count",
855                    0),
856    INIT_PARAM_DFLT(max_insts_all_threads,
857                    "terminate when all threads have reached this inst count",
858                    0),
859    INIT_PARAM_DFLT(max_loads_any_thread,
860                    "terminate when any thread reaches this load count",
861                    0),
862    INIT_PARAM_DFLT(max_loads_all_threads,
863                    "terminate when all threads have reached this load count",
864                    0),
865
866#ifdef FULL_SYSTEM
867    INIT_PARAM(itb, "Instruction TLB"),
868    INIT_PARAM(dtb, "Data TLB"),
869    INIT_PARAM(mem, "memory"),
870    INIT_PARAM(system, "system object"),
871    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
872#else
873    INIT_PARAM(workload, "processes to run"),
874#endif // FULL_SYSTEM
875
876    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
877    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
878    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
879                    "(for sampling)", false),
880
881    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
882
883END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
884
885
886CREATE_SIM_OBJECT(SimpleCPU)
887{
888    SimpleCPU *cpu;
889#ifdef FULL_SYSTEM
890    if (mult != 1)
891        panic("processor clock multiplier must be 1\n");
892
893    cpu = new SimpleCPU(getInstanceName(), system,
894                        max_insts_any_thread, max_insts_all_threads,
895                        max_loads_any_thread, max_loads_all_threads,
896                        itb, dtb, mem,
897                        (icache) ? icache->getInterface() : NULL,
898                        (dcache) ? dcache->getInterface() : NULL,
899                        defer_registration,
900                        ticksPerSecond * mult);
901#else
902
903    cpu = new SimpleCPU(getInstanceName(), workload,
904                        max_insts_any_thread, max_insts_all_threads,
905                        max_loads_any_thread, max_loads_all_threads,
906                        (icache) ? icache->getInterface() : NULL,
907                        (dcache) ? dcache->getInterface() : NULL,
908                        defer_registration);
909
910#endif // FULL_SYSTEM
911
912    cpu->setTickMultiplier(multiplier);
913
914    return cpu;
915}
916
917REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
918
919