base.cc revision 10905
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47338SAli.Saidi@ARM.com * All rights reserved 57338SAli.Saidi@ARM.com * 67338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147338SAli.Saidi@ARM.com * 151762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422SN/A */ 432SN/A 448779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 458779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 468779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 472439SN/A#include "arch/utility.hh" 488779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 498229Snate@binkert.org#include "base/loader/symtab.hh" 506216Snate@binkert.org#include "base/cp_annotate.hh" 51146SN/A#include "base/cprintf.hh" 52146SN/A#include "base/inifile.hh" 53146SN/A#include "base/misc.hh" 54146SN/A#include "base/pollevent.hh" 55146SN/A#include "base/trace.hh" 566216Snate@binkert.org#include "base/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 588229Snate@binkert.org#include "cpu/simple/base.hh" 591717SN/A#include "cpu/base.hh" 608887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 618887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 62146SN/A#include "cpu/exetrace.hh" 6310061Sandreas@sandberg.pp.se#include "cpu/pred/bpred_unit.hh" 641977SN/A#include "cpu/profile.hh" 652683Sktlim@umich.edu#include "cpu/simple_thread.hh" 661717SN/A#include "cpu/smt.hh" 67146SN/A#include "cpu/static_inst.hh" 682683Sktlim@umich.edu#include "cpu/thread_context.hh" 698232Snate@binkert.org#include "debug/Decode.hh" 708232Snate@binkert.org#include "debug/Fetch.hh" 718232Snate@binkert.org#include "debug/Quiesce.hh" 728779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 733348Sbinkertn@umich.edu#include "mem/packet.hh" 746105Ssteve.reinhardt@amd.com#include "mem/request.hh" 756216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 762036SN/A#include "sim/byteswap.hh" 77146SN/A#include "sim/debug.hh" 788817Sgblack@eecs.umich.edu#include "sim/faults.hh" 798793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 8056SN/A#include "sim/sim_events.hh" 8156SN/A#include "sim/sim_object.hh" 82695SN/A#include "sim/stats.hh" 832901Ssaidi@eecs.umich.edu#include "sim/system.hh" 842SN/A 852SN/Ausing namespace std; 862449SN/Ausing namespace TheISA; 871355SN/A 885529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 8910061Sandreas@sandberg.pp.se : BaseCPU(p), 9010061Sandreas@sandberg.pp.se branchPred(p->branchPred), 9110537Sandreas.hansson@arm.com traceData(NULL), thread(NULL), _status(Idle), interval_stats(false), 9210537Sandreas.hansson@arm.com inst() 93224SN/A{ 948793Sgblack@eecs.umich.edu if (FullSystem) 959384SAndreas.Sandberg@arm.com thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, 969384SAndreas.Sandberg@arm.com p->isa[0]); 978793Sgblack@eecs.umich.edu else 988820Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->system, 999384SAndreas.Sandberg@arm.com p->workload[0], p->itb, p->dtb, p->isa[0]); 1002SN/A 1016029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 1022672Sktlim@umich.edu 1032683Sktlim@umich.edu tc = thread->getTC(); 1042SN/A 1058733Sgeoffrey.blake@arm.com if (p->checker) { 1068733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1078733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1088733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1098733Sgeoffrey.blake@arm.com // Manipulate thread context 1108733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1118733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1128733Sgeoffrey.blake@arm.com } else { 1138733Sgeoffrey.blake@arm.com checker = NULL; 1148733Sgeoffrey.blake@arm.com } 1158733Sgeoffrey.blake@arm.com 1162SN/A numInst = 0; 117334SN/A startNumInst = 0; 1188834Satgutier@umich.edu numOp = 0; 1198834Satgutier@umich.edu startNumOp = 0; 120140SN/A numLoad = 0; 121334SN/A startNumLoad = 0; 1222SN/A lastIcacheStall = 0; 1232SN/A lastDcacheStall = 0; 1242SN/A 1252680Sktlim@umich.edu threadContexts.push_back(tc); 1264377Sgblack@eecs.umich.edu 1275169Ssaidi@eecs.umich.edu 1284377Sgblack@eecs.umich.edu fetchOffset = 0; 1294377Sgblack@eecs.umich.edu stayAtPC = false; 1302SN/A} 1312SN/A 1322623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1332SN/A{ 1342SN/A} 1352SN/A 136180SN/Avoid 1378737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 138393SN/A{ 139393SN/A // for now, these are equivalent 140393SN/A suspendContext(thread_num); 141393SN/A} 142384SN/A 143189SN/A 144189SN/Avoid 1452623SN/ABaseSimpleCPU::regStats() 1462SN/A{ 147729SN/A using namespace Stats; 148334SN/A 1492SN/A BaseCPU::regStats(); 1502SN/A 1512SN/A numInsts 1528834Satgutier@umich.edu .name(name() + ".committedInsts") 1538834Satgutier@umich.edu .desc("Number of instructions committed") 1548834Satgutier@umich.edu ; 1558834Satgutier@umich.edu 1568834Satgutier@umich.edu numOps 1578834Satgutier@umich.edu .name(name() + ".committedOps") 1588834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1592SN/A ; 1602SN/A 1617897Shestness@cs.utexas.edu numIntAluAccesses 1627897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1637897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1647897Shestness@cs.utexas.edu ; 1657897Shestness@cs.utexas.edu 1667897Shestness@cs.utexas.edu numFpAluAccesses 1677897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1687897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1697897Shestness@cs.utexas.edu ; 1707897Shestness@cs.utexas.edu 1717897Shestness@cs.utexas.edu numCallsReturns 1727897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1737897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1747897Shestness@cs.utexas.edu ; 1757897Shestness@cs.utexas.edu 1767897Shestness@cs.utexas.edu numCondCtrlInsts 1777897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1787897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1797897Shestness@cs.utexas.edu ; 1807897Shestness@cs.utexas.edu 1817897Shestness@cs.utexas.edu numIntInsts 1827897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1837897Shestness@cs.utexas.edu .desc("number of integer instructions") 1847897Shestness@cs.utexas.edu ; 1857897Shestness@cs.utexas.edu 1867897Shestness@cs.utexas.edu numFpInsts 1877897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1887897Shestness@cs.utexas.edu .desc("number of float instructions") 1897897Shestness@cs.utexas.edu ; 1907897Shestness@cs.utexas.edu 1917897Shestness@cs.utexas.edu numIntRegReads 1927897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1937897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1947897Shestness@cs.utexas.edu ; 1957897Shestness@cs.utexas.edu 1967897Shestness@cs.utexas.edu numIntRegWrites 1977897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 1987897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 1997897Shestness@cs.utexas.edu ; 2007897Shestness@cs.utexas.edu 2017897Shestness@cs.utexas.edu numFpRegReads 2027897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2037897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2047897Shestness@cs.utexas.edu ; 2057897Shestness@cs.utexas.edu 2067897Shestness@cs.utexas.edu numFpRegWrites 2077897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2087897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2097897Shestness@cs.utexas.edu ; 2107897Shestness@cs.utexas.edu 2119920Syasuko.eckert@amd.com numCCRegReads 2129920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_reads") 2139920Syasuko.eckert@amd.com .desc("number of times the CC registers were read") 2149920Syasuko.eckert@amd.com .flags(nozero) 2159920Syasuko.eckert@amd.com ; 2169920Syasuko.eckert@amd.com 2179920Syasuko.eckert@amd.com numCCRegWrites 2189920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_writes") 2199920Syasuko.eckert@amd.com .desc("number of times the CC registers were written") 2209920Syasuko.eckert@amd.com .flags(nozero) 2219920Syasuko.eckert@amd.com ; 2229920Syasuko.eckert@amd.com 2232SN/A numMemRefs 2247897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2257897Shestness@cs.utexas.edu .desc("number of memory refs") 2267897Shestness@cs.utexas.edu ; 2277897Shestness@cs.utexas.edu 2287897Shestness@cs.utexas.edu numStoreInsts 2297897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2307897Shestness@cs.utexas.edu .desc("Number of store instructions") 2317897Shestness@cs.utexas.edu ; 2327897Shestness@cs.utexas.edu 2337897Shestness@cs.utexas.edu numLoadInsts 2347897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2357897Shestness@cs.utexas.edu .desc("Number of load instructions") 2362SN/A ; 2372SN/A 2381001SN/A notIdleFraction 2391001SN/A .name(name() + ".not_idle_fraction") 2401001SN/A .desc("Percentage of non-idle cycles") 2411001SN/A ; 2421001SN/A 2432SN/A idleFraction 2442SN/A .name(name() + ".idle_fraction") 2452SN/A .desc("Percentage of idle cycles") 2462SN/A ; 2472SN/A 2487897Shestness@cs.utexas.edu numBusyCycles 2497897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2507897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2517897Shestness@cs.utexas.edu ; 2527897Shestness@cs.utexas.edu 2537897Shestness@cs.utexas.edu numIdleCycles 2547897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2557897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2567897Shestness@cs.utexas.edu ; 2577897Shestness@cs.utexas.edu 2582SN/A icacheStallCycles 2592SN/A .name(name() + ".icache_stall_cycles") 2602SN/A .desc("ICache total stall cycles") 2612SN/A .prereq(icacheStallCycles) 2622SN/A ; 2632SN/A 2642SN/A dcacheStallCycles 2652SN/A .name(name() + ".dcache_stall_cycles") 2662SN/A .desc("DCache total stall cycles") 2672SN/A .prereq(dcacheStallCycles) 2682SN/A ; 2692SN/A 27010193SCurtis.Dunham@arm.com statExecutedInstType 27110193SCurtis.Dunham@arm.com .init(Enums::Num_OpClass) 27210193SCurtis.Dunham@arm.com .name(name() + ".op_class") 27310193SCurtis.Dunham@arm.com .desc("Class of executed instruction") 27410193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 27510193SCurtis.Dunham@arm.com ; 27610193SCurtis.Dunham@arm.com for (unsigned i = 0; i < Num_OpClasses; ++i) { 27710193SCurtis.Dunham@arm.com statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 27810193SCurtis.Dunham@arm.com } 27910193SCurtis.Dunham@arm.com 280385SN/A idleFraction = constant(1.0) - notIdleFraction; 2817897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2827897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 28310061Sandreas@sandberg.pp.se 28410061Sandreas@sandberg.pp.se numBranches 28510061Sandreas@sandberg.pp.se .name(name() + ".Branches") 28610061Sandreas@sandberg.pp.se .desc("Number of branches fetched") 28710061Sandreas@sandberg.pp.se .prereq(numBranches); 28810061Sandreas@sandberg.pp.se 28910061Sandreas@sandberg.pp.se numPredictedBranches 29010061Sandreas@sandberg.pp.se .name(name() + ".predictedBranches") 29110061Sandreas@sandberg.pp.se .desc("Number of branches predicted as taken") 29210061Sandreas@sandberg.pp.se .prereq(numPredictedBranches); 29310061Sandreas@sandberg.pp.se 29410061Sandreas@sandberg.pp.se numBranchMispred 29510061Sandreas@sandberg.pp.se .name(name() + ".BranchMispred") 29610061Sandreas@sandberg.pp.se .desc("Number of branch mispredictions") 29710061Sandreas@sandberg.pp.se .prereq(numBranchMispred); 2982SN/A} 2992SN/A 3002SN/Avoid 3012623SN/ABaseSimpleCPU::resetStats() 302334SN/A{ 3032361SN/A// startNumInst = numInst; 3045496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 305334SN/A} 306334SN/A 307334SN/Avoid 30810905Sandreas.sandberg@arm.comBaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 3092SN/A{ 3109448SAndreas.Sandberg@ARM.com assert(_status == Idle || _status == Running); 3119448SAndreas.Sandberg@ARM.com assert(tid == 0); 3129448SAndreas.Sandberg@ARM.com 31310905Sandreas.sandberg@arm.com thread->serialize(cp); 3142SN/A} 3152SN/A 3162SN/Avoid 31710905Sandreas.sandberg@arm.comBaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 3182SN/A{ 3199448SAndreas.Sandberg@ARM.com if (tid != 0) 3209448SAndreas.Sandberg@ARM.com fatal("Trying to load more than one thread into a SimpleCPU\n"); 32110905Sandreas.sandberg@arm.com thread->unserialize(cp); 3222SN/A} 3232SN/A 3242SN/Avoid 3256221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3262SN/A{ 3272SN/A} 3282SN/A 3292SN/AAddr 3302623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3312SN/A{ 3322680Sktlim@umich.edu return vtophys(tc, addr); 3332SN/A} 3342SN/A 3352SN/Avoid 3365807Snate@binkert.orgBaseSimpleCPU::wakeup() 3372SN/A{ 33810529Smorr@cs.wisc.edu getAddrMonitor()->gotWakeup = true; 33910529Smorr@cs.wisc.edu 3405807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3415807Snate@binkert.org return; 3422SN/A 3435807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3445807Snate@binkert.org thread->activate(); 3452SN/A} 3462SN/A 3472SN/Avoid 3482623SN/ABaseSimpleCPU::checkForInterrupts() 3492SN/A{ 3505704Snate@binkert.org if (checkInterrupts(tc)) { 3515647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3522SN/A 3533520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3547338SAli.Saidi@ARM.com fetchOffset = 0; 3555647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3563520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3579023Sgblack@eecs.umich.edu thread->decoder.reset(); 3582SN/A } 3592SN/A } 3602623SN/A} 3612SN/A 3622623SN/A 3635894Sgblack@eecs.umich.eduvoid 3642662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3652623SN/A{ 3667720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3674495Sacolyte@umich.edu 3682623SN/A // set up memory request for instruction fetch 3697720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3702623SN/A 3717720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3728832SAli.Saidi@ARM.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3738832SAli.Saidi@ARM.com instAddr); 3742623SN/A} 3752623SN/A 3762623SN/A 3772623SN/Avoid 3782623SN/ABaseSimpleCPU::preExecute() 3792623SN/A{ 3802SN/A // maintain $r0 semantics 3812683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3822427SN/A#if THE_ISA == ALPHA_ISA 3832683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3842427SN/A#endif // ALPHA_ISA 3852SN/A 3862623SN/A // check for instruction-count-based events 3872623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3887897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3892SN/A 3902623SN/A // decode the instruction 3912623SN/A inst = gtoh(inst); 3924377Sgblack@eecs.umich.edu 3937720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3944377Sgblack@eecs.umich.edu 3957720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3965665Sgblack@eecs.umich.edu stayAtPC = false; 3977720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3987720Sgblack@eecs.umich.edu curMacroStaticInst); 3995665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 4005665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 4014181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 4024181Sgblack@eecs.umich.edu 4039023Sgblack@eecs.umich.edu TheISA::Decoder *decoder = &(thread->decoder); 4049023Sgblack@eecs.umich.edu 4054181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 4064182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 4077720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 4089023Sgblack@eecs.umich.edu //if(decoder->needMoreBytes()) 4099023Sgblack@eecs.umich.edu decoder->moreBytes(pcState, fetchPC, inst); 4104593Sgblack@eecs.umich.edu //else 4119023Sgblack@eecs.umich.edu // decoder->process(); 4124377Sgblack@eecs.umich.edu 4139023Sgblack@eecs.umich.edu //Decode an instruction if one is ready. Otherwise, we'll have to 4144377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4159023Sgblack@eecs.umich.edu instPtr = decoder->decode(pcState); 4169023Sgblack@eecs.umich.edu if (instPtr) { 4174377Sgblack@eecs.umich.edu stayAtPC = false; 4187720Sgblack@eecs.umich.edu thread->pcState(pcState); 4194377Sgblack@eecs.umich.edu } else { 4204377Sgblack@eecs.umich.edu stayAtPC = true; 4214377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4224377Sgblack@eecs.umich.edu } 4234181Sgblack@eecs.umich.edu 4244181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4254181Sgblack@eecs.umich.edu //out micro ops 4264539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4273276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4287720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4293280Sgblack@eecs.umich.edu } else { 4303280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4313276Sgblack@eecs.umich.edu } 4323276Sgblack@eecs.umich.edu } else { 4333276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4347720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4353276Sgblack@eecs.umich.edu } 4363276Sgblack@eecs.umich.edu 4374181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4388955Sgblack@eecs.umich.edu if (curStaticInst) { 4394522Ssaidi@eecs.umich.edu#if TRACING_ON 4407823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4417720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4422470SN/A 4438955Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 4444181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4454522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4464181Sgblack@eecs.umich.edu } 44710061Sandreas@sandberg.pp.se 44810061Sandreas@sandberg.pp.se if (branchPred && curStaticInst && curStaticInst->isControl()) { 44910061Sandreas@sandberg.pp.se // Use a fake sequence number since we only have one 45010061Sandreas@sandberg.pp.se // instruction in flight at the same time. 45110061Sandreas@sandberg.pp.se const InstSeqNum cur_sn(0); 45210061Sandreas@sandberg.pp.se const ThreadID tid(0); 45310061Sandreas@sandberg.pp.se pred_pc = thread->pcState(); 45410061Sandreas@sandberg.pp.se const bool predict_taken( 45510061Sandreas@sandberg.pp.se branchPred->predict(curStaticInst, cur_sn, pred_pc, tid)); 45610061Sandreas@sandberg.pp.se 45710061Sandreas@sandberg.pp.se if (predict_taken) 45810061Sandreas@sandberg.pp.se ++numPredictedBranches; 45910061Sandreas@sandberg.pp.se } 4602623SN/A} 4612623SN/A 4622623SN/Avoid 4632623SN/ABaseSimpleCPU::postExecute() 4642623SN/A{ 4657720Sgblack@eecs.umich.edu assert(curStaticInst); 4667720Sgblack@eecs.umich.edu 4677720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4687720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4698780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4703577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4717720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4725086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4732623SN/A if (node) 4742683Sktlim@umich.edu thread->profileNode = node; 4752623SN/A } 4762SN/A 4772623SN/A if (curStaticInst->isMemRef()) { 4782623SN/A numMemRefs++; 4792SN/A } 4802SN/A 4812623SN/A if (curStaticInst->isLoad()) { 4822623SN/A ++numLoad; 4832623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4842623SN/A } 4852SN/A 4865953Ssaidi@eecs.umich.edu if (CPA::available()) { 4877720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4885953Ssaidi@eecs.umich.edu } 4895953Ssaidi@eecs.umich.edu 49010061Sandreas@sandberg.pp.se if (curStaticInst->isControl()) { 49110061Sandreas@sandberg.pp.se ++numBranches; 49210061Sandreas@sandberg.pp.se } 49310061Sandreas@sandberg.pp.se 4947897Shestness@cs.utexas.edu /* Power model statistics */ 4957897Shestness@cs.utexas.edu //integer alu accesses 4967897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4977897Shestness@cs.utexas.edu numIntAluAccesses++; 4987897Shestness@cs.utexas.edu numIntInsts++; 4997897Shestness@cs.utexas.edu } 5007897Shestness@cs.utexas.edu 5017897Shestness@cs.utexas.edu //float alu accesses 5027897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 5037897Shestness@cs.utexas.edu numFpAluAccesses++; 5047897Shestness@cs.utexas.edu numFpInsts++; 5057897Shestness@cs.utexas.edu } 5067897Shestness@cs.utexas.edu 5077897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 5087897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 5097897Shestness@cs.utexas.edu numCallsReturns++; 5107897Shestness@cs.utexas.edu } 5117897Shestness@cs.utexas.edu 5127897Shestness@cs.utexas.edu //the number of branch predictions that will be made 5137897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 5147897Shestness@cs.utexas.edu numCondCtrlInsts++; 5157897Shestness@cs.utexas.edu } 5167897Shestness@cs.utexas.edu 5177897Shestness@cs.utexas.edu //result bus acceses 5187897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 5197897Shestness@cs.utexas.edu numLoadInsts++; 5207897Shestness@cs.utexas.edu } 5217897Shestness@cs.utexas.edu 5227897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 5237897Shestness@cs.utexas.edu numStoreInsts++; 5247897Shestness@cs.utexas.edu } 5257897Shestness@cs.utexas.edu /* End power model statistics */ 5267897Shestness@cs.utexas.edu 52710193SCurtis.Dunham@arm.com statExecutedInstType[curStaticInst->opClass()]++; 52810193SCurtis.Dunham@arm.com 5298780Sgblack@eecs.umich.edu if (FullSystem) 5308780Sgblack@eecs.umich.edu traceFunctions(instAddr); 5312644Sstever@eecs.umich.edu 5322644Sstever@eecs.umich.edu if (traceData) { 5334046Sbinkertn@umich.edu traceData->dump(); 5344046Sbinkertn@umich.edu delete traceData; 5354046Sbinkertn@umich.edu traceData = NULL; 5362644Sstever@eecs.umich.edu } 53710464SAndreas.Sandberg@ARM.com 53810464SAndreas.Sandberg@ARM.com // Call CPU instruction commit probes 53910464SAndreas.Sandberg@ARM.com probeInstCommit(curStaticInst); 5402623SN/A} 5412SN/A 5422623SN/Avoid 54310379Sandreas.hansson@arm.comBaseSimpleCPU::advancePC(const Fault &fault) 5442623SN/A{ 54510061Sandreas@sandberg.pp.se const bool branching(thread->pcState().branching()); 54610061Sandreas@sandberg.pp.se 5474377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5484377Sgblack@eecs.umich.edu fetchOffset = 0; 5492090SN/A if (fault != NoFault) { 5503905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5517678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5529023Sgblack@eecs.umich.edu thread->decoder.reset(); 5534377Sgblack@eecs.umich.edu } else { 5547720Sgblack@eecs.umich.edu if (curStaticInst) { 5557720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5567720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5577720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5587720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5597720Sgblack@eecs.umich.edu thread->pcState(pcState); 5603276Sgblack@eecs.umich.edu } 5612SN/A } 56210061Sandreas@sandberg.pp.se 56310061Sandreas@sandberg.pp.se if (branchPred && curStaticInst && curStaticInst->isControl()) { 56410061Sandreas@sandberg.pp.se // Use a fake sequence number since we only have one 56510061Sandreas@sandberg.pp.se // instruction in flight at the same time. 56610061Sandreas@sandberg.pp.se const InstSeqNum cur_sn(0); 56710061Sandreas@sandberg.pp.se const ThreadID tid(0); 56810061Sandreas@sandberg.pp.se 56910061Sandreas@sandberg.pp.se if (pred_pc == thread->pcState()) { 57010061Sandreas@sandberg.pp.se // Correctly predicted branch 57110061Sandreas@sandberg.pp.se branchPred->update(cur_sn, tid); 57210061Sandreas@sandberg.pp.se } else { 57310061Sandreas@sandberg.pp.se // Mis-predicted branch 57410061Sandreas@sandberg.pp.se branchPred->squash(cur_sn, pcState(), 57510061Sandreas@sandberg.pp.se branching, tid); 57610061Sandreas@sandberg.pp.se ++numBranchMispred; 57710061Sandreas@sandberg.pp.se } 57810061Sandreas@sandberg.pp.se } 5792SN/A} 5802SN/A 5819461Snilay@cs.wisc.eduvoid 5829461Snilay@cs.wisc.eduBaseSimpleCPU::startup() 5839461Snilay@cs.wisc.edu{ 5849461Snilay@cs.wisc.edu BaseCPU::startup(); 5859461Snilay@cs.wisc.edu thread->startup(); 5869461Snilay@cs.wisc.edu} 587