base.cc revision 1089 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = multiplier;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue),
100      cpu(_cpu)
101{
102}
103
104void SimpleCPU::CacheCompletionEvent::process()
105{
106    cpu->processCacheCompletion();
107}
108
109const char *
110SimpleCPU::CacheCompletionEvent::description()
111{
112    return "SimpleCPU cache completion event";
113}
114
115#ifdef FULL_SYSTEM
116SimpleCPU::SimpleCPU(const string &_name,
117                     System *_system,
118                     Counter max_insts_any_thread,
119                     Counter max_insts_all_threads,
120                     Counter max_loads_any_thread,
121                     Counter max_loads_all_threads,
122                     AlphaITB *itb, AlphaDTB *dtb,
123                     FunctionalMemory *mem,
124                     MemInterface *icache_interface,
125                     MemInterface *dcache_interface,
126                     bool _def_reg, Tick freq)
127    : BaseCPU(_name, /* number_of_threads */ 1,
128              max_insts_any_thread, max_insts_all_threads,
129              max_loads_any_thread, max_loads_all_threads,
130              _system, freq),
131#else
132SimpleCPU::SimpleCPU(const string &_name, Process *_process,
133                     Counter max_insts_any_thread,
134                     Counter max_insts_all_threads,
135                     Counter max_loads_any_thread,
136                     Counter max_loads_all_threads,
137                     MemInterface *icache_interface,
138                     MemInterface *dcache_interface,
139                     bool _def_reg)
140    : BaseCPU(_name, /* number_of_threads */ 1,
141              max_insts_any_thread, max_insts_all_threads,
142              max_loads_any_thread, max_loads_all_threads),
143#endif
144      tickEvent(this), xc(NULL), defer_registration(_def_reg),
145      cacheCompletionEvent(this)
146{
147    _status = Idle;
148#ifdef FULL_SYSTEM
149    xc = new ExecContext(this, 0, system, itb, dtb, mem);
150
151    // initialize CPU, including PC
152    TheISA::initCPU(&xc->regs);
153#else
154    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
155#endif // !FULL_SYSTEM
156
157    icacheInterface = icache_interface;
158    dcacheInterface = dcache_interface;
159
160    memReq = new MemReq();
161    memReq->xc = xc;
162    memReq->asid = 0;
163    memReq->data = new uint8_t[64];
164
165    numInst = 0;
166    startNumInst = 0;
167    numLoad = 0;
168    startNumLoad = 0;
169    lastIcacheStall = 0;
170    lastDcacheStall = 0;
171
172    execContexts.push_back(xc);
173}
174
175SimpleCPU::~SimpleCPU()
176{
177}
178
179void SimpleCPU::init()
180{
181    if (!defer_registration) {
182        this->registerExecContexts();
183    }
184}
185
186void
187SimpleCPU::switchOut()
188{
189    _status = SwitchedOut;
190    if (tickEvent.scheduled())
191        tickEvent.squash();
192}
193
194
195void
196SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
197{
198    BaseCPU::takeOverFrom(oldCPU);
199
200    assert(!tickEvent.scheduled());
201
202    // if any of this CPU's ExecContexts are active, mark the CPU as
203    // running and schedule its tick event.
204    for (int i = 0; i < execContexts.size(); ++i) {
205        ExecContext *xc = execContexts[i];
206        if (xc->status() == ExecContext::Active && _status != Running) {
207            _status = Running;
208            tickEvent.schedule(curTick);
209        }
210    }
211
212    oldCPU->switchOut();
213}
214
215
216void
217SimpleCPU::activateContext(int thread_num, int delay)
218{
219    assert(thread_num == 0);
220    assert(xc);
221
222    assert(_status == Idle);
223    notIdleFraction++;
224    scheduleTickEvent(delay);
225    _status = Running;
226}
227
228
229void
230SimpleCPU::suspendContext(int thread_num)
231{
232    assert(thread_num == 0);
233    assert(xc);
234
235    assert(_status == Running);
236    notIdleFraction--;
237    unscheduleTickEvent();
238    _status = Idle;
239}
240
241
242void
243SimpleCPU::deallocateContext(int thread_num)
244{
245    // for now, these are equivalent
246    suspendContext(thread_num);
247}
248
249
250void
251SimpleCPU::haltContext(int thread_num)
252{
253    // for now, these are equivalent
254    suspendContext(thread_num);
255}
256
257
258void
259SimpleCPU::regStats()
260{
261    using namespace Stats;
262
263    BaseCPU::regStats();
264
265    numInsts
266        .name(name() + ".num_insts")
267        .desc("Number of instructions executed")
268        ;
269
270    numMemRefs
271        .name(name() + ".num_refs")
272        .desc("Number of memory references")
273        ;
274
275    notIdleFraction
276        .name(name() + ".not_idle_fraction")
277        .desc("Percentage of non-idle cycles")
278        ;
279
280    idleFraction
281        .name(name() + ".idle_fraction")
282        .desc("Percentage of idle cycles")
283        ;
284
285    icacheStallCycles
286        .name(name() + ".icache_stall_cycles")
287        .desc("ICache total stall cycles")
288        .prereq(icacheStallCycles)
289        ;
290
291    dcacheStallCycles
292        .name(name() + ".dcache_stall_cycles")
293        .desc("DCache total stall cycles")
294        .prereq(dcacheStallCycles)
295        ;
296
297    idleFraction = constant(1.0) - notIdleFraction;
298}
299
300void
301SimpleCPU::resetStats()
302{
303    startNumInst = numInst;
304    notIdleFraction = (_status != Idle);
305}
306
307void
308SimpleCPU::serialize(ostream &os)
309{
310    BaseCPU::serialize(os);
311    SERIALIZE_ENUM(_status);
312    SERIALIZE_SCALAR(inst);
313    nameOut(os, csprintf("%s.xc", name()));
314    xc->serialize(os);
315    nameOut(os, csprintf("%s.tickEvent", name()));
316    tickEvent.serialize(os);
317    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
318    cacheCompletionEvent.serialize(os);
319}
320
321void
322SimpleCPU::unserialize(Checkpoint *cp, const string &section)
323{
324    BaseCPU::unserialize(cp, section);
325    UNSERIALIZE_ENUM(_status);
326    UNSERIALIZE_SCALAR(inst);
327    xc->unserialize(cp, csprintf("%s.xc", section));
328    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
329    cacheCompletionEvent
330        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
331}
332
333void
334change_thread_state(int thread_number, int activate, int priority)
335{
336}
337
338Fault
339SimpleCPU::copySrcTranslate(Addr src)
340{
341    static bool no_warn = true;
342    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
343    // Only support block sizes of 64 atm.
344    assert(blk_size == 64);
345    int offset = src & (blk_size - 1);
346
347    // Make sure block doesn't span page
348    if (no_warn && (src & (~8191)) != ((src + blk_size) & (~8191)) &&
349        (src >> 40) != 0xfffffc) {
350        warn("Copied block source spans pages %x.", src);
351        no_warn = false;
352    }
353
354
355    memReq->reset(src & ~(blk_size - 1), blk_size);
356
357    // translate to physical address
358    Fault fault = xc->translateDataReadReq(memReq);
359
360    assert(fault != Alignment_Fault);
361
362    if (fault == No_Fault) {
363        xc->copySrcAddr = src;
364        xc->copySrcPhysAddr = memReq->paddr + offset;
365    } else {
366        xc->copySrcAddr = 0;
367        xc->copySrcPhysAddr = 0;
368    }
369    return fault;
370}
371
372Fault
373SimpleCPU::copy(Addr dest)
374{
375    static bool no_warn = true;
376    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
377    // Only support block sizes of 64 atm.
378    assert(blk_size == 64);
379    uint8_t data[blk_size];
380    //assert(xc->copySrcAddr);
381    int offset = dest & (blk_size - 1);
382
383    // Make sure block doesn't span page
384    if (no_warn && (dest & (~8191)) != ((dest + blk_size) & (~8191)) &&
385        (dest >> 40) != 0xfffffc) {
386        no_warn = false;
387        warn("Copied block destination spans pages %x. ", dest);
388    }
389
390    memReq->reset(dest & ~(blk_size -1), blk_size);
391    // translate to physical address
392    Fault fault = xc->translateDataWriteReq(memReq);
393
394    assert(fault != Alignment_Fault);
395
396    if (fault == No_Fault) {
397        Addr dest_addr = memReq->paddr + offset;
398        // Need to read straight from memory since we have more than 8 bytes.
399        memReq->paddr = xc->copySrcPhysAddr;
400        xc->mem->read(memReq, data);
401        memReq->paddr = dest_addr;
402        xc->mem->write(memReq, data);
403    }
404    return fault;
405}
406
407// precise architected memory state accessor macros
408template <class T>
409Fault
410SimpleCPU::read(Addr addr, T &data, unsigned flags)
411{
412    memReq->reset(addr, sizeof(T), flags);
413
414    // translate to physical address
415    Fault fault = xc->translateDataReadReq(memReq);
416
417    // do functional access
418    if (fault == No_Fault)
419        fault = xc->read(memReq, data);
420
421    if (traceData) {
422        traceData->setAddr(addr);
423        if (fault == No_Fault)
424            traceData->setData(data);
425    }
426
427    // if we have a cache, do cache access too
428    if (fault == No_Fault && dcacheInterface) {
429        memReq->cmd = Read;
430        memReq->completionEvent = NULL;
431        memReq->time = curTick;
432        MemAccessResult result = dcacheInterface->access(memReq);
433
434        // Ugly hack to get an event scheduled *only* if the access is
435        // a miss.  We really should add first-class support for this
436        // at some point.
437        if (result != MA_HIT && dcacheInterface->doEvents()) {
438            memReq->completionEvent = &cacheCompletionEvent;
439            lastDcacheStall = curTick;
440            unscheduleTickEvent();
441            _status = DcacheMissStall;
442        }
443    }
444
445    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
446        recordEvent("Uncached Read");
447
448    return fault;
449}
450
451#ifndef DOXYGEN_SHOULD_SKIP_THIS
452
453template
454Fault
455SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
456
457template
458Fault
459SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
460
461template
462Fault
463SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
464
465template
466Fault
467SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
468
469#endif //DOXYGEN_SHOULD_SKIP_THIS
470
471template<>
472Fault
473SimpleCPU::read(Addr addr, double &data, unsigned flags)
474{
475    return read(addr, *(uint64_t*)&data, flags);
476}
477
478template<>
479Fault
480SimpleCPU::read(Addr addr, float &data, unsigned flags)
481{
482    return read(addr, *(uint32_t*)&data, flags);
483}
484
485
486template<>
487Fault
488SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
489{
490    return read(addr, (uint32_t&)data, flags);
491}
492
493
494template <class T>
495Fault
496SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
497{
498    if (traceData) {
499        traceData->setAddr(addr);
500        traceData->setData(data);
501    }
502
503    memReq->reset(addr, sizeof(T), flags);
504
505    // translate to physical address
506    Fault fault = xc->translateDataWriteReq(memReq);
507
508    // do functional access
509    if (fault == No_Fault)
510        fault = xc->write(memReq, data);
511
512    if (fault == No_Fault && dcacheInterface) {
513        memReq->cmd = Write;
514        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
515        memReq->completionEvent = NULL;
516        memReq->time = curTick;
517        MemAccessResult result = dcacheInterface->access(memReq);
518
519        // Ugly hack to get an event scheduled *only* if the access is
520        // a miss.  We really should add first-class support for this
521        // at some point.
522        if (result != MA_HIT && dcacheInterface->doEvents()) {
523            memReq->completionEvent = &cacheCompletionEvent;
524            lastDcacheStall = curTick;
525            unscheduleTickEvent();
526            _status = DcacheMissStall;
527        }
528    }
529
530    if (res && (fault == No_Fault))
531        *res = memReq->result;
532
533    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
534        recordEvent("Uncached Write");
535
536    return fault;
537}
538
539
540#ifndef DOXYGEN_SHOULD_SKIP_THIS
541template
542Fault
543SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
544
545template
546Fault
547SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
548
549template
550Fault
551SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
552
553template
554Fault
555SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
556
557#endif //DOXYGEN_SHOULD_SKIP_THIS
558
559template<>
560Fault
561SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
562{
563    return write(*(uint64_t*)&data, addr, flags, res);
564}
565
566template<>
567Fault
568SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
569{
570    return write(*(uint32_t*)&data, addr, flags, res);
571}
572
573
574template<>
575Fault
576SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
577{
578    return write((uint32_t)data, addr, flags, res);
579}
580
581
582#ifdef FULL_SYSTEM
583Addr
584SimpleCPU::dbg_vtophys(Addr addr)
585{
586    return vtophys(xc, addr);
587}
588#endif // FULL_SYSTEM
589
590Tick save_cycle = 0;
591
592
593void
594SimpleCPU::processCacheCompletion()
595{
596    switch (status()) {
597      case IcacheMissStall:
598        icacheStallCycles += curTick - lastIcacheStall;
599        _status = IcacheMissComplete;
600        scheduleTickEvent(1);
601        break;
602      case DcacheMissStall:
603        dcacheStallCycles += curTick - lastDcacheStall;
604        _status = Running;
605        scheduleTickEvent(1);
606        break;
607      case SwitchedOut:
608        // If this CPU has been switched out due to sampling/warm-up,
609        // ignore any further status changes (e.g., due to cache
610        // misses outstanding at the time of the switch).
611        return;
612      default:
613        panic("SimpleCPU::processCacheCompletion: bad state");
614        break;
615    }
616}
617
618#ifdef FULL_SYSTEM
619void
620SimpleCPU::post_interrupt(int int_num, int index)
621{
622    BaseCPU::post_interrupt(int_num, index);
623
624    if (xc->status() == ExecContext::Suspended) {
625                DPRINTF(IPI,"Suspended Processor awoke\n");
626        xc->activate();
627    }
628}
629#endif // FULL_SYSTEM
630
631/* start simulation, program loaded, processor precise state initialized */
632void
633SimpleCPU::tick()
634{
635    numCycles++;
636
637    traceData = NULL;
638
639    Fault fault = No_Fault;
640
641#ifdef FULL_SYSTEM
642    if (AlphaISA::check_interrupts &&
643        xc->cpu->check_interrupts() &&
644        !PC_PAL(xc->regs.pc) &&
645        status() != IcacheMissComplete) {
646        int ipl = 0;
647        int summary = 0;
648        AlphaISA::check_interrupts = 0;
649        IntReg *ipr = xc->regs.ipr;
650
651        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
652            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
653                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
654                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
655                    // See table 4-19 of 21164 hardware reference
656                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
657                    summary |= (ULL(1) << i);
658                }
659            }
660        }
661
662        uint64_t interrupts = xc->cpu->intr_status();
663        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
664            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
665            if (interrupts & (ULL(1) << i)) {
666                // See table 4-19 of 21164 hardware reference
667                ipl = i;
668                summary |= (ULL(1) << i);
669            }
670        }
671
672        if (ipr[TheISA::IPR_ASTRR])
673            panic("asynchronous traps not implemented\n");
674
675        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
676            ipr[TheISA::IPR_ISR] = summary;
677            ipr[TheISA::IPR_INTID] = ipl;
678            xc->ev5_trap(Interrupt_Fault);
679
680            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
681                    ipr[TheISA::IPR_IPLR], ipl, summary);
682        }
683    }
684#endif
685
686    // maintain $r0 semantics
687    xc->regs.intRegFile[ZeroReg] = 0;
688#ifdef TARGET_ALPHA
689    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
690#endif // TARGET_ALPHA
691
692    if (status() == IcacheMissComplete) {
693        // We've already fetched an instruction and were stalled on an
694        // I-cache miss.  No need to fetch it again.
695
696        // Set status to running; tick event will get rescheduled if
697        // necessary at end of tick() function.
698        _status = Running;
699    }
700    else {
701        // Try to fetch an instruction
702
703        // set up memory request for instruction fetch
704#ifdef FULL_SYSTEM
705#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
706#else
707#define IFETCH_FLAGS(pc)	0
708#endif
709
710        memReq->cmd = Read;
711        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
712                     IFETCH_FLAGS(xc->regs.pc));
713
714        fault = xc->translateInstReq(memReq);
715
716        if (fault == No_Fault)
717            fault = xc->mem->read(memReq, inst);
718
719        if (icacheInterface && fault == No_Fault) {
720            memReq->completionEvent = NULL;
721
722            memReq->time = curTick;
723            MemAccessResult result = icacheInterface->access(memReq);
724
725            // Ugly hack to get an event scheduled *only* if the access is
726            // a miss.  We really should add first-class support for this
727            // at some point.
728            if (result != MA_HIT && icacheInterface->doEvents()) {
729                memReq->completionEvent = &cacheCompletionEvent;
730                lastIcacheStall = curTick;
731                unscheduleTickEvent();
732                _status = IcacheMissStall;
733                return;
734            }
735        }
736    }
737
738    // If we've got a valid instruction (i.e., no fault on instruction
739    // fetch), then execute it.
740    if (fault == No_Fault) {
741
742        // keep an instruction count
743        numInst++;
744        numInsts++;
745
746        // check for instruction-count-based events
747        comInstEventQueue[0]->serviceEvents(numInst);
748
749        // decode the instruction
750    inst = htoa(inst);
751        StaticInstPtr<TheISA> si(inst);
752
753        traceData = Trace::getInstRecord(curTick, xc, this, si,
754                                         xc->regs.pc);
755
756#ifdef FULL_SYSTEM
757        xc->setInst(inst);
758#endif // FULL_SYSTEM
759
760        xc->func_exe_inst++;
761
762        fault = si->execute(this, traceData);
763
764#ifdef FULL_SYSTEM
765        if (xc->fnbin)
766            xc->execute(si.get());
767#endif
768
769        if (si->isMemRef()) {
770            numMemRefs++;
771        }
772
773        if (si->isLoad()) {
774            ++numLoad;
775            comLoadEventQueue[0]->serviceEvents(numLoad);
776        }
777
778        if (traceData)
779            traceData->finalize();
780
781    }	// if (fault == No_Fault)
782
783    if (fault != No_Fault) {
784#ifdef FULL_SYSTEM
785        xc->ev5_trap(fault);
786#else // !FULL_SYSTEM
787        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
788#endif // FULL_SYSTEM
789    }
790    else {
791        // go to the next instruction
792        xc->regs.pc = xc->regs.npc;
793        xc->regs.npc += sizeof(MachInst);
794    }
795
796#ifdef FULL_SYSTEM
797    Addr oldpc;
798    do {
799        oldpc = xc->regs.pc;
800        system->pcEventQueue.service(xc);
801    } while (oldpc != xc->regs.pc);
802#endif
803
804    assert(status() == Running ||
805           status() == Idle ||
806           status() == DcacheMissStall);
807
808    if (status() == Running && !tickEvent.scheduled())
809        tickEvent.schedule(curTick + 1);
810}
811
812
813////////////////////////////////////////////////////////////////////////
814//
815//  SimpleCPU Simulation Object
816//
817BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
818
819    Param<Counter> max_insts_any_thread;
820    Param<Counter> max_insts_all_threads;
821    Param<Counter> max_loads_any_thread;
822    Param<Counter> max_loads_all_threads;
823
824#ifdef FULL_SYSTEM
825    SimObjectParam<AlphaITB *> itb;
826    SimObjectParam<AlphaDTB *> dtb;
827    SimObjectParam<FunctionalMemory *> mem;
828    SimObjectParam<System *> system;
829    Param<int> mult;
830#else
831    SimObjectParam<Process *> workload;
832#endif // FULL_SYSTEM
833
834    SimObjectParam<BaseMem *> icache;
835    SimObjectParam<BaseMem *> dcache;
836
837    Param<bool> defer_registration;
838    Param<int> multiplier;
839
840END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
841
842BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
843
844    INIT_PARAM_DFLT(max_insts_any_thread,
845                    "terminate when any thread reaches this inst count",
846                    0),
847    INIT_PARAM_DFLT(max_insts_all_threads,
848                    "terminate when all threads have reached this inst count",
849                    0),
850    INIT_PARAM_DFLT(max_loads_any_thread,
851                    "terminate when any thread reaches this load count",
852                    0),
853    INIT_PARAM_DFLT(max_loads_all_threads,
854                    "terminate when all threads have reached this load count",
855                    0),
856
857#ifdef FULL_SYSTEM
858    INIT_PARAM(itb, "Instruction TLB"),
859    INIT_PARAM(dtb, "Data TLB"),
860    INIT_PARAM(mem, "memory"),
861    INIT_PARAM(system, "system object"),
862    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
863#else
864    INIT_PARAM(workload, "processes to run"),
865#endif // FULL_SYSTEM
866
867    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
868    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
869    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
870                    "(for sampling)", false),
871
872    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
873
874END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
875
876
877CREATE_SIM_OBJECT(SimpleCPU)
878{
879    SimpleCPU *cpu;
880#ifdef FULL_SYSTEM
881    if (mult != 1)
882        panic("processor clock multiplier must be 1\n");
883
884    cpu = new SimpleCPU(getInstanceName(), system,
885                        max_insts_any_thread, max_insts_all_threads,
886                        max_loads_any_thread, max_loads_all_threads,
887                        itb, dtb, mem,
888                        (icache) ? icache->getInterface() : NULL,
889                        (dcache) ? dcache->getInterface() : NULL,
890                        defer_registration,
891                        ticksPerSecond * mult);
892#else
893
894    cpu = new SimpleCPU(getInstanceName(), workload,
895                        max_insts_any_thread, max_insts_all_threads,
896                        max_loads_any_thread, max_loads_all_threads,
897                        (icache) ? icache->getInterface() : NULL,
898                        (dcache) ? dcache->getInterface() : NULL,
899                        defer_registration);
900
901#endif // FULL_SYSTEM
902
903    cpu->setTickMultiplier(multiplier);
904
905    return cpu;
906}
907
908REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
909
910