indirect.hh revision 11426
111426Smitch.hayenga@arm.com/* 211426Smitch.hayenga@arm.com * Copyright (c) 2014 ARM Limited 311426Smitch.hayenga@arm.com * All rights reserved. 411426Smitch.hayenga@arm.com * 511426Smitch.hayenga@arm.com * Redistribution and use in source and binary forms, with or without 611426Smitch.hayenga@arm.com * modification, are permitted provided that the following conditions are 711426Smitch.hayenga@arm.com * met: redistributions of source code must retain the above copyright 811426Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer; 911426Smitch.hayenga@arm.com * redistributions in binary form must reproduce the above copyright 1011426Smitch.hayenga@arm.com * notice, this list of conditions and the following disclaimer in the 1111426Smitch.hayenga@arm.com * documentation and/or other materials provided with the distribution; 1211426Smitch.hayenga@arm.com * neither the name of the copyright holders nor the names of its 1311426Smitch.hayenga@arm.com * contributors may be used to endorse or promote products derived from 1411426Smitch.hayenga@arm.com * this software without specific prior written permission. 1511426Smitch.hayenga@arm.com * 1611426Smitch.hayenga@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711426Smitch.hayenga@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811426Smitch.hayenga@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911426Smitch.hayenga@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011426Smitch.hayenga@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111426Smitch.hayenga@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211426Smitch.hayenga@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311426Smitch.hayenga@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411426Smitch.hayenga@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511426Smitch.hayenga@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611426Smitch.hayenga@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711426Smitch.hayenga@arm.com * 2811426Smitch.hayenga@arm.com * Authors: Mitch Hayenga 2911426Smitch.hayenga@arm.com */ 3011426Smitch.hayenga@arm.com 3111426Smitch.hayenga@arm.com#ifndef __CPU_PRED_INDIRECT_HH__ 3211426Smitch.hayenga@arm.com#define __CPU_PRED_INDIRECT_HH__ 3311426Smitch.hayenga@arm.com 3411426Smitch.hayenga@arm.com#include <deque> 3511426Smitch.hayenga@arm.com 3611426Smitch.hayenga@arm.com#include "arch/isa_traits.hh" 3711426Smitch.hayenga@arm.com#include "config/the_isa.hh" 3811426Smitch.hayenga@arm.com#include "cpu/inst_seq.hh" 3911426Smitch.hayenga@arm.com 4011426Smitch.hayenga@arm.comclass IndirectPredictor 4111426Smitch.hayenga@arm.com{ 4211426Smitch.hayenga@arm.com public: 4311426Smitch.hayenga@arm.com IndirectPredictor(bool hash_ghr, bool hash_targets, 4411426Smitch.hayenga@arm.com unsigned num_sets, unsigned num_ways, 4511426Smitch.hayenga@arm.com unsigned tag_bits, unsigned path_len, 4611426Smitch.hayenga@arm.com unsigned inst_shift, unsigned num_threads); 4711426Smitch.hayenga@arm.com bool lookup(Addr br_addr, unsigned ghr, TheISA::PCState& br_target, 4811426Smitch.hayenga@arm.com ThreadID tid); 4911426Smitch.hayenga@arm.com void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, 5011426Smitch.hayenga@arm.com ThreadID tid); 5111426Smitch.hayenga@arm.com void commit(InstSeqNum seq_num, ThreadID tid); 5211426Smitch.hayenga@arm.com void squash(InstSeqNum seq_num, ThreadID tid); 5311426Smitch.hayenga@arm.com void recordTarget(InstSeqNum seq_num, unsigned ghr, 5411426Smitch.hayenga@arm.com const TheISA::PCState& target, ThreadID tid); 5511426Smitch.hayenga@arm.com 5611426Smitch.hayenga@arm.com private: 5711426Smitch.hayenga@arm.com const bool hashGHR; 5811426Smitch.hayenga@arm.com const bool hashTargets; 5911426Smitch.hayenga@arm.com const unsigned numSets; 6011426Smitch.hayenga@arm.com const unsigned numWays; 6111426Smitch.hayenga@arm.com const unsigned tagBits; 6211426Smitch.hayenga@arm.com const unsigned pathLength; 6311426Smitch.hayenga@arm.com const unsigned instShift; 6411426Smitch.hayenga@arm.com 6511426Smitch.hayenga@arm.com struct IPredEntry 6611426Smitch.hayenga@arm.com { 6711426Smitch.hayenga@arm.com IPredEntry() : tag(0), target(0) { } 6811426Smitch.hayenga@arm.com Addr tag; 6911426Smitch.hayenga@arm.com TheISA::PCState target; 7011426Smitch.hayenga@arm.com }; 7111426Smitch.hayenga@arm.com 7211426Smitch.hayenga@arm.com std::vector<std::vector<IPredEntry> > targetCache; 7311426Smitch.hayenga@arm.com 7411426Smitch.hayenga@arm.com Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid); 7511426Smitch.hayenga@arm.com Addr getTag(Addr br_addr); 7611426Smitch.hayenga@arm.com 7711426Smitch.hayenga@arm.com struct HistoryEntry 7811426Smitch.hayenga@arm.com { 7911426Smitch.hayenga@arm.com HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num) 8011426Smitch.hayenga@arm.com : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { } 8111426Smitch.hayenga@arm.com Addr pcAddr; 8211426Smitch.hayenga@arm.com Addr targetAddr; 8311426Smitch.hayenga@arm.com InstSeqNum seqNum; 8411426Smitch.hayenga@arm.com }; 8511426Smitch.hayenga@arm.com 8611426Smitch.hayenga@arm.com 8711426Smitch.hayenga@arm.com struct ThreadInfo { 8811426Smitch.hayenga@arm.com ThreadInfo() : headHistEntry(0) { } 8911426Smitch.hayenga@arm.com 9011426Smitch.hayenga@arm.com std::deque<HistoryEntry> pathHist; 9111426Smitch.hayenga@arm.com unsigned headHistEntry; 9211426Smitch.hayenga@arm.com }; 9311426Smitch.hayenga@arm.com 9411426Smitch.hayenga@arm.com std::vector<ThreadInfo> threadInfo; 9511426Smitch.hayenga@arm.com}; 9611426Smitch.hayenga@arm.com 9711426Smitch.hayenga@arm.com#endif // __CPU_PRED_INDIRECT_HH__ 98