indirect.hh revision 11426
1/* 2 * Copyright (c) 2014 ARM Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Mitch Hayenga 29 */ 30 31#ifndef __CPU_PRED_INDIRECT_HH__ 32#define __CPU_PRED_INDIRECT_HH__ 33 34#include <deque> 35 36#include "arch/isa_traits.hh" 37#include "config/the_isa.hh" 38#include "cpu/inst_seq.hh" 39 40class IndirectPredictor 41{ 42 public: 43 IndirectPredictor(bool hash_ghr, bool hash_targets, 44 unsigned num_sets, unsigned num_ways, 45 unsigned tag_bits, unsigned path_len, 46 unsigned inst_shift, unsigned num_threads); 47 bool lookup(Addr br_addr, unsigned ghr, TheISA::PCState& br_target, 48 ThreadID tid); 49 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, 50 ThreadID tid); 51 void commit(InstSeqNum seq_num, ThreadID tid); 52 void squash(InstSeqNum seq_num, ThreadID tid); 53 void recordTarget(InstSeqNum seq_num, unsigned ghr, 54 const TheISA::PCState& target, ThreadID tid); 55 56 private: 57 const bool hashGHR; 58 const bool hashTargets; 59 const unsigned numSets; 60 const unsigned numWays; 61 const unsigned tagBits; 62 const unsigned pathLength; 63 const unsigned instShift; 64 65 struct IPredEntry 66 { 67 IPredEntry() : tag(0), target(0) { } 68 Addr tag; 69 TheISA::PCState target; 70 }; 71 72 std::vector<std::vector<IPredEntry> > targetCache; 73 74 Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid); 75 Addr getTag(Addr br_addr); 76 77 struct HistoryEntry 78 { 79 HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num) 80 : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { } 81 Addr pcAddr; 82 Addr targetAddr; 83 InstSeqNum seqNum; 84 }; 85 86 87 struct ThreadInfo { 88 ThreadInfo() : headHistEntry(0) { } 89 90 std::deque<HistoryEntry> pathHist; 91 unsigned headHistEntry; 92 }; 93 94 std::vector<ThreadInfo> threadInfo; 95}; 96 97#endif // __CPU_PRED_INDIRECT_HH__ 98