store_set.hh revision 6221
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_STORE_SET_HH__ 32#define __CPU_O3_STORE_SET_HH__ 33 34#include <list> 35#include <map> 36#include <utility> 37#include <vector> 38 39#include "base/types.hh" 40#include "cpu/inst_seq.hh" 41 42struct ltseqnum { 43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 44 { 45 return lhs > rhs; 46 } 47}; 48 49/** 50 * Implements a store set predictor for determining if memory 51 * instructions are dependent upon each other. See paper "Memory 52 * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID 53 * stands for Store Set ID, SSIT stands for Store Set ID Table, and 54 * LFST is Last Fetched Store Table. 55 */ 56class StoreSet 57{ 58 public: 59 typedef unsigned SSID; 60 61 public: 62 /** Default constructor. init() must be called prior to use. */ 63 StoreSet() { }; 64 65 /** Creates store set predictor with given table sizes. */ 66 StoreSet(int SSIT_size, int LFST_size); 67 68 /** Default destructor. */ 69 ~StoreSet(); 70 71 /** Initializes the store set predictor with the given table sizes. */ 72 void init(int SSIT_size, int LFST_size); 73 74 /** Records a memory ordering violation between the younger load 75 * and the older store. */ 76 void violation(Addr store_PC, Addr load_PC); 77 78 /** Inserts a load into the store set predictor. This does nothing but 79 * is included in case other predictors require a similar function. 80 */ 81 void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 82 83 /** Inserts a store into the store set predictor. Updates the 84 * LFST if the store has a valid SSID. */ 85 void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid); 86 87 /** Checks if the instruction with the given PC is dependent upon 88 * any store. @return Returns the sequence number of the store 89 * instruction this PC is dependent upon. Returns 0 if none. 90 */ 91 InstSeqNum checkInst(Addr PC); 92 93 /** Records this PC/sequence number as issued. */ 94 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 95 96 /** Squashes for a specific thread until the given sequence number. */ 97 void squash(InstSeqNum squashed_num, ThreadID tid); 98 99 /** Resets all tables. */ 100 void clear(); 101 102 /** Debug function to dump the contents of the store list. */ 103 void dump(); 104 105 private: 106 /** Calculates the index into the SSIT based on the PC. */ 107 inline int calcIndex(Addr PC) 108 { return (PC >> offsetBits) & indexMask; } 109 110 /** Calculates a Store Set ID based on the PC. */ 111 inline SSID calcSSID(Addr PC) 112 { return ((PC ^ (PC >> 10)) % LFSTSize); } 113 114 /** The Store Set ID Table. */ 115 std::vector<SSID> SSIT; 116 117 /** Bit vector to tell if the SSIT has a valid entry. */ 118 std::vector<bool> validSSIT; 119 120 /** Last Fetched Store Table. */ 121 std::vector<InstSeqNum> LFST; 122 123 /** Bit vector to tell if the LFST has a valid entry. */ 124 std::vector<bool> validLFST; 125 126 /** Map of stores that have been inserted into the store set, but 127 * not yet issued or squashed. 128 */ 129 std::map<InstSeqNum, int, ltseqnum> storeList; 130 131 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; 132 133 /** Store Set ID Table size, in entries. */ 134 int SSITSize; 135 136 /** Last Fetched Store Table size, in entries. */ 137 int LFSTSize; 138 139 /** Mask to obtain the index. */ 140 int indexMask; 141 142 // HACK: Hardcoded for now. 143 int offsetBits; 144}; 145 146#endif // __CPU_O3_STORE_SET_HH__ 147