store_set.hh revision 2980:eab855f06b79 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_O3_STORE_SET_HH__
32#define __CPU_O3_STORE_SET_HH__
33
34#include <list>
35#include <map>
36#include <utility>
37#include <vector>
38
39#include "cpu/inst_seq.hh"
40#include "sim/host.hh"
41
42struct ltseqnum {
43    bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
44    {
45        return lhs > rhs;
46    }
47};
48
49/**
50 * Implements a store set predictor for determining if memory
51 * instructions are dependent upon each other.  See paper "Memory
52 * Dependence Prediction using Store Sets" by Chrysos and Emer.  SSID
53 * stands for Store Set ID, SSIT stands for Store Set ID Table, and
54 * LFST is Last Fetched Store Table.
55 */
56class StoreSet
57{
58  public:
59    typedef unsigned SSID;
60
61  public:
62    /** Default constructor.  init() must be called prior to use. */
63    StoreSet() { };
64
65    /** Creates store set predictor with given table sizes. */
66    StoreSet(int SSIT_size, int LFST_size);
67
68    /** Default destructor. */
69    ~StoreSet();
70
71    /** Initializes the store set predictor with the given table sizes. */
72    void init(int SSIT_size, int LFST_size);
73
74    /** Records a memory ordering violation between the younger load
75     * and the older store. */
76    void violation(Addr store_PC, Addr load_PC);
77
78    /** Inserts a load into the store set predictor.  This does nothing but
79     * is included in case other predictors require a similar function.
80     */
81    void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
82
83    /** Inserts a store into the store set predictor.  Updates the
84     * LFST if the store has a valid SSID. */
85    void insertStore(Addr store_PC, InstSeqNum store_seq_num,
86                     unsigned tid);
87
88    /** Checks if the instruction with the given PC is dependent upon
89     * any store.  @return Returns the sequence number of the store
90     * instruction this PC is dependent upon.  Returns 0 if none.
91     */
92    InstSeqNum checkInst(Addr PC);
93
94    /** Records this PC/sequence number as issued. */
95    void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
96
97    /** Squashes for a specific thread until the given sequence number. */
98    void squash(InstSeqNum squashed_num, unsigned tid);
99
100    /** Resets all tables. */
101    void clear();
102
103    /** Debug function to dump the contents of the store list. */
104    void dump();
105
106  private:
107    /** Calculates the index into the SSIT based on the PC. */
108    inline int calcIndex(Addr PC)
109    { return (PC >> offsetBits) & indexMask; }
110
111    /** Calculates a Store Set ID based on the PC. */
112    inline SSID calcSSID(Addr PC)
113    { return ((PC ^ (PC >> 10)) % LFSTSize); }
114
115    /** The Store Set ID Table. */
116    std::vector<SSID> SSIT;
117
118    /** Bit vector to tell if the SSIT has a valid entry. */
119    std::vector<bool> validSSIT;
120
121    /** Last Fetched Store Table. */
122    std::vector<InstSeqNum> LFST;
123
124    /** Bit vector to tell if the LFST has a valid entry. */
125    std::vector<bool> validLFST;
126
127    /** Map of stores that have been inserted into the store set, but
128     * not yet issued or squashed.
129     */
130    std::map<InstSeqNum, int, ltseqnum> storeList;
131
132    typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
133
134    /** Store Set ID Table size, in entries. */
135    int SSITSize;
136
137    /** Last Fetched Store Table size, in entries. */
138    int LFSTSize;
139
140    /** Mask to obtain the index. */
141    int indexMask;
142
143    // HACK: Hardcoded for now.
144    int offsetBits;
145};
146
147#endif // __CPU_O3_STORE_SET_HH__
148