store_set.hh revision 6216
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312292SN/A#ifndef __CPU_O3_STORE_SET_HH__ 322292SN/A#define __CPU_O3_STORE_SET_HH__ 331061SN/A 342292SN/A#include <list> 352292SN/A#include <map> 362292SN/A#include <utility> 371061SN/A#include <vector> 381061SN/A 396216Snate@binkert.org#include "base/types.hh" 401061SN/A#include "cpu/inst_seq.hh" 411061SN/A 422292SN/Astruct ltseqnum { 432292SN/A bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const 442292SN/A { 452292SN/A return lhs > rhs; 462292SN/A } 472292SN/A}; 482292SN/A 492348SN/A/** 502348SN/A * Implements a store set predictor for determining if memory 512348SN/A * instructions are dependent upon each other. See paper "Memory 522348SN/A * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID 532348SN/A * stands for Store Set ID, SSIT stands for Store Set ID Table, and 542348SN/A * LFST is Last Fetched Store Table. 552348SN/A */ 561061SN/Aclass StoreSet 571061SN/A{ 581061SN/A public: 591061SN/A typedef unsigned SSID; 601061SN/A 611061SN/A public: 622348SN/A /** Default constructor. init() must be called prior to use. */ 632292SN/A StoreSet() { }; 642292SN/A 652348SN/A /** Creates store set predictor with given table sizes. */ 661061SN/A StoreSet(int SSIT_size, int LFST_size); 671061SN/A 682348SN/A /** Default destructor. */ 692292SN/A ~StoreSet(); 702292SN/A 712348SN/A /** Initializes the store set predictor with the given table sizes. */ 722292SN/A void init(int SSIT_size, int LFST_size); 732292SN/A 742348SN/A /** Records a memory ordering violation between the younger load 752348SN/A * and the older store. */ 761062SN/A void violation(Addr store_PC, Addr load_PC); 771061SN/A 782348SN/A /** Inserts a load into the store set predictor. This does nothing but 792348SN/A * is included in case other predictors require a similar function. 802348SN/A */ 811061SN/A void insertLoad(Addr load_PC, InstSeqNum load_seq_num); 821061SN/A 832348SN/A /** Inserts a store into the store set predictor. Updates the 842348SN/A * LFST if the store has a valid SSID. */ 852292SN/A void insertStore(Addr store_PC, InstSeqNum store_seq_num, 862292SN/A unsigned tid); 871061SN/A 882348SN/A /** Checks if the instruction with the given PC is dependent upon 892348SN/A * any store. @return Returns the sequence number of the store 902348SN/A * instruction this PC is dependent upon. Returns 0 if none. 912348SN/A */ 921061SN/A InstSeqNum checkInst(Addr PC); 931061SN/A 942348SN/A /** Records this PC/sequence number as issued. */ 951061SN/A void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store); 961061SN/A 972348SN/A /** Squashes for a specific thread until the given sequence number. */ 982292SN/A void squash(InstSeqNum squashed_num, unsigned tid); 991061SN/A 1002348SN/A /** Resets all tables. */ 1011061SN/A void clear(); 1021061SN/A 1032348SN/A /** Debug function to dump the contents of the store list. */ 1042348SN/A void dump(); 1052348SN/A 1061061SN/A private: 1072348SN/A /** Calculates the index into the SSIT based on the PC. */ 1081061SN/A inline int calcIndex(Addr PC) 1092292SN/A { return (PC >> offsetBits) & indexMask; } 1101061SN/A 1112348SN/A /** Calculates a Store Set ID based on the PC. */ 1121061SN/A inline SSID calcSSID(Addr PC) 1132292SN/A { return ((PC ^ (PC >> 10)) % LFSTSize); } 1141061SN/A 1152348SN/A /** The Store Set ID Table. */ 1162292SN/A std::vector<SSID> SSIT; 1171061SN/A 1182348SN/A /** Bit vector to tell if the SSIT has a valid entry. */ 1191061SN/A std::vector<bool> validSSIT; 1201061SN/A 1212348SN/A /** Last Fetched Store Table. */ 1222292SN/A std::vector<InstSeqNum> LFST; 1231061SN/A 1242348SN/A /** Bit vector to tell if the LFST has a valid entry. */ 1251061SN/A std::vector<bool> validLFST; 1261061SN/A 1272348SN/A /** Map of stores that have been inserted into the store set, but 1282348SN/A * not yet issued or squashed. 1292348SN/A */ 1302292SN/A std::map<InstSeqNum, int, ltseqnum> storeList; 1311061SN/A 1322292SN/A typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt; 1331061SN/A 1342348SN/A /** Store Set ID Table size, in entries. */ 1352292SN/A int SSITSize; 1361061SN/A 1372348SN/A /** Last Fetched Store Table size, in entries. */ 1382292SN/A int LFSTSize; 1392292SN/A 1402348SN/A /** Mask to obtain the index. */ 1412292SN/A int indexMask; 1421061SN/A 1431061SN/A // HACK: Hardcoded for now. 1442292SN/A int offsetBits; 1451061SN/A}; 1461061SN/A 1472292SN/A#endif // __CPU_O3_STORE_SET_HH__ 148