iew_impl.hh revision 3867
11689SN/A/*
22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
311060SN/A// @todo: Fix the instantaneous communication among all the stages within
321060SN/A// iew.  There's a clear delay between issue and execute, yet backwards
331689SN/A// communication happens simultaneously.
341060SN/A
351060SN/A#include <queue>
361060SN/A
371060SN/A#include "base/timebuf.hh"
382292SN/A#include "cpu/o3/fu_pool.hh"
391717SN/A#include "cpu/o3/iew.hh"
401060SN/A
411681SN/Atemplate<class Impl>
422292SN/ADefaultIEW<Impl>::DefaultIEW(Params *params)
432873Sktlim@umich.edu    : issueToExecQueue(params->backComSize, params->forwardComSize),
441060SN/A      instQueue(params),
451061SN/A      ldstQueue(params),
462292SN/A      fuPool(params->fuPool),
472292SN/A      commitToIEWDelay(params->commitToIEWDelay),
482292SN/A      renameToIEWDelay(params->renameToIEWDelay),
492292SN/A      issueToExecuteDelay(params->issueToExecuteDelay),
502820Sktlim@umich.edu      dispatchWidth(params->dispatchWidth),
512292SN/A      issueWidth(params->issueWidth),
522820Sktlim@umich.edu      wbOutstanding(0),
532820Sktlim@umich.edu      wbWidth(params->wbWidth),
542307SN/A      numThreads(params->numberOfThreads),
552307SN/A      switchedOut(false)
561060SN/A{
572292SN/A    _status = Active;
582292SN/A    exeStatus = Running;
592292SN/A    wbStatus = Idle;
601060SN/A
611060SN/A    // Setup wire to read instructions coming from issue.
621060SN/A    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
631060SN/A
641060SN/A    // Instruction queue needs the queue between issue and execute.
651060SN/A    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
661681SN/A
672292SN/A    instQueue.setIEW(this);
681681SN/A    ldstQueue.setIEW(this);
692292SN/A
702292SN/A    for (int i=0; i < numThreads; i++) {
712292SN/A        dispatchStatus[i] = Running;
722292SN/A        stalls[i].commit = false;
732292SN/A        fetchRedirect[i] = false;
742935Sksewell@umich.edu        bdelayDoneSeqNum[i] = 0;
752292SN/A    }
762292SN/A
772820Sktlim@umich.edu    wbMax = wbWidth * params->wbDepth;
782820Sktlim@umich.edu
792292SN/A    updateLSQNextCycle = false;
802292SN/A
812820Sktlim@umich.edu    ableToIssue = true;
822820Sktlim@umich.edu
832292SN/A    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
842292SN/A}
852292SN/A
862292SN/Atemplate <class Impl>
872292SN/Astd::string
882292SN/ADefaultIEW<Impl>::name() const
892292SN/A{
902292SN/A    return cpu->name() + ".iew";
911060SN/A}
921060SN/A
931681SN/Atemplate <class Impl>
941062SN/Avoid
952292SN/ADefaultIEW<Impl>::regStats()
961062SN/A{
972301SN/A    using namespace Stats;
982301SN/A
991062SN/A    instQueue.regStats();
1002727Sktlim@umich.edu    ldstQueue.regStats();
1011062SN/A
1021062SN/A    iewIdleCycles
1031062SN/A        .name(name() + ".iewIdleCycles")
1041062SN/A        .desc("Number of cycles IEW is idle");
1051062SN/A
1061062SN/A    iewSquashCycles
1071062SN/A        .name(name() + ".iewSquashCycles")
1081062SN/A        .desc("Number of cycles IEW is squashing");
1091062SN/A
1101062SN/A    iewBlockCycles
1111062SN/A        .name(name() + ".iewBlockCycles")
1121062SN/A        .desc("Number of cycles IEW is blocking");
1131062SN/A
1141062SN/A    iewUnblockCycles
1151062SN/A        .name(name() + ".iewUnblockCycles")
1161062SN/A        .desc("Number of cycles IEW is unblocking");
1171062SN/A
1181062SN/A    iewDispatchedInsts
1191062SN/A        .name(name() + ".iewDispatchedInsts")
1201062SN/A        .desc("Number of instructions dispatched to IQ");
1211062SN/A
1221062SN/A    iewDispSquashedInsts
1231062SN/A        .name(name() + ".iewDispSquashedInsts")
1241062SN/A        .desc("Number of squashed instructions skipped by dispatch");
1251062SN/A
1261062SN/A    iewDispLoadInsts
1271062SN/A        .name(name() + ".iewDispLoadInsts")
1281062SN/A        .desc("Number of dispatched load instructions");
1291062SN/A
1301062SN/A    iewDispStoreInsts
1311062SN/A        .name(name() + ".iewDispStoreInsts")
1321062SN/A        .desc("Number of dispatched store instructions");
1331062SN/A
1341062SN/A    iewDispNonSpecInsts
1351062SN/A        .name(name() + ".iewDispNonSpecInsts")
1361062SN/A        .desc("Number of dispatched non-speculative instructions");
1371062SN/A
1381062SN/A    iewIQFullEvents
1391062SN/A        .name(name() + ".iewIQFullEvents")
1401062SN/A        .desc("Number of times the IQ has become full, causing a stall");
1411062SN/A
1422292SN/A    iewLSQFullEvents
1432292SN/A        .name(name() + ".iewLSQFullEvents")
1442292SN/A        .desc("Number of times the LSQ has become full, causing a stall");
1452292SN/A
1461062SN/A    memOrderViolationEvents
1471062SN/A        .name(name() + ".memOrderViolationEvents")
1481062SN/A        .desc("Number of memory order violations");
1491062SN/A
1501062SN/A    predictedTakenIncorrect
1511062SN/A        .name(name() + ".predictedTakenIncorrect")
1521062SN/A        .desc("Number of branches that were predicted taken incorrectly");
1532292SN/A
1542292SN/A    predictedNotTakenIncorrect
1552292SN/A        .name(name() + ".predictedNotTakenIncorrect")
1562292SN/A        .desc("Number of branches that were predicted not taken incorrectly");
1572292SN/A
1582292SN/A    branchMispredicts
1592292SN/A        .name(name() + ".branchMispredicts")
1602292SN/A        .desc("Number of branch mispredicts detected at execute");
1612292SN/A
1622292SN/A    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
1632301SN/A
1642727Sktlim@umich.edu    iewExecutedInsts
1652353SN/A        .name(name() + ".iewExecutedInsts")
1662727Sktlim@umich.edu        .desc("Number of executed instructions");
1672727Sktlim@umich.edu
1682727Sktlim@umich.edu    iewExecLoadInsts
1692727Sktlim@umich.edu        .init(cpu->number_of_threads)
1702353SN/A        .name(name() + ".iewExecLoadInsts")
1712727Sktlim@umich.edu        .desc("Number of load instructions executed")
1722727Sktlim@umich.edu        .flags(total);
1732727Sktlim@umich.edu
1742727Sktlim@umich.edu    iewExecSquashedInsts
1752353SN/A        .name(name() + ".iewExecSquashedInsts")
1762727Sktlim@umich.edu        .desc("Number of squashed instructions skipped in execute");
1772727Sktlim@umich.edu
1782727Sktlim@umich.edu    iewExecutedSwp
1792301SN/A        .init(cpu->number_of_threads)
1802301SN/A        .name(name() + ".EXEC:swp")
1812301SN/A        .desc("number of swp insts executed")
1822727Sktlim@umich.edu        .flags(total);
1832301SN/A
1842727Sktlim@umich.edu    iewExecutedNop
1852301SN/A        .init(cpu->number_of_threads)
1862301SN/A        .name(name() + ".EXEC:nop")
1872301SN/A        .desc("number of nop insts executed")
1882727Sktlim@umich.edu        .flags(total);
1892301SN/A
1902727Sktlim@umich.edu    iewExecutedRefs
1912301SN/A        .init(cpu->number_of_threads)
1922301SN/A        .name(name() + ".EXEC:refs")
1932301SN/A        .desc("number of memory reference insts executed")
1942727Sktlim@umich.edu        .flags(total);
1952301SN/A
1962727Sktlim@umich.edu    iewExecutedBranches
1972301SN/A        .init(cpu->number_of_threads)
1982301SN/A        .name(name() + ".EXEC:branches")
1992301SN/A        .desc("Number of branches executed")
2002727Sktlim@umich.edu        .flags(total);
2012301SN/A
2022301SN/A    iewExecStoreInsts
2032301SN/A        .name(name() + ".EXEC:stores")
2042301SN/A        .desc("Number of stores executed")
2052727Sktlim@umich.edu        .flags(total);
2062727Sktlim@umich.edu    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
2072727Sktlim@umich.edu
2082727Sktlim@umich.edu    iewExecRate
2092727Sktlim@umich.edu        .name(name() + ".EXEC:rate")
2102727Sktlim@umich.edu        .desc("Inst execution rate")
2112727Sktlim@umich.edu        .flags(total);
2122727Sktlim@umich.edu
2132727Sktlim@umich.edu    iewExecRate = iewExecutedInsts / cpu->numCycles;
2142301SN/A
2152301SN/A    iewInstsToCommit
2162301SN/A        .init(cpu->number_of_threads)
2172301SN/A        .name(name() + ".WB:sent")
2182301SN/A        .desc("cumulative count of insts sent to commit")
2192727Sktlim@umich.edu        .flags(total);
2202301SN/A
2212326SN/A    writebackCount
2222301SN/A        .init(cpu->number_of_threads)
2232301SN/A        .name(name() + ".WB:count")
2242301SN/A        .desc("cumulative count of insts written-back")
2252727Sktlim@umich.edu        .flags(total);
2262301SN/A
2272326SN/A    producerInst
2282301SN/A        .init(cpu->number_of_threads)
2292301SN/A        .name(name() + ".WB:producers")
2302301SN/A        .desc("num instructions producing a value")
2312727Sktlim@umich.edu        .flags(total);
2322301SN/A
2332326SN/A    consumerInst
2342301SN/A        .init(cpu->number_of_threads)
2352301SN/A        .name(name() + ".WB:consumers")
2362301SN/A        .desc("num instructions consuming a value")
2372727Sktlim@umich.edu        .flags(total);
2382301SN/A
2392326SN/A    wbPenalized
2402301SN/A        .init(cpu->number_of_threads)
2412301SN/A        .name(name() + ".WB:penalized")
2422301SN/A        .desc("number of instrctions required to write to 'other' IQ")
2432727Sktlim@umich.edu        .flags(total);
2442301SN/A
2452326SN/A    wbPenalizedRate
2462301SN/A        .name(name() + ".WB:penalized_rate")
2472301SN/A        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
2482727Sktlim@umich.edu        .flags(total);
2492301SN/A
2502326SN/A    wbPenalizedRate = wbPenalized / writebackCount;
2512301SN/A
2522326SN/A    wbFanout
2532301SN/A        .name(name() + ".WB:fanout")
2542301SN/A        .desc("average fanout of values written-back")
2552727Sktlim@umich.edu        .flags(total);
2562301SN/A
2572326SN/A    wbFanout = producerInst / consumerInst;
2582301SN/A
2592326SN/A    wbRate
2602301SN/A        .name(name() + ".WB:rate")
2612301SN/A        .desc("insts written-back per cycle")
2622727Sktlim@umich.edu        .flags(total);
2632326SN/A    wbRate = writebackCount / cpu->numCycles;
2641062SN/A}
2651062SN/A
2661681SN/Atemplate<class Impl>
2671060SN/Avoid
2682292SN/ADefaultIEW<Impl>::initStage()
2691060SN/A{
2702292SN/A    for (int tid=0; tid < numThreads; tid++) {
2712292SN/A        toRename->iewInfo[tid].usedIQ = true;
2722292SN/A        toRename->iewInfo[tid].freeIQEntries =
2732292SN/A            instQueue.numFreeEntries(tid);
2742292SN/A
2752292SN/A        toRename->iewInfo[tid].usedLSQ = true;
2762292SN/A        toRename->iewInfo[tid].freeLSQEntries =
2772292SN/A            ldstQueue.numFreeEntries(tid);
2782292SN/A    }
2792292SN/A}
2802292SN/A
2812292SN/Atemplate<class Impl>
2822292SN/Avoid
2832733Sktlim@umich.eduDefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
2842292SN/A{
2852292SN/A    DPRINTF(IEW, "Setting CPU pointer.\n");
2861060SN/A    cpu = cpu_ptr;
2871060SN/A
2881060SN/A    instQueue.setCPU(cpu_ptr);
2891061SN/A    ldstQueue.setCPU(cpu_ptr);
2902292SN/A
2912733Sktlim@umich.edu    cpu->activateStage(O3CPU::IEWIdx);
2921060SN/A}
2931060SN/A
2941681SN/Atemplate<class Impl>
2951060SN/Avoid
2962292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
2971060SN/A{
2982292SN/A    DPRINTF(IEW, "Setting time buffer pointer.\n");
2991060SN/A    timeBuffer = tb_ptr;
3001060SN/A
3011060SN/A    // Setup wire to read information from time buffer, from commit.
3021060SN/A    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
3031060SN/A
3041060SN/A    // Setup wire to write information back to previous stages.
3051060SN/A    toRename = timeBuffer->getWire(0);
3061060SN/A
3072292SN/A    toFetch = timeBuffer->getWire(0);
3082292SN/A
3091060SN/A    // Instruction queue also needs main time buffer.
3101060SN/A    instQueue.setTimeBuffer(tb_ptr);
3111060SN/A}
3121060SN/A
3131681SN/Atemplate<class Impl>
3141060SN/Avoid
3152292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
3161060SN/A{
3172292SN/A    DPRINTF(IEW, "Setting rename queue pointer.\n");
3181060SN/A    renameQueue = rq_ptr;
3191060SN/A
3201060SN/A    // Setup wire to read information from rename queue.
3211060SN/A    fromRename = renameQueue->getWire(-renameToIEWDelay);
3221060SN/A}
3231060SN/A
3241681SN/Atemplate<class Impl>
3251060SN/Avoid
3262292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
3271060SN/A{
3282292SN/A    DPRINTF(IEW, "Setting IEW queue pointer.\n");
3291060SN/A    iewQueue = iq_ptr;
3301060SN/A
3311060SN/A    // Setup wire to write instructions to commit.
3321060SN/A    toCommit = iewQueue->getWire(0);
3331060SN/A}
3341060SN/A
3351681SN/Atemplate<class Impl>
3361060SN/Avoid
3372980Sgblack@eecs.umich.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
3381060SN/A{
3392292SN/A    DPRINTF(IEW, "Setting active threads list pointer.\n");
3402292SN/A    activeThreads = at_ptr;
3412292SN/A
3422292SN/A    ldstQueue.setActiveThreads(at_ptr);
3432292SN/A    instQueue.setActiveThreads(at_ptr);
3441060SN/A}
3451060SN/A
3461681SN/Atemplate<class Impl>
3471060SN/Avoid
3482292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
3491060SN/A{
3502292SN/A    DPRINTF(IEW, "Setting scoreboard pointer.\n");
3512292SN/A    scoreboard = sb_ptr;
3521060SN/A}
3531060SN/A
3542307SN/Atemplate <class Impl>
3552863Sktlim@umich.edubool
3562843Sktlim@umich.eduDefaultIEW<Impl>::drain()
3572307SN/A{
3582843Sktlim@umich.edu    // IEW is ready to drain at any time.
3592843Sktlim@umich.edu    cpu->signalDrained();
3602863Sktlim@umich.edu    return true;
3611681SN/A}
3621681SN/A
3632316SN/Atemplate <class Impl>
3641681SN/Avoid
3652843Sktlim@umich.eduDefaultIEW<Impl>::resume()
3662843Sktlim@umich.edu{
3672843Sktlim@umich.edu}
3682843Sktlim@umich.edu
3692843Sktlim@umich.edutemplate <class Impl>
3702843Sktlim@umich.eduvoid
3712843Sktlim@umich.eduDefaultIEW<Impl>::switchOut()
3721681SN/A{
3732348SN/A    // Clear any state.
3742307SN/A    switchedOut = true;
3752367SN/A    assert(insts[0].empty());
3762367SN/A    assert(skidBuffer[0].empty());
3771681SN/A
3782307SN/A    instQueue.switchOut();
3792307SN/A    ldstQueue.switchOut();
3802307SN/A    fuPool->switchOut();
3812307SN/A
3822307SN/A    for (int i = 0; i < numThreads; i++) {
3832307SN/A        while (!insts[i].empty())
3842307SN/A            insts[i].pop();
3852307SN/A        while (!skidBuffer[i].empty())
3862307SN/A            skidBuffer[i].pop();
3872307SN/A    }
3881681SN/A}
3891681SN/A
3902307SN/Atemplate <class Impl>
3911681SN/Avoid
3922307SN/ADefaultIEW<Impl>::takeOverFrom()
3931060SN/A{
3942348SN/A    // Reset all state.
3952307SN/A    _status = Active;
3962307SN/A    exeStatus = Running;
3972307SN/A    wbStatus = Idle;
3982307SN/A    switchedOut = false;
3991060SN/A
4002307SN/A    instQueue.takeOverFrom();
4012307SN/A    ldstQueue.takeOverFrom();
4022307SN/A    fuPool->takeOverFrom();
4031060SN/A
4042307SN/A    initStage();
4052307SN/A    cpu->activityThisCycle();
4061060SN/A
4072307SN/A    for (int i=0; i < numThreads; i++) {
4082307SN/A        dispatchStatus[i] = Running;
4092307SN/A        stalls[i].commit = false;
4102307SN/A        fetchRedirect[i] = false;
4112307SN/A    }
4121060SN/A
4132307SN/A    updateLSQNextCycle = false;
4142307SN/A
4152873Sktlim@umich.edu    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
4162307SN/A        issueToExecQueue.advance();
4171060SN/A    }
4181060SN/A}
4191060SN/A
4201681SN/Atemplate<class Impl>
4211060SN/Avoid
4222292SN/ADefaultIEW<Impl>::squash(unsigned tid)
4232107SN/A{
4242292SN/A    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
4252292SN/A            tid);
4262107SN/A
4272292SN/A    // Tell the IQ to start squashing.
4282292SN/A    instQueue.squash(tid);
4292107SN/A
4302292SN/A    // Tell the LDSTQ to start squashing.
4313093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
4323093Sksewell@umich.edu    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
4333093Sksewell@umich.edu#else
4342326SN/A    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
4352935Sksewell@umich.edu#endif
4362292SN/A    updatedQueues = true;
4372107SN/A
4382292SN/A    // Clear the skid buffer in case it has any data in it.
4392935Sksewell@umich.edu    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
4402935Sksewell@umich.edu            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
4412935Sksewell@umich.edu
4422292SN/A    while (!skidBuffer[tid].empty()) {
4433093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
4442935Sksewell@umich.edu        if (skidBuffer[tid].front()->seqNum <=
4452935Sksewell@umich.edu            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
4462935Sksewell@umich.edu            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
4472935Sksewell@umich.edu                    "that occur before delay slot [sn:%i].\n",
4482935Sksewell@umich.edu                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
4492935Sksewell@umich.edu                    tid);
4502935Sksewell@umich.edu            break;
4512935Sksewell@umich.edu        } else {
4522935Sksewell@umich.edu            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
4532935Sksewell@umich.edu                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
4542935Sksewell@umich.edu        }
4552935Sksewell@umich.edu#endif
4562292SN/A        if (skidBuffer[tid].front()->isLoad() ||
4572292SN/A            skidBuffer[tid].front()->isStore() ) {
4582292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
4592292SN/A        }
4602107SN/A
4612292SN/A        toRename->iewInfo[tid].dispatched++;
4622107SN/A
4632292SN/A        skidBuffer[tid].pop();
4642292SN/A    }
4652107SN/A
4662935Sksewell@umich.edu    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
4672935Sksewell@umich.edu
4682702Sktlim@umich.edu    emptyRenameInsts(tid);
4692107SN/A}
4702107SN/A
4712107SN/Atemplate<class Impl>
4722107SN/Avoid
4732292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
4742292SN/A{
4752292SN/A    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
4762292SN/A            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
4772292SN/A
4782292SN/A    toCommit->squash[tid] = true;
4792292SN/A    toCommit->squashedSeqNum[tid] = inst->seqNum;
4802292SN/A    toCommit->mispredPC[tid] = inst->readPC();
4812292SN/A    toCommit->branchMispredict[tid] = true;
4822935Sksewell@umich.edu
4833093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
4842935Sksewell@umich.edu    bool branch_taken = inst->readNextNPC() !=
4852935Sksewell@umich.edu        (inst->readNextPC() + sizeof(TheISA::MachInst));
4862935Sksewell@umich.edu
4872935Sksewell@umich.edu    toCommit->branchTaken[tid] = branch_taken;
4882935Sksewell@umich.edu
4892935Sksewell@umich.edu    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
4902935Sksewell@umich.edu
4912935Sksewell@umich.edu    if (inst->isCondDelaySlot() && branch_taken) {
4922935Sksewell@umich.edu        toCommit->nextPC[tid] = inst->readNextPC();
4932935Sksewell@umich.edu    } else {
4942935Sksewell@umich.edu        toCommit->nextPC[tid] = inst->readNextNPC();
4952935Sksewell@umich.edu    }
4963093Sksewell@umich.edu#else
4973093Sksewell@umich.edu    toCommit->branchTaken[tid] = inst->readNextPC() !=
4983093Sksewell@umich.edu        (inst->readPC() + sizeof(TheISA::MachInst));
4993093Sksewell@umich.edu    toCommit->nextPC[tid] = inst->readNextPC();
5002935Sksewell@umich.edu#endif
5012292SN/A
5022292SN/A    toCommit->includeSquashInst[tid] = false;
5032292SN/A
5042292SN/A    wroteToTimeBuffer = true;
5052292SN/A}
5062292SN/A
5072292SN/Atemplate<class Impl>
5082292SN/Avoid
5092292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
5102292SN/A{
5112292SN/A    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
5122292SN/A            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
5132292SN/A
5142292SN/A    toCommit->squash[tid] = true;
5152292SN/A    toCommit->squashedSeqNum[tid] = inst->seqNum;
5162292SN/A    toCommit->nextPC[tid] = inst->readNextPC();
5173732Sktlim@umich.edu    toCommit->branchMispredict[tid] = false;
5182292SN/A
5192292SN/A    toCommit->includeSquashInst[tid] = false;
5202292SN/A
5212292SN/A    wroteToTimeBuffer = true;
5222292SN/A}
5232292SN/A
5242292SN/Atemplate<class Impl>
5252292SN/Avoid
5262292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
5272292SN/A{
5282292SN/A    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
5292292SN/A            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
5302292SN/A
5312292SN/A    toCommit->squash[tid] = true;
5322292SN/A    toCommit->squashedSeqNum[tid] = inst->seqNum;
5332292SN/A    toCommit->nextPC[tid] = inst->readPC();
5343732Sktlim@umich.edu    toCommit->branchMispredict[tid] = false;
5352292SN/A
5362348SN/A    // Must include the broadcasted SN in the squash.
5372292SN/A    toCommit->includeSquashInst[tid] = true;
5382292SN/A
5392292SN/A    ldstQueue.setLoadBlockedHandled(tid);
5402292SN/A
5412292SN/A    wroteToTimeBuffer = true;
5422292SN/A}
5432292SN/A
5442292SN/Atemplate<class Impl>
5452292SN/Avoid
5462292SN/ADefaultIEW<Impl>::block(unsigned tid)
5472292SN/A{
5482292SN/A    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
5492292SN/A
5502292SN/A    if (dispatchStatus[tid] != Blocked &&
5512292SN/A        dispatchStatus[tid] != Unblocking) {
5522292SN/A        toRename->iewBlock[tid] = true;
5532292SN/A        wroteToTimeBuffer = true;
5542292SN/A    }
5552292SN/A
5562292SN/A    // Add the current inputs to the skid buffer so they can be
5572292SN/A    // reprocessed when this stage unblocks.
5582292SN/A    skidInsert(tid);
5592292SN/A
5602292SN/A    dispatchStatus[tid] = Blocked;
5612292SN/A}
5622292SN/A
5632292SN/Atemplate<class Impl>
5642292SN/Avoid
5652292SN/ADefaultIEW<Impl>::unblock(unsigned tid)
5662292SN/A{
5672292SN/A    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
5682292SN/A            "buffer %u.\n",tid, tid);
5692292SN/A
5702292SN/A    // If the skid bufffer is empty, signal back to previous stages to unblock.
5712292SN/A    // Also switch status to running.
5722292SN/A    if (skidBuffer[tid].empty()) {
5732292SN/A        toRename->iewUnblock[tid] = true;
5742292SN/A        wroteToTimeBuffer = true;
5752292SN/A        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
5762292SN/A        dispatchStatus[tid] = Running;
5772292SN/A    }
5782292SN/A}
5792292SN/A
5802292SN/Atemplate<class Impl>
5812292SN/Avoid
5822292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
5831060SN/A{
5841681SN/A    instQueue.wakeDependents(inst);
5851060SN/A}
5861060SN/A
5872292SN/Atemplate<class Impl>
5882292SN/Avoid
5892292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
5902292SN/A{
5912292SN/A    instQueue.rescheduleMemInst(inst);
5922292SN/A}
5931681SN/A
5941681SN/Atemplate<class Impl>
5951060SN/Avoid
5962292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
5971060SN/A{
5982292SN/A    instQueue.replayMemInst(inst);
5992292SN/A}
6001060SN/A
6012292SN/Atemplate<class Impl>
6022292SN/Avoid
6032292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
6042292SN/A{
6053221Sktlim@umich.edu    // This function should not be called after writebackInsts in a
6063221Sktlim@umich.edu    // single cycle.  That will cause problems with an instruction
6073221Sktlim@umich.edu    // being added to the queue to commit without being processed by
6083221Sktlim@umich.edu    // writebackInsts prior to being sent to commit.
6093221Sktlim@umich.edu
6102292SN/A    // First check the time slot that this instruction will write
6112292SN/A    // to.  If there are free write ports at the time, then go ahead
6122292SN/A    // and write the instruction to that time.  If there are not,
6132292SN/A    // keep looking back to see where's the first time there's a
6142326SN/A    // free slot.
6152292SN/A    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
6162292SN/A        ++wbNumInst;
6172820Sktlim@umich.edu        if (wbNumInst == wbWidth) {
6182292SN/A            ++wbCycle;
6192292SN/A            wbNumInst = 0;
6202292SN/A        }
6212292SN/A
6222353SN/A        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
6232292SN/A    }
6242292SN/A
6252353SN/A    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
6262353SN/A            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
6272292SN/A    // Add finished instruction to queue to commit.
6282292SN/A    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
6292292SN/A    (*iewQueue)[wbCycle].size++;
6302292SN/A}
6312292SN/A
6322292SN/Atemplate <class Impl>
6332292SN/Aunsigned
6342292SN/ADefaultIEW<Impl>::validInstsFromRename()
6352292SN/A{
6362292SN/A    unsigned inst_count = 0;
6372292SN/A
6382292SN/A    for (int i=0; i<fromRename->size; i++) {
6392731Sktlim@umich.edu        if (!fromRename->insts[i]->isSquashed())
6402292SN/A            inst_count++;
6412292SN/A    }
6422292SN/A
6432292SN/A    return inst_count;
6442292SN/A}
6452292SN/A
6462292SN/Atemplate<class Impl>
6472292SN/Avoid
6482292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid)
6492292SN/A{
6502292SN/A    DynInstPtr inst = NULL;
6512292SN/A
6522292SN/A    while (!insts[tid].empty()) {
6532292SN/A        inst = insts[tid].front();
6542292SN/A
6552292SN/A        insts[tid].pop();
6562292SN/A
6572292SN/A        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
6582292SN/A                "dispatch skidBuffer %i\n",tid, inst->seqNum,
6592292SN/A                inst->readPC(),tid);
6602292SN/A
6612292SN/A        skidBuffer[tid].push(inst);
6622292SN/A    }
6632292SN/A
6642292SN/A    assert(skidBuffer[tid].size() <= skidBufferMax &&
6652292SN/A           "Skidbuffer Exceeded Max Size");
6662292SN/A}
6672292SN/A
6682292SN/Atemplate<class Impl>
6692292SN/Aint
6702292SN/ADefaultIEW<Impl>::skidCount()
6712292SN/A{
6722292SN/A    int max=0;
6732292SN/A
6743867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
6753867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
6762292SN/A
6773867Sbinkertn@umich.edu    while (threads != end) {
6783867Sbinkertn@umich.edu        unsigned tid = *threads++;
6793867Sbinkertn@umich.edu        unsigned thread_count = skidBuffer[tid].size();
6802292SN/A        if (max < thread_count)
6812292SN/A            max = thread_count;
6822292SN/A    }
6832292SN/A
6842292SN/A    return max;
6852292SN/A}
6862292SN/A
6872292SN/Atemplate<class Impl>
6882292SN/Abool
6892292SN/ADefaultIEW<Impl>::skidsEmpty()
6902292SN/A{
6913867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
6923867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
6932292SN/A
6943867Sbinkertn@umich.edu    while (threads != end) {
6953867Sbinkertn@umich.edu        unsigned tid = *threads++;
6963867Sbinkertn@umich.edu
6973867Sbinkertn@umich.edu        if (!skidBuffer[tid].empty())
6982292SN/A            return false;
6992292SN/A    }
7002292SN/A
7012292SN/A    return true;
7021062SN/A}
7031062SN/A
7041681SN/Atemplate <class Impl>
7051062SN/Avoid
7062292SN/ADefaultIEW<Impl>::updateStatus()
7071062SN/A{
7082292SN/A    bool any_unblocking = false;
7091062SN/A
7103867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
7113867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
7121062SN/A
7133867Sbinkertn@umich.edu    while (threads != end) {
7142292SN/A        unsigned tid = *threads++;
7151062SN/A
7162292SN/A        if (dispatchStatus[tid] == Unblocking) {
7172292SN/A            any_unblocking = true;
7182292SN/A            break;
7192292SN/A        }
7202292SN/A    }
7211062SN/A
7222292SN/A    // If there are no ready instructions waiting to be scheduled by the IQ,
7232292SN/A    // and there's no stores waiting to write back, and dispatch is not
7242292SN/A    // unblocking, then there is no internal activity for the IEW stage.
7252292SN/A    if (_status == Active && !instQueue.hasReadyInsts() &&
7262292SN/A        !ldstQueue.willWB() && !any_unblocking) {
7272292SN/A        DPRINTF(IEW, "IEW switching to idle\n");
7281062SN/A
7292292SN/A        deactivateStage();
7301062SN/A
7312292SN/A        _status = Inactive;
7322292SN/A    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
7332292SN/A                                       ldstQueue.willWB() ||
7342292SN/A                                       any_unblocking)) {
7352292SN/A        // Otherwise there is internal activity.  Set to active.
7362292SN/A        DPRINTF(IEW, "IEW switching to active\n");
7371062SN/A
7382292SN/A        activateStage();
7391062SN/A
7402292SN/A        _status = Active;
7411062SN/A    }
7421062SN/A}
7431062SN/A
7441681SN/Atemplate <class Impl>
7451062SN/Avoid
7462292SN/ADefaultIEW<Impl>::resetEntries()
7471062SN/A{
7482292SN/A    instQueue.resetEntries();
7492292SN/A    ldstQueue.resetEntries();
7502292SN/A}
7511062SN/A
7522292SN/Atemplate <class Impl>
7532292SN/Avoid
7542292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid)
7552292SN/A{
7562292SN/A    if (fromCommit->commitBlock[tid]) {
7572292SN/A        stalls[tid].commit = true;
7582292SN/A    }
7591062SN/A
7602292SN/A    if (fromCommit->commitUnblock[tid]) {
7612292SN/A        assert(stalls[tid].commit);
7622292SN/A        stalls[tid].commit = false;
7632292SN/A    }
7642292SN/A}
7652292SN/A
7662292SN/Atemplate <class Impl>
7672292SN/Abool
7682292SN/ADefaultIEW<Impl>::checkStall(unsigned tid)
7692292SN/A{
7702292SN/A    bool ret_val(false);
7712292SN/A
7722292SN/A    if (stalls[tid].commit) {
7732292SN/A        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
7742292SN/A        ret_val = true;
7752292SN/A    } else if (instQueue.isFull(tid)) {
7762292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
7772292SN/A        ret_val = true;
7782292SN/A    } else if (ldstQueue.isFull(tid)) {
7792292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
7802292SN/A
7812292SN/A        if (ldstQueue.numLoads(tid) > 0 ) {
7822292SN/A
7832292SN/A            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
7842292SN/A                    tid,ldstQueue.getLoadHeadSeqNum(tid));
7852292SN/A        }
7862292SN/A
7872292SN/A        if (ldstQueue.numStores(tid) > 0) {
7882292SN/A
7892292SN/A            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
7902292SN/A                    tid,ldstQueue.getStoreHeadSeqNum(tid));
7912292SN/A        }
7922292SN/A
7932292SN/A        ret_val = true;
7942292SN/A    } else if (ldstQueue.isStalled(tid)) {
7952292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
7962292SN/A        ret_val = true;
7972292SN/A    }
7982292SN/A
7992292SN/A    return ret_val;
8002292SN/A}
8012292SN/A
8022292SN/Atemplate <class Impl>
8032292SN/Avoid
8042292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
8052292SN/A{
8062292SN/A    // Check if there's a squash signal, squash if there is
8072292SN/A    // Check stall signals, block if there is.
8082292SN/A    // If status was Blocked
8092292SN/A    //     if so then go to unblocking
8102292SN/A    // If status was Squashing
8112292SN/A    //     check if squashing is not high.  Switch to running this cycle.
8122292SN/A
8132292SN/A    readStallSignals(tid);
8142292SN/A
8152292SN/A    if (fromCommit->commitInfo[tid].squash) {
8162292SN/A        squash(tid);
8172292SN/A
8182292SN/A        if (dispatchStatus[tid] == Blocked ||
8192292SN/A            dispatchStatus[tid] == Unblocking) {
8202292SN/A            toRename->iewUnblock[tid] = true;
8212292SN/A            wroteToTimeBuffer = true;
8222292SN/A        }
8232292SN/A
8242292SN/A        dispatchStatus[tid] = Squashing;
8252292SN/A
8262292SN/A        fetchRedirect[tid] = false;
8272292SN/A        return;
8282292SN/A    }
8292292SN/A
8302292SN/A    if (fromCommit->commitInfo[tid].robSquashing) {
8312702Sktlim@umich.edu        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
8322292SN/A
8332292SN/A        dispatchStatus[tid] = Squashing;
8342292SN/A
8352702Sktlim@umich.edu        emptyRenameInsts(tid);
8362702Sktlim@umich.edu        wroteToTimeBuffer = true;
8372292SN/A        return;
8382292SN/A    }
8392292SN/A
8402292SN/A    if (checkStall(tid)) {
8412292SN/A        block(tid);
8422292SN/A        dispatchStatus[tid] = Blocked;
8432292SN/A        return;
8442292SN/A    }
8452292SN/A
8462292SN/A    if (dispatchStatus[tid] == Blocked) {
8472292SN/A        // Status from previous cycle was blocked, but there are no more stall
8482292SN/A        // conditions.  Switch over to unblocking.
8492292SN/A        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
8502292SN/A                tid);
8512292SN/A
8522292SN/A        dispatchStatus[tid] = Unblocking;
8532292SN/A
8542292SN/A        unblock(tid);
8552292SN/A
8562292SN/A        return;
8572292SN/A    }
8582292SN/A
8592292SN/A    if (dispatchStatus[tid] == Squashing) {
8602292SN/A        // Switch status to running if rename isn't being told to block or
8612292SN/A        // squash this cycle.
8622292SN/A        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
8632292SN/A                tid);
8642292SN/A
8652292SN/A        dispatchStatus[tid] = Running;
8662292SN/A
8672292SN/A        return;
8682292SN/A    }
8692292SN/A}
8702292SN/A
8712292SN/Atemplate <class Impl>
8722292SN/Avoid
8732292SN/ADefaultIEW<Impl>::sortInsts()
8742292SN/A{
8752292SN/A    int insts_from_rename = fromRename->size;
8762326SN/A#ifdef DEBUG
8773093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT
8782292SN/A    for (int i = 0; i < numThreads; i++)
8792292SN/A        assert(insts[i].empty());
8802326SN/A#endif
8812935Sksewell@umich.edu#endif
8822292SN/A    for (int i = 0; i < insts_from_rename; ++i) {
8832292SN/A        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
8842292SN/A    }
8852292SN/A}
8862292SN/A
8872292SN/Atemplate <class Impl>
8882292SN/Avoid
8892702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
8902702Sktlim@umich.edu{
8912935Sksewell@umich.edu    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
8922935Sksewell@umich.edu            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
8932935Sksewell@umich.edu
8942702Sktlim@umich.edu    while (!insts[tid].empty()) {
8953093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
8962935Sksewell@umich.edu        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
8972935Sksewell@umich.edu            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
8982935Sksewell@umich.edu                    " that occurs at or before delay slot [sn:%i].\n",
8992935Sksewell@umich.edu                    tid, bdelayDoneSeqNum[tid]);
9002935Sksewell@umich.edu            break;
9012935Sksewell@umich.edu        } else {
9022935Sksewell@umich.edu            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
9032935Sksewell@umich.edu                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
9042935Sksewell@umich.edu        }
9052935Sksewell@umich.edu#endif
9062935Sksewell@umich.edu
9072702Sktlim@umich.edu        if (insts[tid].front()->isLoad() ||
9082702Sktlim@umich.edu            insts[tid].front()->isStore() ) {
9092702Sktlim@umich.edu            toRename->iewInfo[tid].dispatchedToLSQ++;
9102702Sktlim@umich.edu        }
9112702Sktlim@umich.edu
9122702Sktlim@umich.edu        toRename->iewInfo[tid].dispatched++;
9132702Sktlim@umich.edu
9142702Sktlim@umich.edu        insts[tid].pop();
9152702Sktlim@umich.edu    }
9162702Sktlim@umich.edu}
9172702Sktlim@umich.edu
9182702Sktlim@umich.edutemplate <class Impl>
9192702Sktlim@umich.eduvoid
9202292SN/ADefaultIEW<Impl>::wakeCPU()
9212292SN/A{
9222292SN/A    cpu->wakeCPU();
9232292SN/A}
9242292SN/A
9252292SN/Atemplate <class Impl>
9262292SN/Avoid
9272292SN/ADefaultIEW<Impl>::activityThisCycle()
9282292SN/A{
9292292SN/A    DPRINTF(Activity, "Activity this cycle.\n");
9302292SN/A    cpu->activityThisCycle();
9312292SN/A}
9322292SN/A
9332292SN/Atemplate <class Impl>
9342292SN/Ainline void
9352292SN/ADefaultIEW<Impl>::activateStage()
9362292SN/A{
9372292SN/A    DPRINTF(Activity, "Activating stage.\n");
9382733Sktlim@umich.edu    cpu->activateStage(O3CPU::IEWIdx);
9392292SN/A}
9402292SN/A
9412292SN/Atemplate <class Impl>
9422292SN/Ainline void
9432292SN/ADefaultIEW<Impl>::deactivateStage()
9442292SN/A{
9452292SN/A    DPRINTF(Activity, "Deactivating stage.\n");
9462733Sktlim@umich.edu    cpu->deactivateStage(O3CPU::IEWIdx);
9472292SN/A}
9482292SN/A
9492292SN/Atemplate<class Impl>
9502292SN/Avoid
9512292SN/ADefaultIEW<Impl>::dispatch(unsigned tid)
9522292SN/A{
9532292SN/A    // If status is Running or idle,
9542292SN/A    //     call dispatchInsts()
9552292SN/A    // If status is Unblocking,
9562292SN/A    //     buffer any instructions coming from rename
9572292SN/A    //     continue trying to empty skid buffer
9582292SN/A    //     check if stall conditions have passed
9592292SN/A
9602292SN/A    if (dispatchStatus[tid] == Blocked) {
9612292SN/A        ++iewBlockCycles;
9622292SN/A
9632292SN/A    } else if (dispatchStatus[tid] == Squashing) {
9642292SN/A        ++iewSquashCycles;
9652292SN/A    }
9662292SN/A
9672292SN/A    // Dispatch should try to dispatch as many instructions as its bandwidth
9682292SN/A    // will allow, as long as it is not currently blocked.
9692292SN/A    if (dispatchStatus[tid] == Running ||
9702292SN/A        dispatchStatus[tid] == Idle) {
9712292SN/A        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
9722292SN/A                "dispatch.\n", tid);
9732292SN/A
9742292SN/A        dispatchInsts(tid);
9752292SN/A    } else if (dispatchStatus[tid] == Unblocking) {
9762292SN/A        // Make sure that the skid buffer has something in it if the
9772292SN/A        // status is unblocking.
9782292SN/A        assert(!skidsEmpty());
9792292SN/A
9802292SN/A        // If the status was unblocking, then instructions from the skid
9812292SN/A        // buffer were used.  Remove those instructions and handle
9822292SN/A        // the rest of unblocking.
9832292SN/A        dispatchInsts(tid);
9842292SN/A
9852292SN/A        ++iewUnblockCycles;
9862292SN/A
9872292SN/A        if (validInstsFromRename() && dispatchedAllInsts) {
9882292SN/A            // Add the current inputs to the skid buffer so they can be
9892292SN/A            // reprocessed when this stage unblocks.
9902292SN/A            skidInsert(tid);
9912292SN/A        }
9922292SN/A
9932292SN/A        unblock(tid);
9942292SN/A    }
9952292SN/A}
9962292SN/A
9972292SN/Atemplate <class Impl>
9982292SN/Avoid
9992292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid)
10002292SN/A{
10012292SN/A    dispatchedAllInsts = true;
10022292SN/A
10032292SN/A    // Obtain instructions from skid buffer if unblocking, or queue from rename
10042292SN/A    // otherwise.
10052292SN/A    std::queue<DynInstPtr> &insts_to_dispatch =
10062292SN/A        dispatchStatus[tid] == Unblocking ?
10072292SN/A        skidBuffer[tid] : insts[tid];
10082292SN/A
10092292SN/A    int insts_to_add = insts_to_dispatch.size();
10102292SN/A
10112292SN/A    DynInstPtr inst;
10122292SN/A    bool add_to_iq = false;
10132292SN/A    int dis_num_inst = 0;
10142292SN/A
10152292SN/A    // Loop through the instructions, putting them in the instruction
10162292SN/A    // queue.
10172292SN/A    for ( ; dis_num_inst < insts_to_add &&
10182820Sktlim@umich.edu              dis_num_inst < dispatchWidth;
10192292SN/A          ++dis_num_inst)
10202292SN/A    {
10212292SN/A        inst = insts_to_dispatch.front();
10222292SN/A
10232292SN/A        if (dispatchStatus[tid] == Unblocking) {
10242292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
10252292SN/A                    "buffer\n", tid);
10262292SN/A        }
10272292SN/A
10282292SN/A        // Make sure there's a valid instruction there.
10292292SN/A        assert(inst);
10302292SN/A
10312292SN/A        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
10322292SN/A                "IQ.\n",
10332292SN/A                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
10342292SN/A
10352292SN/A        // Be sure to mark these instructions as ready so that the
10362292SN/A        // commit stage can go ahead and execute them, and mark
10372292SN/A        // them as issued so the IQ doesn't reprocess them.
10382292SN/A
10392292SN/A        // Check for squashed instructions.
10402292SN/A        if (inst->isSquashed()) {
10412292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
10422292SN/A                    "not adding to IQ.\n", tid);
10432292SN/A
10442292SN/A            ++iewDispSquashedInsts;
10452292SN/A
10462292SN/A            insts_to_dispatch.pop();
10472292SN/A
10482292SN/A            //Tell Rename That An Instruction has been processed
10492292SN/A            if (inst->isLoad() || inst->isStore()) {
10502292SN/A                toRename->iewInfo[tid].dispatchedToLSQ++;
10512292SN/A            }
10522292SN/A            toRename->iewInfo[tid].dispatched++;
10532292SN/A
10542292SN/A            continue;
10552292SN/A        }
10562292SN/A
10572292SN/A        // Check for full conditions.
10582292SN/A        if (instQueue.isFull(tid)) {
10592292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
10602292SN/A
10612292SN/A            // Call function to start blocking.
10622292SN/A            block(tid);
10632292SN/A
10642292SN/A            // Set unblock to false. Special case where we are using
10652292SN/A            // skidbuffer (unblocking) instructions but then we still
10662292SN/A            // get full in the IQ.
10672292SN/A            toRename->iewUnblock[tid] = false;
10682292SN/A
10692292SN/A            dispatchedAllInsts = false;
10702292SN/A
10712292SN/A            ++iewIQFullEvents;
10722292SN/A            break;
10732292SN/A        } else if (ldstQueue.isFull(tid)) {
10742292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
10752292SN/A
10762292SN/A            // Call function to start blocking.
10772292SN/A            block(tid);
10782292SN/A
10792292SN/A            // Set unblock to false. Special case where we are using
10802292SN/A            // skidbuffer (unblocking) instructions but then we still
10812292SN/A            // get full in the IQ.
10822292SN/A            toRename->iewUnblock[tid] = false;
10832292SN/A
10842292SN/A            dispatchedAllInsts = false;
10852292SN/A
10862292SN/A            ++iewLSQFullEvents;
10872292SN/A            break;
10882292SN/A        }
10892292SN/A
10902292SN/A        // Otherwise issue the instruction just fine.
10912292SN/A        if (inst->isLoad()) {
10922292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
10932292SN/A                    "encountered, adding to LSQ.\n", tid);
10942292SN/A
10952292SN/A            // Reserve a spot in the load store queue for this
10962292SN/A            // memory access.
10972292SN/A            ldstQueue.insertLoad(inst);
10982292SN/A
10992292SN/A            ++iewDispLoadInsts;
11002292SN/A
11012292SN/A            add_to_iq = true;
11022292SN/A
11032292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
11042292SN/A        } else if (inst->isStore()) {
11052292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
11062292SN/A                    "encountered, adding to LSQ.\n", tid);
11072292SN/A
11082292SN/A            ldstQueue.insertStore(inst);
11092292SN/A
11102292SN/A            ++iewDispStoreInsts;
11112292SN/A
11122336SN/A            if (inst->isStoreConditional()) {
11132336SN/A                // Store conditionals need to be set as "canCommit()"
11142336SN/A                // so that commit can process them when they reach the
11152336SN/A                // head of commit.
11162348SN/A                // @todo: This is somewhat specific to Alpha.
11172292SN/A                inst->setCanCommit();
11182292SN/A                instQueue.insertNonSpec(inst);
11192292SN/A                add_to_iq = false;
11202292SN/A
11212292SN/A                ++iewDispNonSpecInsts;
11222292SN/A            } else {
11232292SN/A                add_to_iq = true;
11242292SN/A            }
11252292SN/A
11262292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
11272292SN/A#if FULL_SYSTEM
11282292SN/A        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
11292326SN/A            // Same as non-speculative stores.
11302292SN/A            inst->setCanCommit();
11312292SN/A            instQueue.insertBarrier(inst);
11322292SN/A            add_to_iq = false;
11332292SN/A#endif
11342292SN/A        } else if (inst->isNonSpeculative()) {
11352292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
11362292SN/A                    "encountered, skipping.\n", tid);
11372292SN/A
11382326SN/A            // Same as non-speculative stores.
11392292SN/A            inst->setCanCommit();
11402292SN/A
11412292SN/A            // Specifically insert it as nonspeculative.
11422292SN/A            instQueue.insertNonSpec(inst);
11432292SN/A
11442292SN/A            ++iewDispNonSpecInsts;
11452292SN/A
11462292SN/A            add_to_iq = false;
11472292SN/A        } else if (inst->isNop()) {
11482292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
11492292SN/A                    "skipping.\n", tid);
11502292SN/A
11512292SN/A            inst->setIssued();
11522292SN/A            inst->setExecuted();
11532292SN/A            inst->setCanCommit();
11542292SN/A
11552326SN/A            instQueue.recordProducer(inst);
11562292SN/A
11572727Sktlim@umich.edu            iewExecutedNop[tid]++;
11582301SN/A
11592292SN/A            add_to_iq = false;
11602292SN/A        } else if (inst->isExecuted()) {
11612292SN/A            assert(0 && "Instruction shouldn't be executed.\n");
11622292SN/A            DPRINTF(IEW, "Issue: Executed branch encountered, "
11632292SN/A                    "skipping.\n");
11642292SN/A
11652292SN/A            inst->setIssued();
11662292SN/A            inst->setCanCommit();
11672292SN/A
11682326SN/A            instQueue.recordProducer(inst);
11692292SN/A
11702292SN/A            add_to_iq = false;
11712292SN/A        } else {
11722292SN/A            add_to_iq = true;
11732292SN/A        }
11742292SN/A
11752292SN/A        // If the instruction queue is not full, then add the
11762292SN/A        // instruction.
11772292SN/A        if (add_to_iq) {
11782292SN/A            instQueue.insert(inst);
11792292SN/A        }
11802292SN/A
11812292SN/A        insts_to_dispatch.pop();
11822292SN/A
11832292SN/A        toRename->iewInfo[tid].dispatched++;
11842292SN/A
11852292SN/A        ++iewDispatchedInsts;
11862292SN/A    }
11872292SN/A
11882292SN/A    if (!insts_to_dispatch.empty()) {
11892935Sksewell@umich.edu        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
11902292SN/A        block(tid);
11912292SN/A        toRename->iewUnblock[tid] = false;
11922292SN/A    }
11932292SN/A
11942292SN/A    if (dispatchStatus[tid] == Idle && dis_num_inst) {
11952292SN/A        dispatchStatus[tid] = Running;
11962292SN/A
11972292SN/A        updatedQueues = true;
11982292SN/A    }
11992292SN/A
12002292SN/A    dis_num_inst = 0;
12012292SN/A}
12022292SN/A
12032292SN/Atemplate <class Impl>
12042292SN/Avoid
12052292SN/ADefaultIEW<Impl>::printAvailableInsts()
12062292SN/A{
12072292SN/A    int inst = 0;
12082292SN/A
12092980Sgblack@eecs.umich.edu    std::cout << "Available Instructions: ";
12102292SN/A
12112292SN/A    while (fromIssue->insts[inst]) {
12122292SN/A
12132980Sgblack@eecs.umich.edu        if (inst%3==0) std::cout << "\n\t";
12142292SN/A
12152980Sgblack@eecs.umich.edu        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
12162292SN/A             << " TN: " << fromIssue->insts[inst]->threadNumber
12172292SN/A             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
12182292SN/A
12192292SN/A        inst++;
12202292SN/A
12212292SN/A    }
12222292SN/A
12232980Sgblack@eecs.umich.edu    std::cout << "\n";
12242292SN/A}
12252292SN/A
12262292SN/Atemplate <class Impl>
12272292SN/Avoid
12282292SN/ADefaultIEW<Impl>::executeInsts()
12292292SN/A{
12302292SN/A    wbNumInst = 0;
12312292SN/A    wbCycle = 0;
12322292SN/A
12333867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
12343867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
12352292SN/A
12363867Sbinkertn@umich.edu    while (threads != end) {
12372292SN/A        unsigned tid = *threads++;
12382292SN/A        fetchRedirect[tid] = false;
12392292SN/A    }
12402292SN/A
12412698Sktlim@umich.edu    // Uncomment this if you want to see all available instructions.
12422698Sktlim@umich.edu//    printAvailableInsts();
12431062SN/A
12441062SN/A    // Execute/writeback any instructions that are available.
12452333SN/A    int insts_to_execute = fromIssue->size;
12462292SN/A    int inst_num = 0;
12472333SN/A    for (; inst_num < insts_to_execute;
12482326SN/A          ++inst_num) {
12491062SN/A
12502292SN/A        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
12511062SN/A
12522333SN/A        DynInstPtr inst = instQueue.getInstToExecute();
12531062SN/A
12542292SN/A        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
12552292SN/A                inst->readPC(), inst->threadNumber,inst->seqNum);
12561062SN/A
12571062SN/A        // Check if the instruction is squashed; if so then skip it
12581062SN/A        if (inst->isSquashed()) {
12592292SN/A            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
12601062SN/A
12611062SN/A            // Consider this instruction executed so that commit can go
12621062SN/A            // ahead and retire the instruction.
12631062SN/A            inst->setExecuted();
12641062SN/A
12652292SN/A            // Not sure if I should set this here or just let commit try to
12662292SN/A            // commit any squashed instructions.  I like the latter a bit more.
12672292SN/A            inst->setCanCommit();
12681062SN/A
12691062SN/A            ++iewExecSquashedInsts;
12701062SN/A
12712820Sktlim@umich.edu            decrWb(inst->seqNum);
12721062SN/A            continue;
12731062SN/A        }
12741062SN/A
12752292SN/A        Fault fault = NoFault;
12761062SN/A
12771062SN/A        // Execute instruction.
12781062SN/A        // Note that if the instruction faults, it will be handled
12791062SN/A        // at the commit stage.
12802292SN/A        if (inst->isMemRef() &&
12812292SN/A            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
12822292SN/A            DPRINTF(IEW, "Execute: Calculating address for memory "
12831062SN/A                    "reference.\n");
12841062SN/A
12851062SN/A            // Tell the LDSTQ to execute this instruction (if it is a load).
12861062SN/A            if (inst->isLoad()) {
12872292SN/A                // Loads will mark themselves as executed, and their writeback
12882292SN/A                // event adds the instruction to the queue to commit
12892292SN/A                fault = ldstQueue.executeLoad(inst);
12901062SN/A            } else if (inst->isStore()) {
12912367SN/A                fault = ldstQueue.executeStore(inst);
12921062SN/A
12932292SN/A                // If the store had a fault then it may not have a mem req
12942367SN/A                if (!inst->isStoreConditional() && fault == NoFault) {
12952292SN/A                    inst->setExecuted();
12962292SN/A
12972292SN/A                    instToCommit(inst);
12982367SN/A                } else if (fault != NoFault) {
12992367SN/A                    // If the instruction faulted, then we need to send it along to commit
13002367SN/A                    // without the instruction completing.
13013732Sktlim@umich.edu                    DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
13023732Sktlim@umich.edu                            fault->name(), inst->seqNum);
13032367SN/A
13042367SN/A                    // Send this instruction to commit, also make sure iew stage
13052367SN/A                    // realizes there is activity.
13062367SN/A                    inst->setExecuted();
13072367SN/A
13082367SN/A                    instToCommit(inst);
13092367SN/A                    activityThisCycle();
13102292SN/A                }
13112326SN/A
13122326SN/A                // Store conditionals will mark themselves as
13132326SN/A                // executed, and their writeback event will add the
13142326SN/A                // instruction to the queue to commit.
13151062SN/A            } else {
13162292SN/A                panic("Unexpected memory type!\n");
13171062SN/A            }
13181062SN/A
13191062SN/A        } else {
13201062SN/A            inst->execute();
13211062SN/A
13222292SN/A            inst->setExecuted();
13232292SN/A
13242292SN/A            instToCommit(inst);
13251062SN/A        }
13261062SN/A
13272301SN/A        updateExeInstStats(inst);
13281681SN/A
13292326SN/A        // Check if branch prediction was correct, if not then we need
13302326SN/A        // to tell commit to squash in flight instructions.  Only
13312326SN/A        // handle this if there hasn't already been something that
13322107SN/A        // redirects fetch in this group of instructions.
13331681SN/A
13342292SN/A        // This probably needs to prioritize the redirects if a different
13352292SN/A        // scheduler is used.  Currently the scheduler schedules the oldest
13362292SN/A        // instruction first, so the branch resolution order will be correct.
13372292SN/A        unsigned tid = inst->threadNumber;
13381062SN/A
13393732Sktlim@umich.edu        if (!fetchRedirect[tid] ||
13403732Sktlim@umich.edu            toCommit->squashedSeqNum[tid] > inst->seqNum) {
13411062SN/A
13421062SN/A            if (inst->mispredicted()) {
13432292SN/A                fetchRedirect[tid] = true;
13441062SN/A
13452292SN/A                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
13463093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
13473093Sksewell@umich.edu                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
13483093Sksewell@umich.edu                        inst->nextNPC);
13493093Sksewell@umich.edu#else
13502292SN/A                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
13511062SN/A                        inst->nextPC);
13522935Sksewell@umich.edu#endif
13531062SN/A                // If incorrect, then signal the ROB that it must be squashed.
13542292SN/A                squashDueToBranch(inst, tid);
13551062SN/A
13561062SN/A                if (inst->predTaken()) {
13571062SN/A                    predictedTakenIncorrect++;
13582292SN/A                } else {
13592292SN/A                    predictedNotTakenIncorrect++;
13601062SN/A                }
13612292SN/A            } else if (ldstQueue.violation(tid)) {
13622326SN/A                // If there was an ordering violation, then get the
13632326SN/A                // DynInst that caused the violation.  Note that this
13642292SN/A                // clears the violation signal.
13652292SN/A                DynInstPtr violator;
13662292SN/A                violator = ldstQueue.getMemDepViolator(tid);
13671062SN/A
13682292SN/A                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
13691062SN/A                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
13701062SN/A                        violator->readPC(), inst->readPC(), inst->physEffAddr);
13711062SN/A
13723732Sktlim@umich.edu                // Ensure the violating instruction is older than
13733732Sktlim@umich.edu                // current squash
13743732Sktlim@umich.edu                if (fetchRedirect[tid] &&
13753732Sktlim@umich.edu                    violator->seqNum >= toCommit->squashedSeqNum[tid])
13763732Sktlim@umich.edu                    continue;
13773732Sktlim@umich.edu
13783732Sktlim@umich.edu                fetchRedirect[tid] = true;
13793732Sktlim@umich.edu
13801062SN/A                // Tell the instruction queue that a violation has occured.
13811062SN/A                instQueue.violation(inst, violator);
13821062SN/A
13831062SN/A                // Squash.
13842292SN/A                squashDueToMemOrder(inst,tid);
13851062SN/A
13861062SN/A                ++memOrderViolationEvents;
13872292SN/A            } else if (ldstQueue.loadBlocked(tid) &&
13882292SN/A                       !ldstQueue.isLoadBlockedHandled(tid)) {
13892292SN/A                fetchRedirect[tid] = true;
13902292SN/A
13912292SN/A                DPRINTF(IEW, "Load operation couldn't execute because the "
13922292SN/A                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
13932292SN/A                        inst->readPC(), inst->seqNum);
13942292SN/A
13952292SN/A                squashDueToMemBlocked(inst, tid);
13961062SN/A            }
13971062SN/A        }
13981062SN/A    }
13992292SN/A
14002348SN/A    // Update and record activity if we processed any instructions.
14012292SN/A    if (inst_num) {
14022292SN/A        if (exeStatus == Idle) {
14032292SN/A            exeStatus = Running;
14042292SN/A        }
14052292SN/A
14062292SN/A        updatedQueues = true;
14072292SN/A
14082292SN/A        cpu->activityThisCycle();
14092292SN/A    }
14102292SN/A
14112292SN/A    // Need to reset this in case a writeback event needs to write into the
14122292SN/A    // iew queue.  That way the writeback event will write into the correct
14132292SN/A    // spot in the queue.
14142292SN/A    wbNumInst = 0;
14152107SN/A}
14162107SN/A
14172292SN/Atemplate <class Impl>
14182107SN/Avoid
14192292SN/ADefaultIEW<Impl>::writebackInsts()
14202107SN/A{
14212326SN/A    // Loop through the head of the time buffer and wake any
14222326SN/A    // dependents.  These instructions are about to write back.  Also
14232326SN/A    // mark scoreboard that this instruction is finally complete.
14242326SN/A    // Either have IEW have direct access to scoreboard, or have this
14252326SN/A    // as part of backwards communication.
14262107SN/A    for (int inst_num = 0; inst_num < issueWidth &&
14272292SN/A             toCommit->insts[inst_num]; inst_num++) {
14282107SN/A        DynInstPtr inst = toCommit->insts[inst_num];
14292301SN/A        int tid = inst->threadNumber;
14302107SN/A
14312698Sktlim@umich.edu        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
14322698Sktlim@umich.edu                inst->seqNum, inst->readPC());
14332107SN/A
14342301SN/A        iewInstsToCommit[tid]++;
14352301SN/A
14362292SN/A        // Some instructions will be sent to commit without having
14372292SN/A        // executed because they need commit to handle them.
14382292SN/A        // E.g. Uncached loads have not actually executed when they
14392292SN/A        // are first sent to commit.  Instead commit must tell the LSQ
14402292SN/A        // when it's ready to execute the uncached load.
14412367SN/A        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
14422301SN/A            int dependents = instQueue.wakeDependents(inst);
14432107SN/A
14442292SN/A            for (int i = 0; i < inst->numDestRegs(); i++) {
14452292SN/A                //mark as Ready
14462292SN/A                DPRINTF(IEW,"Setting Destination Register %i\n",
14472292SN/A                        inst->renamedDestRegIdx(i));
14482292SN/A                scoreboard->setReg(inst->renamedDestRegIdx(i));
14492107SN/A            }
14502301SN/A
14512348SN/A            if (dependents) {
14522348SN/A                producerInst[tid]++;
14532348SN/A                consumerInst[tid]+= dependents;
14542348SN/A            }
14552326SN/A            writebackCount[tid]++;
14562107SN/A        }
14572820Sktlim@umich.edu
14582820Sktlim@umich.edu        decrWb(inst->seqNum);
14592107SN/A    }
14601060SN/A}
14611060SN/A
14621681SN/Atemplate<class Impl>
14631060SN/Avoid
14642292SN/ADefaultIEW<Impl>::tick()
14651060SN/A{
14662292SN/A    wbNumInst = 0;
14672292SN/A    wbCycle = 0;
14681060SN/A
14692292SN/A    wroteToTimeBuffer = false;
14702292SN/A    updatedQueues = false;
14711060SN/A
14722292SN/A    sortInsts();
14731060SN/A
14742326SN/A    // Free function units marked as being freed this cycle.
14752326SN/A    fuPool->processFreeUnits();
14761062SN/A
14773867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
14783867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
14791060SN/A
14802326SN/A    // Check stall and squash signals, dispatch any instructions.
14813867Sbinkertn@umich.edu    while (threads != end) {
14823867Sbinkertn@umich.edu        unsigned tid = *threads++;
14831060SN/A
14842292SN/A        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
14851060SN/A
14862292SN/A        checkSignalsAndUpdate(tid);
14872292SN/A        dispatch(tid);
14881060SN/A    }
14891060SN/A
14902292SN/A    if (exeStatus != Squashing) {
14912292SN/A        executeInsts();
14921060SN/A
14932292SN/A        writebackInsts();
14942292SN/A
14952292SN/A        // Have the instruction queue try to schedule any ready instructions.
14962292SN/A        // (In actuality, this scheduling is for instructions that will
14972292SN/A        // be executed next cycle.)
14982292SN/A        instQueue.scheduleReadyInsts();
14992292SN/A
15002292SN/A        // Also should advance its own time buffers if the stage ran.
15012292SN/A        // Not the best place for it, but this works (hopefully).
15022292SN/A        issueToExecQueue.advance();
15032292SN/A    }
15042292SN/A
15052292SN/A    bool broadcast_free_entries = false;
15062292SN/A
15072292SN/A    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
15082292SN/A        exeStatus = Idle;
15092292SN/A        updateLSQNextCycle = false;
15102292SN/A
15112292SN/A        broadcast_free_entries = true;
15122292SN/A    }
15132292SN/A
15142292SN/A    // Writeback any stores using any leftover bandwidth.
15151681SN/A    ldstQueue.writebackStores();
15161681SN/A
15171061SN/A    // Check the committed load/store signals to see if there's a load
15181061SN/A    // or store to commit.  Also check if it's being told to execute a
15191061SN/A    // nonspeculative instruction.
15201681SN/A    // This is pretty inefficient...
15212292SN/A
15223867Sbinkertn@umich.edu    threads = activeThreads->begin();
15233867Sbinkertn@umich.edu    while (threads != end) {
15242292SN/A        unsigned tid = (*threads++);
15252292SN/A
15262292SN/A        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
15272292SN/A
15282348SN/A        // Update structures based on instructions committed.
15292292SN/A        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
15302292SN/A            !fromCommit->commitInfo[tid].squash &&
15312292SN/A            !fromCommit->commitInfo[tid].robSquashing) {
15322292SN/A
15332292SN/A            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
15342292SN/A
15352292SN/A            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
15362292SN/A
15372292SN/A            updateLSQNextCycle = true;
15382292SN/A            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
15392292SN/A        }
15402292SN/A
15412292SN/A        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
15422292SN/A
15432292SN/A            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
15442292SN/A            if (fromCommit->commitInfo[tid].uncached) {
15452292SN/A                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
15462292SN/A            } else {
15472292SN/A                instQueue.scheduleNonSpec(
15482292SN/A                    fromCommit->commitInfo[tid].nonSpecSeqNum);
15492292SN/A            }
15502292SN/A        }
15512292SN/A
15522292SN/A        if (broadcast_free_entries) {
15532292SN/A            toFetch->iewInfo[tid].iqCount =
15542292SN/A                instQueue.getCount(tid);
15552292SN/A            toFetch->iewInfo[tid].ldstqCount =
15562292SN/A                ldstQueue.getCount(tid);
15572292SN/A
15582292SN/A            toRename->iewInfo[tid].usedIQ = true;
15592292SN/A            toRename->iewInfo[tid].freeIQEntries =
15602292SN/A                instQueue.numFreeEntries();
15612292SN/A            toRename->iewInfo[tid].usedLSQ = true;
15622292SN/A            toRename->iewInfo[tid].freeLSQEntries =
15632292SN/A                ldstQueue.numFreeEntries(tid);
15642292SN/A
15652292SN/A            wroteToTimeBuffer = true;
15662292SN/A        }
15672292SN/A
15682292SN/A        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
15692292SN/A                tid, toRename->iewInfo[tid].dispatched);
15701061SN/A    }
15711061SN/A
15722292SN/A    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
15732292SN/A            "LSQ has %i free entries.\n",
15742292SN/A            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
15752292SN/A            ldstQueue.numFreeEntries());
15762292SN/A
15772292SN/A    updateStatus();
15782292SN/A
15792292SN/A    if (wroteToTimeBuffer) {
15802292SN/A        DPRINTF(Activity, "Activity this cycle.\n");
15812292SN/A        cpu->activityThisCycle();
15821061SN/A    }
15831060SN/A}
15841060SN/A
15852301SN/Atemplate <class Impl>
15861060SN/Avoid
15872301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
15881060SN/A{
15892301SN/A    int thread_number = inst->threadNumber;
15901060SN/A
15912301SN/A    //
15922301SN/A    //  Pick off the software prefetches
15932301SN/A    //
15942301SN/A#ifdef TARGET_ALPHA
15952301SN/A    if (inst->isDataPrefetch())
15962727Sktlim@umich.edu        iewExecutedSwp[thread_number]++;
15972301SN/A    else
15982727Sktlim@umich.edu        iewIewExecutedcutedInsts++;
15992301SN/A#else
16002669Sktlim@umich.edu    iewExecutedInsts++;
16012301SN/A#endif
16021060SN/A
16032301SN/A    //
16042301SN/A    //  Control operations
16052301SN/A    //
16062301SN/A    if (inst->isControl())
16072727Sktlim@umich.edu        iewExecutedBranches[thread_number]++;
16081060SN/A
16092301SN/A    //
16102301SN/A    //  Memory operations
16112301SN/A    //
16122301SN/A    if (inst->isMemRef()) {
16132727Sktlim@umich.edu        iewExecutedRefs[thread_number]++;
16141060SN/A
16152301SN/A        if (inst->isLoad()) {
16162301SN/A            iewExecLoadInsts[thread_number]++;
16171060SN/A        }
16181060SN/A    }
16191060SN/A}
1620