iew_impl.hh revision 3867
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40
41template<class Impl>
42DefaultIEW<Impl>::DefaultIEW(Params *params)
43    : issueToExecQueue(params->backComSize, params->forwardComSize),
44      instQueue(params),
45      ldstQueue(params),
46      fuPool(params->fuPool),
47      commitToIEWDelay(params->commitToIEWDelay),
48      renameToIEWDelay(params->renameToIEWDelay),
49      issueToExecuteDelay(params->issueToExecuteDelay),
50      dispatchWidth(params->dispatchWidth),
51      issueWidth(params->issueWidth),
52      wbOutstanding(0),
53      wbWidth(params->wbWidth),
54      numThreads(params->numberOfThreads),
55      switchedOut(false)
56{
57    _status = Active;
58    exeStatus = Running;
59    wbStatus = Idle;
60
61    // Setup wire to read instructions coming from issue.
62    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
63
64    // Instruction queue needs the queue between issue and execute.
65    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
66
67    instQueue.setIEW(this);
68    ldstQueue.setIEW(this);
69
70    for (int i=0; i < numThreads; i++) {
71        dispatchStatus[i] = Running;
72        stalls[i].commit = false;
73        fetchRedirect[i] = false;
74        bdelayDoneSeqNum[i] = 0;
75    }
76
77    wbMax = wbWidth * params->wbDepth;
78
79    updateLSQNextCycle = false;
80
81    ableToIssue = true;
82
83    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90    return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97    using namespace Stats;
98
99    instQueue.regStats();
100    ldstQueue.regStats();
101
102    iewIdleCycles
103        .name(name() + ".iewIdleCycles")
104        .desc("Number of cycles IEW is idle");
105
106    iewSquashCycles
107        .name(name() + ".iewSquashCycles")
108        .desc("Number of cycles IEW is squashing");
109
110    iewBlockCycles
111        .name(name() + ".iewBlockCycles")
112        .desc("Number of cycles IEW is blocking");
113
114    iewUnblockCycles
115        .name(name() + ".iewUnblockCycles")
116        .desc("Number of cycles IEW is unblocking");
117
118    iewDispatchedInsts
119        .name(name() + ".iewDispatchedInsts")
120        .desc("Number of instructions dispatched to IQ");
121
122    iewDispSquashedInsts
123        .name(name() + ".iewDispSquashedInsts")
124        .desc("Number of squashed instructions skipped by dispatch");
125
126    iewDispLoadInsts
127        .name(name() + ".iewDispLoadInsts")
128        .desc("Number of dispatched load instructions");
129
130    iewDispStoreInsts
131        .name(name() + ".iewDispStoreInsts")
132        .desc("Number of dispatched store instructions");
133
134    iewDispNonSpecInsts
135        .name(name() + ".iewDispNonSpecInsts")
136        .desc("Number of dispatched non-speculative instructions");
137
138    iewIQFullEvents
139        .name(name() + ".iewIQFullEvents")
140        .desc("Number of times the IQ has become full, causing a stall");
141
142    iewLSQFullEvents
143        .name(name() + ".iewLSQFullEvents")
144        .desc("Number of times the LSQ has become full, causing a stall");
145
146    memOrderViolationEvents
147        .name(name() + ".memOrderViolationEvents")
148        .desc("Number of memory order violations");
149
150    predictedTakenIncorrect
151        .name(name() + ".predictedTakenIncorrect")
152        .desc("Number of branches that were predicted taken incorrectly");
153
154    predictedNotTakenIncorrect
155        .name(name() + ".predictedNotTakenIncorrect")
156        .desc("Number of branches that were predicted not taken incorrectly");
157
158    branchMispredicts
159        .name(name() + ".branchMispredicts")
160        .desc("Number of branch mispredicts detected at execute");
161
162    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164    iewExecutedInsts
165        .name(name() + ".iewExecutedInsts")
166        .desc("Number of executed instructions");
167
168    iewExecLoadInsts
169        .init(cpu->number_of_threads)
170        .name(name() + ".iewExecLoadInsts")
171        .desc("Number of load instructions executed")
172        .flags(total);
173
174    iewExecSquashedInsts
175        .name(name() + ".iewExecSquashedInsts")
176        .desc("Number of squashed instructions skipped in execute");
177
178    iewExecutedSwp
179        .init(cpu->number_of_threads)
180        .name(name() + ".EXEC:swp")
181        .desc("number of swp insts executed")
182        .flags(total);
183
184    iewExecutedNop
185        .init(cpu->number_of_threads)
186        .name(name() + ".EXEC:nop")
187        .desc("number of nop insts executed")
188        .flags(total);
189
190    iewExecutedRefs
191        .init(cpu->number_of_threads)
192        .name(name() + ".EXEC:refs")
193        .desc("number of memory reference insts executed")
194        .flags(total);
195
196    iewExecutedBranches
197        .init(cpu->number_of_threads)
198        .name(name() + ".EXEC:branches")
199        .desc("Number of branches executed")
200        .flags(total);
201
202    iewExecStoreInsts
203        .name(name() + ".EXEC:stores")
204        .desc("Number of stores executed")
205        .flags(total);
206    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208    iewExecRate
209        .name(name() + ".EXEC:rate")
210        .desc("Inst execution rate")
211        .flags(total);
212
213    iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215    iewInstsToCommit
216        .init(cpu->number_of_threads)
217        .name(name() + ".WB:sent")
218        .desc("cumulative count of insts sent to commit")
219        .flags(total);
220
221    writebackCount
222        .init(cpu->number_of_threads)
223        .name(name() + ".WB:count")
224        .desc("cumulative count of insts written-back")
225        .flags(total);
226
227    producerInst
228        .init(cpu->number_of_threads)
229        .name(name() + ".WB:producers")
230        .desc("num instructions producing a value")
231        .flags(total);
232
233    consumerInst
234        .init(cpu->number_of_threads)
235        .name(name() + ".WB:consumers")
236        .desc("num instructions consuming a value")
237        .flags(total);
238
239    wbPenalized
240        .init(cpu->number_of_threads)
241        .name(name() + ".WB:penalized")
242        .desc("number of instrctions required to write to 'other' IQ")
243        .flags(total);
244
245    wbPenalizedRate
246        .name(name() + ".WB:penalized_rate")
247        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248        .flags(total);
249
250    wbPenalizedRate = wbPenalized / writebackCount;
251
252    wbFanout
253        .name(name() + ".WB:fanout")
254        .desc("average fanout of values written-back")
255        .flags(total);
256
257    wbFanout = producerInst / consumerInst;
258
259    wbRate
260        .name(name() + ".WB:rate")
261        .desc("insts written-back per cycle")
262        .flags(total);
263    wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270    for (int tid=0; tid < numThreads; tid++) {
271        toRename->iewInfo[tid].usedIQ = true;
272        toRename->iewInfo[tid].freeIQEntries =
273            instQueue.numFreeEntries(tid);
274
275        toRename->iewInfo[tid].usedLSQ = true;
276        toRename->iewInfo[tid].freeLSQEntries =
277            ldstQueue.numFreeEntries(tid);
278    }
279}
280
281template<class Impl>
282void
283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr)
284{
285    DPRINTF(IEW, "Setting CPU pointer.\n");
286    cpu = cpu_ptr;
287
288    instQueue.setCPU(cpu_ptr);
289    ldstQueue.setCPU(cpu_ptr);
290
291    cpu->activateStage(O3CPU::IEWIdx);
292}
293
294template<class Impl>
295void
296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
297{
298    DPRINTF(IEW, "Setting time buffer pointer.\n");
299    timeBuffer = tb_ptr;
300
301    // Setup wire to read information from time buffer, from commit.
302    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
303
304    // Setup wire to write information back to previous stages.
305    toRename = timeBuffer->getWire(0);
306
307    toFetch = timeBuffer->getWire(0);
308
309    // Instruction queue also needs main time buffer.
310    instQueue.setTimeBuffer(tb_ptr);
311}
312
313template<class Impl>
314void
315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317    DPRINTF(IEW, "Setting rename queue pointer.\n");
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    DPRINTF(IEW, "Setting IEW queue pointer.\n");
329    iewQueue = iq_ptr;
330
331    // Setup wire to write instructions to commit.
332    toCommit = iewQueue->getWire(0);
333}
334
335template<class Impl>
336void
337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
338{
339    DPRINTF(IEW, "Setting active threads list pointer.\n");
340    activeThreads = at_ptr;
341
342    ldstQueue.setActiveThreads(at_ptr);
343    instQueue.setActiveThreads(at_ptr);
344}
345
346template<class Impl>
347void
348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
349{
350    DPRINTF(IEW, "Setting scoreboard pointer.\n");
351    scoreboard = sb_ptr;
352}
353
354template <class Impl>
355bool
356DefaultIEW<Impl>::drain()
357{
358    // IEW is ready to drain at any time.
359    cpu->signalDrained();
360    return true;
361}
362
363template <class Impl>
364void
365DefaultIEW<Impl>::resume()
366{
367}
368
369template <class Impl>
370void
371DefaultIEW<Impl>::switchOut()
372{
373    // Clear any state.
374    switchedOut = true;
375    assert(insts[0].empty());
376    assert(skidBuffer[0].empty());
377
378    instQueue.switchOut();
379    ldstQueue.switchOut();
380    fuPool->switchOut();
381
382    for (int i = 0; i < numThreads; i++) {
383        while (!insts[i].empty())
384            insts[i].pop();
385        while (!skidBuffer[i].empty())
386            skidBuffer[i].pop();
387    }
388}
389
390template <class Impl>
391void
392DefaultIEW<Impl>::takeOverFrom()
393{
394    // Reset all state.
395    _status = Active;
396    exeStatus = Running;
397    wbStatus = Idle;
398    switchedOut = false;
399
400    instQueue.takeOverFrom();
401    ldstQueue.takeOverFrom();
402    fuPool->takeOverFrom();
403
404    initStage();
405    cpu->activityThisCycle();
406
407    for (int i=0; i < numThreads; i++) {
408        dispatchStatus[i] = Running;
409        stalls[i].commit = false;
410        fetchRedirect[i] = false;
411    }
412
413    updateLSQNextCycle = false;
414
415    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
416        issueToExecQueue.advance();
417    }
418}
419
420template<class Impl>
421void
422DefaultIEW<Impl>::squash(unsigned tid)
423{
424    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
425            tid);
426
427    // Tell the IQ to start squashing.
428    instQueue.squash(tid);
429
430    // Tell the LDSTQ to start squashing.
431#if ISA_HAS_DELAY_SLOT
432    ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
433#else
434    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
435#endif
436    updatedQueues = true;
437
438    // Clear the skid buffer in case it has any data in it.
439    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
440            tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
441
442    while (!skidBuffer[tid].empty()) {
443#if ISA_HAS_DELAY_SLOT
444        if (skidBuffer[tid].front()->seqNum <=
445            fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
446            DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
447                    "that occur before delay slot [sn:%i].\n",
448                    fromCommit->commitInfo[tid].bdelayDoneSeqNum,
449                    tid);
450            break;
451        } else {
452            DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from "
453                    "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum);
454        }
455#endif
456        if (skidBuffer[tid].front()->isLoad() ||
457            skidBuffer[tid].front()->isStore() ) {
458            toRename->iewInfo[tid].dispatchedToLSQ++;
459        }
460
461        toRename->iewInfo[tid].dispatched++;
462
463        skidBuffer[tid].pop();
464    }
465
466    bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
467
468    emptyRenameInsts(tid);
469}
470
471template<class Impl>
472void
473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
474{
475    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
476            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
477
478    toCommit->squash[tid] = true;
479    toCommit->squashedSeqNum[tid] = inst->seqNum;
480    toCommit->mispredPC[tid] = inst->readPC();
481    toCommit->branchMispredict[tid] = true;
482
483#if ISA_HAS_DELAY_SLOT
484    bool branch_taken = inst->readNextNPC() !=
485        (inst->readNextPC() + sizeof(TheISA::MachInst));
486
487    toCommit->branchTaken[tid] = branch_taken;
488
489    toCommit->condDelaySlotBranch[tid] = inst->isCondDelaySlot();
490
491    if (inst->isCondDelaySlot() && branch_taken) {
492        toCommit->nextPC[tid] = inst->readNextPC();
493    } else {
494        toCommit->nextPC[tid] = inst->readNextNPC();
495    }
496#else
497    toCommit->branchTaken[tid] = inst->readNextPC() !=
498        (inst->readPC() + sizeof(TheISA::MachInst));
499    toCommit->nextPC[tid] = inst->readNextPC();
500#endif
501
502    toCommit->includeSquashInst[tid] = false;
503
504    wroteToTimeBuffer = true;
505}
506
507template<class Impl>
508void
509DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
510{
511    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
512            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
513
514    toCommit->squash[tid] = true;
515    toCommit->squashedSeqNum[tid] = inst->seqNum;
516    toCommit->nextPC[tid] = inst->readNextPC();
517    toCommit->branchMispredict[tid] = false;
518
519    toCommit->includeSquashInst[tid] = false;
520
521    wroteToTimeBuffer = true;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
527{
528    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
529            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
530
531    toCommit->squash[tid] = true;
532    toCommit->squashedSeqNum[tid] = inst->seqNum;
533    toCommit->nextPC[tid] = inst->readPC();
534    toCommit->branchMispredict[tid] = false;
535
536    // Must include the broadcasted SN in the squash.
537    toCommit->includeSquashInst[tid] = true;
538
539    ldstQueue.setLoadBlockedHandled(tid);
540
541    wroteToTimeBuffer = true;
542}
543
544template<class Impl>
545void
546DefaultIEW<Impl>::block(unsigned tid)
547{
548    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
549
550    if (dispatchStatus[tid] != Blocked &&
551        dispatchStatus[tid] != Unblocking) {
552        toRename->iewBlock[tid] = true;
553        wroteToTimeBuffer = true;
554    }
555
556    // Add the current inputs to the skid buffer so they can be
557    // reprocessed when this stage unblocks.
558    skidInsert(tid);
559
560    dispatchStatus[tid] = Blocked;
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::unblock(unsigned tid)
566{
567    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
568            "buffer %u.\n",tid, tid);
569
570    // If the skid bufffer is empty, signal back to previous stages to unblock.
571    // Also switch status to running.
572    if (skidBuffer[tid].empty()) {
573        toRename->iewUnblock[tid] = true;
574        wroteToTimeBuffer = true;
575        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
576        dispatchStatus[tid] = Running;
577    }
578}
579
580template<class Impl>
581void
582DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
583{
584    instQueue.wakeDependents(inst);
585}
586
587template<class Impl>
588void
589DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
590{
591    instQueue.rescheduleMemInst(inst);
592}
593
594template<class Impl>
595void
596DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
597{
598    instQueue.replayMemInst(inst);
599}
600
601template<class Impl>
602void
603DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
604{
605    // This function should not be called after writebackInsts in a
606    // single cycle.  That will cause problems with an instruction
607    // being added to the queue to commit without being processed by
608    // writebackInsts prior to being sent to commit.
609
610    // First check the time slot that this instruction will write
611    // to.  If there are free write ports at the time, then go ahead
612    // and write the instruction to that time.  If there are not,
613    // keep looking back to see where's the first time there's a
614    // free slot.
615    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
616        ++wbNumInst;
617        if (wbNumInst == wbWidth) {
618            ++wbCycle;
619            wbNumInst = 0;
620        }
621
622        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
623    }
624
625    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
626            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
627    // Add finished instruction to queue to commit.
628    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
629    (*iewQueue)[wbCycle].size++;
630}
631
632template <class Impl>
633unsigned
634DefaultIEW<Impl>::validInstsFromRename()
635{
636    unsigned inst_count = 0;
637
638    for (int i=0; i<fromRename->size; i++) {
639        if (!fromRename->insts[i]->isSquashed())
640            inst_count++;
641    }
642
643    return inst_count;
644}
645
646template<class Impl>
647void
648DefaultIEW<Impl>::skidInsert(unsigned tid)
649{
650    DynInstPtr inst = NULL;
651
652    while (!insts[tid].empty()) {
653        inst = insts[tid].front();
654
655        insts[tid].pop();
656
657        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
658                "dispatch skidBuffer %i\n",tid, inst->seqNum,
659                inst->readPC(),tid);
660
661        skidBuffer[tid].push(inst);
662    }
663
664    assert(skidBuffer[tid].size() <= skidBufferMax &&
665           "Skidbuffer Exceeded Max Size");
666}
667
668template<class Impl>
669int
670DefaultIEW<Impl>::skidCount()
671{
672    int max=0;
673
674    std::list<unsigned>::iterator threads = activeThreads->begin();
675    std::list<unsigned>::iterator end = activeThreads->end();
676
677    while (threads != end) {
678        unsigned tid = *threads++;
679        unsigned thread_count = skidBuffer[tid].size();
680        if (max < thread_count)
681            max = thread_count;
682    }
683
684    return max;
685}
686
687template<class Impl>
688bool
689DefaultIEW<Impl>::skidsEmpty()
690{
691    std::list<unsigned>::iterator threads = activeThreads->begin();
692    std::list<unsigned>::iterator end = activeThreads->end();
693
694    while (threads != end) {
695        unsigned tid = *threads++;
696
697        if (!skidBuffer[tid].empty())
698            return false;
699    }
700
701    return true;
702}
703
704template <class Impl>
705void
706DefaultIEW<Impl>::updateStatus()
707{
708    bool any_unblocking = false;
709
710    std::list<unsigned>::iterator threads = activeThreads->begin();
711    std::list<unsigned>::iterator end = activeThreads->end();
712
713    while (threads != end) {
714        unsigned tid = *threads++;
715
716        if (dispatchStatus[tid] == Unblocking) {
717            any_unblocking = true;
718            break;
719        }
720    }
721
722    // If there are no ready instructions waiting to be scheduled by the IQ,
723    // and there's no stores waiting to write back, and dispatch is not
724    // unblocking, then there is no internal activity for the IEW stage.
725    if (_status == Active && !instQueue.hasReadyInsts() &&
726        !ldstQueue.willWB() && !any_unblocking) {
727        DPRINTF(IEW, "IEW switching to idle\n");
728
729        deactivateStage();
730
731        _status = Inactive;
732    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
733                                       ldstQueue.willWB() ||
734                                       any_unblocking)) {
735        // Otherwise there is internal activity.  Set to active.
736        DPRINTF(IEW, "IEW switching to active\n");
737
738        activateStage();
739
740        _status = Active;
741    }
742}
743
744template <class Impl>
745void
746DefaultIEW<Impl>::resetEntries()
747{
748    instQueue.resetEntries();
749    ldstQueue.resetEntries();
750}
751
752template <class Impl>
753void
754DefaultIEW<Impl>::readStallSignals(unsigned tid)
755{
756    if (fromCommit->commitBlock[tid]) {
757        stalls[tid].commit = true;
758    }
759
760    if (fromCommit->commitUnblock[tid]) {
761        assert(stalls[tid].commit);
762        stalls[tid].commit = false;
763    }
764}
765
766template <class Impl>
767bool
768DefaultIEW<Impl>::checkStall(unsigned tid)
769{
770    bool ret_val(false);
771
772    if (stalls[tid].commit) {
773        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
774        ret_val = true;
775    } else if (instQueue.isFull(tid)) {
776        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
777        ret_val = true;
778    } else if (ldstQueue.isFull(tid)) {
779        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
780
781        if (ldstQueue.numLoads(tid) > 0 ) {
782
783            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
784                    tid,ldstQueue.getLoadHeadSeqNum(tid));
785        }
786
787        if (ldstQueue.numStores(tid) > 0) {
788
789            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
790                    tid,ldstQueue.getStoreHeadSeqNum(tid));
791        }
792
793        ret_val = true;
794    } else if (ldstQueue.isStalled(tid)) {
795        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
796        ret_val = true;
797    }
798
799    return ret_val;
800}
801
802template <class Impl>
803void
804DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
805{
806    // Check if there's a squash signal, squash if there is
807    // Check stall signals, block if there is.
808    // If status was Blocked
809    //     if so then go to unblocking
810    // If status was Squashing
811    //     check if squashing is not high.  Switch to running this cycle.
812
813    readStallSignals(tid);
814
815    if (fromCommit->commitInfo[tid].squash) {
816        squash(tid);
817
818        if (dispatchStatus[tid] == Blocked ||
819            dispatchStatus[tid] == Unblocking) {
820            toRename->iewUnblock[tid] = true;
821            wroteToTimeBuffer = true;
822        }
823
824        dispatchStatus[tid] = Squashing;
825
826        fetchRedirect[tid] = false;
827        return;
828    }
829
830    if (fromCommit->commitInfo[tid].robSquashing) {
831        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
832
833        dispatchStatus[tid] = Squashing;
834
835        emptyRenameInsts(tid);
836        wroteToTimeBuffer = true;
837        return;
838    }
839
840    if (checkStall(tid)) {
841        block(tid);
842        dispatchStatus[tid] = Blocked;
843        return;
844    }
845
846    if (dispatchStatus[tid] == Blocked) {
847        // Status from previous cycle was blocked, but there are no more stall
848        // conditions.  Switch over to unblocking.
849        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
850                tid);
851
852        dispatchStatus[tid] = Unblocking;
853
854        unblock(tid);
855
856        return;
857    }
858
859    if (dispatchStatus[tid] == Squashing) {
860        // Switch status to running if rename isn't being told to block or
861        // squash this cycle.
862        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
863                tid);
864
865        dispatchStatus[tid] = Running;
866
867        return;
868    }
869}
870
871template <class Impl>
872void
873DefaultIEW<Impl>::sortInsts()
874{
875    int insts_from_rename = fromRename->size;
876#ifdef DEBUG
877#if !ISA_HAS_DELAY_SLOT
878    for (int i = 0; i < numThreads; i++)
879        assert(insts[i].empty());
880#endif
881#endif
882    for (int i = 0; i < insts_from_rename; ++i) {
883        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
884    }
885}
886
887template <class Impl>
888void
889DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
890{
891    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until "
892            "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
893
894    while (!insts[tid].empty()) {
895#if ISA_HAS_DELAY_SLOT
896        if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
897            DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
898                    " that occurs at or before delay slot [sn:%i].\n",
899                    tid, bdelayDoneSeqNum[tid]);
900            break;
901        } else {
902            DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction "
903                    "[sn:%i].\n", tid, insts[tid].front()->seqNum);
904        }
905#endif
906
907        if (insts[tid].front()->isLoad() ||
908            insts[tid].front()->isStore() ) {
909            toRename->iewInfo[tid].dispatchedToLSQ++;
910        }
911
912        toRename->iewInfo[tid].dispatched++;
913
914        insts[tid].pop();
915    }
916}
917
918template <class Impl>
919void
920DefaultIEW<Impl>::wakeCPU()
921{
922    cpu->wakeCPU();
923}
924
925template <class Impl>
926void
927DefaultIEW<Impl>::activityThisCycle()
928{
929    DPRINTF(Activity, "Activity this cycle.\n");
930    cpu->activityThisCycle();
931}
932
933template <class Impl>
934inline void
935DefaultIEW<Impl>::activateStage()
936{
937    DPRINTF(Activity, "Activating stage.\n");
938    cpu->activateStage(O3CPU::IEWIdx);
939}
940
941template <class Impl>
942inline void
943DefaultIEW<Impl>::deactivateStage()
944{
945    DPRINTF(Activity, "Deactivating stage.\n");
946    cpu->deactivateStage(O3CPU::IEWIdx);
947}
948
949template<class Impl>
950void
951DefaultIEW<Impl>::dispatch(unsigned tid)
952{
953    // If status is Running or idle,
954    //     call dispatchInsts()
955    // If status is Unblocking,
956    //     buffer any instructions coming from rename
957    //     continue trying to empty skid buffer
958    //     check if stall conditions have passed
959
960    if (dispatchStatus[tid] == Blocked) {
961        ++iewBlockCycles;
962
963    } else if (dispatchStatus[tid] == Squashing) {
964        ++iewSquashCycles;
965    }
966
967    // Dispatch should try to dispatch as many instructions as its bandwidth
968    // will allow, as long as it is not currently blocked.
969    if (dispatchStatus[tid] == Running ||
970        dispatchStatus[tid] == Idle) {
971        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
972                "dispatch.\n", tid);
973
974        dispatchInsts(tid);
975    } else if (dispatchStatus[tid] == Unblocking) {
976        // Make sure that the skid buffer has something in it if the
977        // status is unblocking.
978        assert(!skidsEmpty());
979
980        // If the status was unblocking, then instructions from the skid
981        // buffer were used.  Remove those instructions and handle
982        // the rest of unblocking.
983        dispatchInsts(tid);
984
985        ++iewUnblockCycles;
986
987        if (validInstsFromRename() && dispatchedAllInsts) {
988            // Add the current inputs to the skid buffer so they can be
989            // reprocessed when this stage unblocks.
990            skidInsert(tid);
991        }
992
993        unblock(tid);
994    }
995}
996
997template <class Impl>
998void
999DefaultIEW<Impl>::dispatchInsts(unsigned tid)
1000{
1001    dispatchedAllInsts = true;
1002
1003    // Obtain instructions from skid buffer if unblocking, or queue from rename
1004    // otherwise.
1005    std::queue<DynInstPtr> &insts_to_dispatch =
1006        dispatchStatus[tid] == Unblocking ?
1007        skidBuffer[tid] : insts[tid];
1008
1009    int insts_to_add = insts_to_dispatch.size();
1010
1011    DynInstPtr inst;
1012    bool add_to_iq = false;
1013    int dis_num_inst = 0;
1014
1015    // Loop through the instructions, putting them in the instruction
1016    // queue.
1017    for ( ; dis_num_inst < insts_to_add &&
1018              dis_num_inst < dispatchWidth;
1019          ++dis_num_inst)
1020    {
1021        inst = insts_to_dispatch.front();
1022
1023        if (dispatchStatus[tid] == Unblocking) {
1024            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
1025                    "buffer\n", tid);
1026        }
1027
1028        // Make sure there's a valid instruction there.
1029        assert(inst);
1030
1031        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
1032                "IQ.\n",
1033                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
1034
1035        // Be sure to mark these instructions as ready so that the
1036        // commit stage can go ahead and execute them, and mark
1037        // them as issued so the IQ doesn't reprocess them.
1038
1039        // Check for squashed instructions.
1040        if (inst->isSquashed()) {
1041            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1042                    "not adding to IQ.\n", tid);
1043
1044            ++iewDispSquashedInsts;
1045
1046            insts_to_dispatch.pop();
1047
1048            //Tell Rename That An Instruction has been processed
1049            if (inst->isLoad() || inst->isStore()) {
1050                toRename->iewInfo[tid].dispatchedToLSQ++;
1051            }
1052            toRename->iewInfo[tid].dispatched++;
1053
1054            continue;
1055        }
1056
1057        // Check for full conditions.
1058        if (instQueue.isFull(tid)) {
1059            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1060
1061            // Call function to start blocking.
1062            block(tid);
1063
1064            // Set unblock to false. Special case where we are using
1065            // skidbuffer (unblocking) instructions but then we still
1066            // get full in the IQ.
1067            toRename->iewUnblock[tid] = false;
1068
1069            dispatchedAllInsts = false;
1070
1071            ++iewIQFullEvents;
1072            break;
1073        } else if (ldstQueue.isFull(tid)) {
1074            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1075
1076            // Call function to start blocking.
1077            block(tid);
1078
1079            // Set unblock to false. Special case where we are using
1080            // skidbuffer (unblocking) instructions but then we still
1081            // get full in the IQ.
1082            toRename->iewUnblock[tid] = false;
1083
1084            dispatchedAllInsts = false;
1085
1086            ++iewLSQFullEvents;
1087            break;
1088        }
1089
1090        // Otherwise issue the instruction just fine.
1091        if (inst->isLoad()) {
1092            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1093                    "encountered, adding to LSQ.\n", tid);
1094
1095            // Reserve a spot in the load store queue for this
1096            // memory access.
1097            ldstQueue.insertLoad(inst);
1098
1099            ++iewDispLoadInsts;
1100
1101            add_to_iq = true;
1102
1103            toRename->iewInfo[tid].dispatchedToLSQ++;
1104        } else if (inst->isStore()) {
1105            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1106                    "encountered, adding to LSQ.\n", tid);
1107
1108            ldstQueue.insertStore(inst);
1109
1110            ++iewDispStoreInsts;
1111
1112            if (inst->isStoreConditional()) {
1113                // Store conditionals need to be set as "canCommit()"
1114                // so that commit can process them when they reach the
1115                // head of commit.
1116                // @todo: This is somewhat specific to Alpha.
1117                inst->setCanCommit();
1118                instQueue.insertNonSpec(inst);
1119                add_to_iq = false;
1120
1121                ++iewDispNonSpecInsts;
1122            } else {
1123                add_to_iq = true;
1124            }
1125
1126            toRename->iewInfo[tid].dispatchedToLSQ++;
1127#if FULL_SYSTEM
1128        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1129            // Same as non-speculative stores.
1130            inst->setCanCommit();
1131            instQueue.insertBarrier(inst);
1132            add_to_iq = false;
1133#endif
1134        } else if (inst->isNonSpeculative()) {
1135            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1136                    "encountered, skipping.\n", tid);
1137
1138            // Same as non-speculative stores.
1139            inst->setCanCommit();
1140
1141            // Specifically insert it as nonspeculative.
1142            instQueue.insertNonSpec(inst);
1143
1144            ++iewDispNonSpecInsts;
1145
1146            add_to_iq = false;
1147        } else if (inst->isNop()) {
1148            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1149                    "skipping.\n", tid);
1150
1151            inst->setIssued();
1152            inst->setExecuted();
1153            inst->setCanCommit();
1154
1155            instQueue.recordProducer(inst);
1156
1157            iewExecutedNop[tid]++;
1158
1159            add_to_iq = false;
1160        } else if (inst->isExecuted()) {
1161            assert(0 && "Instruction shouldn't be executed.\n");
1162            DPRINTF(IEW, "Issue: Executed branch encountered, "
1163                    "skipping.\n");
1164
1165            inst->setIssued();
1166            inst->setCanCommit();
1167
1168            instQueue.recordProducer(inst);
1169
1170            add_to_iq = false;
1171        } else {
1172            add_to_iq = true;
1173        }
1174
1175        // If the instruction queue is not full, then add the
1176        // instruction.
1177        if (add_to_iq) {
1178            instQueue.insert(inst);
1179        }
1180
1181        insts_to_dispatch.pop();
1182
1183        toRename->iewInfo[tid].dispatched++;
1184
1185        ++iewDispatchedInsts;
1186    }
1187
1188    if (!insts_to_dispatch.empty()) {
1189        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1190        block(tid);
1191        toRename->iewUnblock[tid] = false;
1192    }
1193
1194    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1195        dispatchStatus[tid] = Running;
1196
1197        updatedQueues = true;
1198    }
1199
1200    dis_num_inst = 0;
1201}
1202
1203template <class Impl>
1204void
1205DefaultIEW<Impl>::printAvailableInsts()
1206{
1207    int inst = 0;
1208
1209    std::cout << "Available Instructions: ";
1210
1211    while (fromIssue->insts[inst]) {
1212
1213        if (inst%3==0) std::cout << "\n\t";
1214
1215        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1216             << " TN: " << fromIssue->insts[inst]->threadNumber
1217             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1218
1219        inst++;
1220
1221    }
1222
1223    std::cout << "\n";
1224}
1225
1226template <class Impl>
1227void
1228DefaultIEW<Impl>::executeInsts()
1229{
1230    wbNumInst = 0;
1231    wbCycle = 0;
1232
1233    std::list<unsigned>::iterator threads = activeThreads->begin();
1234    std::list<unsigned>::iterator end = activeThreads->end();
1235
1236    while (threads != end) {
1237        unsigned tid = *threads++;
1238        fetchRedirect[tid] = false;
1239    }
1240
1241    // Uncomment this if you want to see all available instructions.
1242//    printAvailableInsts();
1243
1244    // Execute/writeback any instructions that are available.
1245    int insts_to_execute = fromIssue->size;
1246    int inst_num = 0;
1247    for (; inst_num < insts_to_execute;
1248          ++inst_num) {
1249
1250        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1251
1252        DynInstPtr inst = instQueue.getInstToExecute();
1253
1254        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1255                inst->readPC(), inst->threadNumber,inst->seqNum);
1256
1257        // Check if the instruction is squashed; if so then skip it
1258        if (inst->isSquashed()) {
1259            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1260
1261            // Consider this instruction executed so that commit can go
1262            // ahead and retire the instruction.
1263            inst->setExecuted();
1264
1265            // Not sure if I should set this here or just let commit try to
1266            // commit any squashed instructions.  I like the latter a bit more.
1267            inst->setCanCommit();
1268
1269            ++iewExecSquashedInsts;
1270
1271            decrWb(inst->seqNum);
1272            continue;
1273        }
1274
1275        Fault fault = NoFault;
1276
1277        // Execute instruction.
1278        // Note that if the instruction faults, it will be handled
1279        // at the commit stage.
1280        if (inst->isMemRef() &&
1281            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1282            DPRINTF(IEW, "Execute: Calculating address for memory "
1283                    "reference.\n");
1284
1285            // Tell the LDSTQ to execute this instruction (if it is a load).
1286            if (inst->isLoad()) {
1287                // Loads will mark themselves as executed, and their writeback
1288                // event adds the instruction to the queue to commit
1289                fault = ldstQueue.executeLoad(inst);
1290            } else if (inst->isStore()) {
1291                fault = ldstQueue.executeStore(inst);
1292
1293                // If the store had a fault then it may not have a mem req
1294                if (!inst->isStoreConditional() && fault == NoFault) {
1295                    inst->setExecuted();
1296
1297                    instToCommit(inst);
1298                } else if (fault != NoFault) {
1299                    // If the instruction faulted, then we need to send it along to commit
1300                    // without the instruction completing.
1301                    DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1302                            fault->name(), inst->seqNum);
1303
1304                    // Send this instruction to commit, also make sure iew stage
1305                    // realizes there is activity.
1306                    inst->setExecuted();
1307
1308                    instToCommit(inst);
1309                    activityThisCycle();
1310                }
1311
1312                // Store conditionals will mark themselves as
1313                // executed, and their writeback event will add the
1314                // instruction to the queue to commit.
1315            } else {
1316                panic("Unexpected memory type!\n");
1317            }
1318
1319        } else {
1320            inst->execute();
1321
1322            inst->setExecuted();
1323
1324            instToCommit(inst);
1325        }
1326
1327        updateExeInstStats(inst);
1328
1329        // Check if branch prediction was correct, if not then we need
1330        // to tell commit to squash in flight instructions.  Only
1331        // handle this if there hasn't already been something that
1332        // redirects fetch in this group of instructions.
1333
1334        // This probably needs to prioritize the redirects if a different
1335        // scheduler is used.  Currently the scheduler schedules the oldest
1336        // instruction first, so the branch resolution order will be correct.
1337        unsigned tid = inst->threadNumber;
1338
1339        if (!fetchRedirect[tid] ||
1340            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1341
1342            if (inst->mispredicted()) {
1343                fetchRedirect[tid] = true;
1344
1345                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1346#if ISA_HAS_DELAY_SLOT
1347                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1348                        inst->nextNPC);
1349#else
1350                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
1351                        inst->nextPC);
1352#endif
1353                // If incorrect, then signal the ROB that it must be squashed.
1354                squashDueToBranch(inst, tid);
1355
1356                if (inst->predTaken()) {
1357                    predictedTakenIncorrect++;
1358                } else {
1359                    predictedNotTakenIncorrect++;
1360                }
1361            } else if (ldstQueue.violation(tid)) {
1362                // If there was an ordering violation, then get the
1363                // DynInst that caused the violation.  Note that this
1364                // clears the violation signal.
1365                DynInstPtr violator;
1366                violator = ldstQueue.getMemDepViolator(tid);
1367
1368                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1369                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1370                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1371
1372                // Ensure the violating instruction is older than
1373                // current squash
1374                if (fetchRedirect[tid] &&
1375                    violator->seqNum >= toCommit->squashedSeqNum[tid])
1376                    continue;
1377
1378                fetchRedirect[tid] = true;
1379
1380                // Tell the instruction queue that a violation has occured.
1381                instQueue.violation(inst, violator);
1382
1383                // Squash.
1384                squashDueToMemOrder(inst,tid);
1385
1386                ++memOrderViolationEvents;
1387            } else if (ldstQueue.loadBlocked(tid) &&
1388                       !ldstQueue.isLoadBlockedHandled(tid)) {
1389                fetchRedirect[tid] = true;
1390
1391                DPRINTF(IEW, "Load operation couldn't execute because the "
1392                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1393                        inst->readPC(), inst->seqNum);
1394
1395                squashDueToMemBlocked(inst, tid);
1396            }
1397        }
1398    }
1399
1400    // Update and record activity if we processed any instructions.
1401    if (inst_num) {
1402        if (exeStatus == Idle) {
1403            exeStatus = Running;
1404        }
1405
1406        updatedQueues = true;
1407
1408        cpu->activityThisCycle();
1409    }
1410
1411    // Need to reset this in case a writeback event needs to write into the
1412    // iew queue.  That way the writeback event will write into the correct
1413    // spot in the queue.
1414    wbNumInst = 0;
1415}
1416
1417template <class Impl>
1418void
1419DefaultIEW<Impl>::writebackInsts()
1420{
1421    // Loop through the head of the time buffer and wake any
1422    // dependents.  These instructions are about to write back.  Also
1423    // mark scoreboard that this instruction is finally complete.
1424    // Either have IEW have direct access to scoreboard, or have this
1425    // as part of backwards communication.
1426    for (int inst_num = 0; inst_num < issueWidth &&
1427             toCommit->insts[inst_num]; inst_num++) {
1428        DynInstPtr inst = toCommit->insts[inst_num];
1429        int tid = inst->threadNumber;
1430
1431        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1432                inst->seqNum, inst->readPC());
1433
1434        iewInstsToCommit[tid]++;
1435
1436        // Some instructions will be sent to commit without having
1437        // executed because they need commit to handle them.
1438        // E.g. Uncached loads have not actually executed when they
1439        // are first sent to commit.  Instead commit must tell the LSQ
1440        // when it's ready to execute the uncached load.
1441        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1442            int dependents = instQueue.wakeDependents(inst);
1443
1444            for (int i = 0; i < inst->numDestRegs(); i++) {
1445                //mark as Ready
1446                DPRINTF(IEW,"Setting Destination Register %i\n",
1447                        inst->renamedDestRegIdx(i));
1448                scoreboard->setReg(inst->renamedDestRegIdx(i));
1449            }
1450
1451            if (dependents) {
1452                producerInst[tid]++;
1453                consumerInst[tid]+= dependents;
1454            }
1455            writebackCount[tid]++;
1456        }
1457
1458        decrWb(inst->seqNum);
1459    }
1460}
1461
1462template<class Impl>
1463void
1464DefaultIEW<Impl>::tick()
1465{
1466    wbNumInst = 0;
1467    wbCycle = 0;
1468
1469    wroteToTimeBuffer = false;
1470    updatedQueues = false;
1471
1472    sortInsts();
1473
1474    // Free function units marked as being freed this cycle.
1475    fuPool->processFreeUnits();
1476
1477    std::list<unsigned>::iterator threads = activeThreads->begin();
1478    std::list<unsigned>::iterator end = activeThreads->end();
1479
1480    // Check stall and squash signals, dispatch any instructions.
1481    while (threads != end) {
1482        unsigned tid = *threads++;
1483
1484        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1485
1486        checkSignalsAndUpdate(tid);
1487        dispatch(tid);
1488    }
1489
1490    if (exeStatus != Squashing) {
1491        executeInsts();
1492
1493        writebackInsts();
1494
1495        // Have the instruction queue try to schedule any ready instructions.
1496        // (In actuality, this scheduling is for instructions that will
1497        // be executed next cycle.)
1498        instQueue.scheduleReadyInsts();
1499
1500        // Also should advance its own time buffers if the stage ran.
1501        // Not the best place for it, but this works (hopefully).
1502        issueToExecQueue.advance();
1503    }
1504
1505    bool broadcast_free_entries = false;
1506
1507    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1508        exeStatus = Idle;
1509        updateLSQNextCycle = false;
1510
1511        broadcast_free_entries = true;
1512    }
1513
1514    // Writeback any stores using any leftover bandwidth.
1515    ldstQueue.writebackStores();
1516
1517    // Check the committed load/store signals to see if there's a load
1518    // or store to commit.  Also check if it's being told to execute a
1519    // nonspeculative instruction.
1520    // This is pretty inefficient...
1521
1522    threads = activeThreads->begin();
1523    while (threads != end) {
1524        unsigned tid = (*threads++);
1525
1526        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1527
1528        // Update structures based on instructions committed.
1529        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1530            !fromCommit->commitInfo[tid].squash &&
1531            !fromCommit->commitInfo[tid].robSquashing) {
1532
1533            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1534
1535            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1536
1537            updateLSQNextCycle = true;
1538            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1539        }
1540
1541        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1542
1543            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1544            if (fromCommit->commitInfo[tid].uncached) {
1545                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1546            } else {
1547                instQueue.scheduleNonSpec(
1548                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1549            }
1550        }
1551
1552        if (broadcast_free_entries) {
1553            toFetch->iewInfo[tid].iqCount =
1554                instQueue.getCount(tid);
1555            toFetch->iewInfo[tid].ldstqCount =
1556                ldstQueue.getCount(tid);
1557
1558            toRename->iewInfo[tid].usedIQ = true;
1559            toRename->iewInfo[tid].freeIQEntries =
1560                instQueue.numFreeEntries();
1561            toRename->iewInfo[tid].usedLSQ = true;
1562            toRename->iewInfo[tid].freeLSQEntries =
1563                ldstQueue.numFreeEntries(tid);
1564
1565            wroteToTimeBuffer = true;
1566        }
1567
1568        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1569                tid, toRename->iewInfo[tid].dispatched);
1570    }
1571
1572    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1573            "LSQ has %i free entries.\n",
1574            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1575            ldstQueue.numFreeEntries());
1576
1577    updateStatus();
1578
1579    if (wroteToTimeBuffer) {
1580        DPRINTF(Activity, "Activity this cycle.\n");
1581        cpu->activityThisCycle();
1582    }
1583}
1584
1585template <class Impl>
1586void
1587DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1588{
1589    int thread_number = inst->threadNumber;
1590
1591    //
1592    //  Pick off the software prefetches
1593    //
1594#ifdef TARGET_ALPHA
1595    if (inst->isDataPrefetch())
1596        iewExecutedSwp[thread_number]++;
1597    else
1598        iewIewExecutedcutedInsts++;
1599#else
1600    iewExecutedInsts++;
1601#endif
1602
1603    //
1604    //  Control operations
1605    //
1606    if (inst->isControl())
1607        iewExecutedBranches[thread_number]++;
1608
1609    //
1610    //  Memory operations
1611    //
1612    if (inst->isMemRef()) {
1613        iewExecutedRefs[thread_number]++;
1614
1615        if (inst->isLoad()) {
1616            iewExecLoadInsts[thread_number]++;
1617        }
1618    }
1619}
1620