iew_impl.hh revision 2333
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 310239Sbinhpham@cs.rutgers.edu * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 67598Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 77598Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 87598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 97598Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 107598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 117598Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 127598Sminkyu.jeong@arm.com * neither the name of the copyright holders nor the names of its 137598Sminkyu.jeong@arm.com * contributors may be used to endorse or promote products derived from 147598Sminkyu.jeong@arm.com * this software without specific prior written permission. 152326SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291689SN/A// @todo: Fix the instantaneous communication among all the stages within 301689SN/A// iew. There's a clear delay between issue and execute, yet backwards 311689SN/A// communication happens simultaneously. 321689SN/A 331689SN/A#include <queue> 341689SN/A 351689SN/A#include "base/timebuf.hh" 361689SN/A#include "cpu/o3/fu_pool.hh" 371689SN/A#include "cpu/o3/iew.hh" 381689SN/A 391689SN/Ausing namespace std; 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edutemplate<class Impl> 421689SN/ADefaultIEW<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst, 431689SN/A DefaultIEW<Impl> *_iew) 449944Smatt.horsnell@ARM.com : Event(&mainEventQueue), inst(_inst), iewStage(_iew) 459944Smatt.horsnell@ARM.com{ 469944Smatt.horsnell@ARM.com this->setFlags(Event::AutoDelete); 471060SN/A} 481060SN/A 491689SN/Atemplate<class Impl> 501060SN/Avoid 511060SN/ADefaultIEW<Impl>::LdWritebackEvent::process() 521060SN/A{ 538230Snate@binkert.org DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum); 546658Snate@binkert.org DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 558887Sgeoffrey.blake@arm.com 562292SN/A //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 571717SN/A 588229Snate@binkert.org if (iewStage->isSwitchedOut()) { 598232Snate@binkert.org inst = NULL; 609444SAndreas.Sandberg@ARM.com return; 618232Snate@binkert.org } else if (inst->isSquashed()) { 629527SMatt.Horsnell@arm.com iewStage->wakeCPU(); 635529Snate@binkert.org inst = NULL; 641060SN/A return; 656221Snate@binkert.org } 666221Snate@binkert.org 671681SN/A iewStage->wakeCPU(); 685529Snate@binkert.org 692873Sktlim@umich.edu if (!inst->isExecuted()) { 704329Sktlim@umich.edu inst->setExecuted(); 714329Sktlim@umich.edu 724329Sktlim@umich.edu // Complete access to copy data to proper place. 732292SN/A if (inst->isStore()) { 742292SN/A inst->completeAcc(); 752292SN/A } 762292SN/A } 772820Sktlim@umich.edu 782292SN/A // Need to insert instruction into queue to commit 792820Sktlim@umich.edu iewStage->instToCommit(inst); 809444SAndreas.Sandberg@ARM.com 811060SN/A iewStage->activityThisCycle(); 8210172Sdam.sunwoo@arm.com 8310172Sdam.sunwoo@arm.com inst = NULL; 8410172Sdam.sunwoo@arm.com} 8510172Sdam.sunwoo@arm.com 8610172Sdam.sunwoo@arm.comtemplate<class Impl> 8710172Sdam.sunwoo@arm.comconst char * 8810172Sdam.sunwoo@arm.comDefaultIEW<Impl>::LdWritebackEvent::description() 8910172Sdam.sunwoo@arm.com{ 9010172Sdam.sunwoo@arm.com return "Load writeback event"; 9110172Sdam.sunwoo@arm.com} 9210172Sdam.sunwoo@arm.com 9310172Sdam.sunwoo@arm.comtemplate<class Impl> 9410172Sdam.sunwoo@arm.comDefaultIEW<Impl>::DefaultIEW(Params *params) 952292SN/A : // @todo: Make this into a parameter. 962292SN/A issueToExecQueue(5, 5), 972292SN/A instQueue(params), 981060SN/A ldstQueue(params), 991060SN/A fuPool(params->fuPool), 1001060SN/A commitToIEWDelay(params->commitToIEWDelay), 1011060SN/A renameToIEWDelay(params->renameToIEWDelay), 1021060SN/A issueToExecuteDelay(params->issueToExecuteDelay), 1031060SN/A issueReadWidth(params->issueWidth), 1041681SN/A issueWidth(params->issueWidth), 1056221Snate@binkert.org executeWidth(params->executeWidth), 1066221Snate@binkert.org numThreads(params->numberOfThreads), 1076221Snate@binkert.org switchedOut(false) 1082292SN/A{ 1092292SN/A _status = Active; 1102292SN/A exeStatus = Running; 1112292SN/A wbStatus = Idle; 11210328Smitch.hayenga@arm.com 1132292SN/A // Setup wire to read instructions coming from issue. 1142292SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1152292SN/A 1162292SN/A // Instruction queue needs the queue between issue and execute. 1172292SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1182292SN/A 1192292SN/A instQueue.setIEW(this); 1201060SN/A ldstQueue.setIEW(this); 1211060SN/A 1221681SN/A for (int i=0; i < numThreads; i++) { 1231062SN/A dispatchStatus[i] = Running; 12410023Smatt.horsnell@ARM.com stalls[i].commit = false; 12510023Smatt.horsnell@ARM.com fetchRedirect[i] = false; 12610023Smatt.horsnell@ARM.com } 12710023Smatt.horsnell@ARM.com 12810023Smatt.horsnell@ARM.com updateLSQNextCycle = false; 12910023Smatt.horsnell@ARM.com 13010023Smatt.horsnell@ARM.com skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 13110023Smatt.horsnell@ARM.com} 1322292SN/A 1331062SN/Atemplate <class Impl> 1342301SN/Astd::string 1352301SN/ADefaultIEW<Impl>::name() const 1361062SN/A{ 1372727Sktlim@umich.edu return cpu->name() + ".iew"; 1381062SN/A} 1391062SN/A 1401062SN/Atemplate <class Impl> 1411062SN/Avoid 1421062SN/ADefaultIEW<Impl>::regStats() 1431062SN/A{ 1441062SN/A using namespace Stats; 1451062SN/A 1461062SN/A instQueue.regStats(); 1471062SN/A 1481062SN/A iewIdleCycles 1491062SN/A .name(name() + ".iewIdleCycles") 1501062SN/A .desc("Number of cycles IEW is idle"); 1511062SN/A 1521062SN/A iewSquashCycles 1531062SN/A .name(name() + ".iewSquashCycles") 1541062SN/A .desc("Number of cycles IEW is squashing"); 1551062SN/A 1561062SN/A iewBlockCycles 1571062SN/A .name(name() + ".iewBlockCycles") 1581062SN/A .desc("Number of cycles IEW is blocking"); 1591062SN/A 1601062SN/A iewUnblockCycles 1611062SN/A .name(name() + ".iewUnblockCycles") 1621062SN/A .desc("Number of cycles IEW is unblocking"); 1631062SN/A 1641062SN/A iewDispatchedInsts 1651062SN/A .name(name() + ".iewDispatchedInsts") 1661062SN/A .desc("Number of instructions dispatched to IQ"); 1671062SN/A 1681062SN/A iewDispSquashedInsts 1691062SN/A .name(name() + ".iewDispSquashedInsts") 1701062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1711062SN/A 1721062SN/A iewDispLoadInsts 1731062SN/A .name(name() + ".iewDispLoadInsts") 1741062SN/A .desc("Number of dispatched load instructions"); 1751062SN/A 1761062SN/A iewDispStoreInsts 1771062SN/A .name(name() + ".iewDispStoreInsts") 1781062SN/A .desc("Number of dispatched store instructions"); 1792292SN/A 1802292SN/A iewDispNonSpecInsts 1812292SN/A .name(name() + ".iewDispNonSpecInsts") 1822292SN/A .desc("Number of dispatched non-speculative instructions"); 1831062SN/A 1841062SN/A iewIQFullEvents 1851062SN/A .name(name() + ".iewIQFullEvents") 1861062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1871062SN/A 1881062SN/A iewLSQFullEvents 1891062SN/A .name(name() + ".iewLSQFullEvents") 1902292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1912292SN/A 1922292SN/A iewExecutedInsts 1932292SN/A .name(name() + ".iewExecutedInsts") 1942292SN/A .desc("Number of executed instructions"); 1952292SN/A 1962292SN/A iewExecLoadInsts 1972292SN/A .init(cpu->number_of_threads) 1982292SN/A .name(name() + ".iewExecLoadInsts") 1992292SN/A .desc("Number of load instructions executed") 2002301SN/A .flags(total); 2012727Sktlim@umich.edu 2022353SN/A iewExecSquashedInsts 2032727Sktlim@umich.edu .name(name() + ".iewExecSquashedInsts") 2042727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 2052727Sktlim@umich.edu 2066221Snate@binkert.org memOrderViolationEvents 2072353SN/A .name(name() + ".memOrderViolationEvents") 2082727Sktlim@umich.edu .desc("Number of memory order violations"); 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu predictedTakenIncorrect 2112727Sktlim@umich.edu .name(name() + ".predictedTakenIncorrect") 2122353SN/A .desc("Number of branches that were predicted taken incorrectly"); 2132727Sktlim@umich.edu 2142727Sktlim@umich.edu predictedNotTakenIncorrect 2152727Sktlim@umich.edu .name(name() + ".predictedNotTakenIncorrect") 2166221Snate@binkert.org .desc("Number of branches that were predicted not taken incorrectly"); 2178240Snate@binkert.org 2182301SN/A branchMispredicts 2192727Sktlim@umich.edu .name(name() + ".branchMispredicts") 2202301SN/A .desc("Number of branch mispredicts detected at execute"); 2212727Sktlim@umich.edu 2226221Snate@binkert.org branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2238240Snate@binkert.org 2242301SN/A exeSwp 2252727Sktlim@umich.edu .init(cpu->number_of_threads) 2262301SN/A .name(name() + ".EXEC:swp") 2272727Sktlim@umich.edu .desc("number of swp insts executed") 2286221Snate@binkert.org .flags(total) 2298240Snate@binkert.org ; 2302301SN/A 2312727Sktlim@umich.edu exeNop 2322301SN/A .init(cpu->number_of_threads) 2332727Sktlim@umich.edu .name(name() + ".EXEC:nop") 2346221Snate@binkert.org .desc("number of nop insts executed") 2358240Snate@binkert.org .flags(total) 2362301SN/A ; 2372727Sktlim@umich.edu 2382301SN/A exeRefs 2392301SN/A .init(cpu->number_of_threads) 2408240Snate@binkert.org .name(name() + ".EXEC:refs") 2412301SN/A .desc("number of memory reference insts executed") 2422727Sktlim@umich.edu .flags(total) 2432727Sktlim@umich.edu ; 2442727Sktlim@umich.edu 2452727Sktlim@umich.edu exeBranches 2468240Snate@binkert.org .init(cpu->number_of_threads) 2472727Sktlim@umich.edu .name(name() + ".EXEC:branches") 2482727Sktlim@umich.edu .desc("Number of branches executed") 2492727Sktlim@umich.edu .flags(total) 2502727Sktlim@umich.edu ; 2512301SN/A 2522301SN/A issueRate 2536221Snate@binkert.org .name(name() + ".EXEC:rate") 2548240Snate@binkert.org .desc("Inst execution rate") 2552301SN/A .flags(total) 2562727Sktlim@umich.edu ; 2572301SN/A issueRate = iewExecutedInsts / cpu->numCycles; 2582326SN/A 2596221Snate@binkert.org iewExecStoreInsts 2608240Snate@binkert.org .name(name() + ".EXEC:stores") 2612301SN/A .desc("Number of stores executed") 2622727Sktlim@umich.edu .flags(total) 2632301SN/A ; 2642326SN/A iewExecStoreInsts = exeRefs - iewExecLoadInsts; 2656221Snate@binkert.org/* 2668240Snate@binkert.org for (int i=0; i<Num_OpClasses; ++i) { 2672301SN/A stringstream subname; 2682727Sktlim@umich.edu subname << opClassStrings[i] << "_delay"; 2692301SN/A issue_delay_dist.subname(i, subname.str()); 2702326SN/A } 2716221Snate@binkert.org*/ 2728240Snate@binkert.org // 2732301SN/A // Other stats 2742727Sktlim@umich.edu // 2752301SN/A 2762326SN/A iewInstsToCommit 2776221Snate@binkert.org .init(cpu->number_of_threads) 2788240Snate@binkert.org .name(name() + ".WB:sent") 2792301SN/A .desc("cumulative count of insts sent to commit") 2802727Sktlim@umich.edu .flags(total) 2812301SN/A ; 2822326SN/A 2838240Snate@binkert.org writebackCount 2842301SN/A .init(cpu->number_of_threads) 2852727Sktlim@umich.edu .name(name() + ".WB:count") 2862301SN/A .desc("cumulative count of insts written-back") 2872326SN/A .flags(total) 2882301SN/A ; 2892326SN/A 2908240Snate@binkert.org producerInst 2912301SN/A .init(cpu->number_of_threads) 2922727Sktlim@umich.edu .name(name() + ".WB:producers") 2932301SN/A .desc("num instructions producing a value") 2942326SN/A .flags(total) 2952301SN/A ; 2962326SN/A 2978240Snate@binkert.org consumerInst 2982301SN/A .init(cpu->number_of_threads) 2992727Sktlim@umich.edu .name(name() + ".WB:consumers") 3002326SN/A .desc("num instructions consuming a value") 3011062SN/A .flags(total) 3021062SN/A ; 3031681SN/A 3041060SN/A wbPenalized 3059427SAndreas.Sandberg@ARM.com .init(cpu->number_of_threads) 3061060SN/A .name(name() + ".WB:penalized") 3076221Snate@binkert.org .desc("number of instrctions required to write to 'other' IQ") 3082292SN/A .flags(total) 3092292SN/A ; 3102292SN/A 3112292SN/A wbPenalizedRate 3122292SN/A .name(name() + ".WB:penalized_rate") 31310239Sbinhpham@cs.rutgers.edu .desc ("fraction of instructions written-back that wrote to 'other' IQ") 31410239Sbinhpham@cs.rutgers.edu .flags(total) 3152292SN/A ; 3162292SN/A 3178887Sgeoffrey.blake@arm.com wbPenalizedRate = wbPenalized / writebackCount; 3188733Sgeoffrey.blake@arm.com 3198850Sandreas.hansson@arm.com wbFanout 3208887Sgeoffrey.blake@arm.com .name(name() + ".WB:fanout") 3218733Sgeoffrey.blake@arm.com .desc("average fanout of values written-back") 3222733Sktlim@umich.edu .flags(total) 3231060SN/A ; 3241060SN/A 3251681SN/A wbFanout = producerInst / consumerInst; 3261060SN/A 3272292SN/A wbRate 3281060SN/A .name(name() + ".WB:rate") 3291060SN/A .desc("insts written-back per cycle") 3301060SN/A .flags(total) 3311060SN/A ; 3321060SN/A wbRate = writebackCount / cpu->numCycles; 3331060SN/A} 3341060SN/A 3351060SN/Atemplate<class Impl> 3361060SN/Avoid 3372292SN/ADefaultIEW<Impl>::initStage() 3382292SN/A{ 3391060SN/A for (int tid=0; tid < numThreads; tid++) { 3401060SN/A toRename->iewInfo[tid].usedIQ = true; 3411060SN/A toRename->iewInfo[tid].freeIQEntries = 3421060SN/A instQueue.numFreeEntries(tid); 3431681SN/A 3441060SN/A toRename->iewInfo[tid].usedLSQ = true; 3452292SN/A toRename->iewInfo[tid].freeLSQEntries = 3461060SN/A ldstQueue.numFreeEntries(tid); 3471060SN/A } 3481060SN/A} 3491060SN/A 3501060SN/Atemplate<class Impl> 3511060SN/Avoid 3521060SN/ADefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 3531681SN/A{ 3541060SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 3552292SN/A cpu = cpu_ptr; 3561060SN/A 3571060SN/A instQueue.setCPU(cpu_ptr); 3581060SN/A ldstQueue.setCPU(cpu_ptr); 3591060SN/A 3601060SN/A cpu->activateStage(FullCPU::IEWIdx); 3611060SN/A} 3621060SN/A 3631681SN/Atemplate<class Impl> 3641060SN/Avoid 3656221Snate@binkert.orgDefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3661060SN/A{ 3672292SN/A DPRINTF(IEW, "Setting time buffer pointer.\n"); 3682292SN/A timeBuffer = tb_ptr; 3692292SN/A 3702292SN/A // Setup wire to read information from time buffer, from commit. 3711060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3721060SN/A 3731681SN/A // Setup wire to write information back to previous stages. 3741060SN/A toRename = timeBuffer->getWire(0); 3752292SN/A 3761060SN/A toFetch = timeBuffer->getWire(0); 3772292SN/A 3781060SN/A // Instruction queue also needs main time buffer. 3791060SN/A instQueue.setTimeBuffer(tb_ptr); 3802307SN/A} 3812863Sktlim@umich.edu 3829444SAndreas.Sandberg@ARM.comtemplate<class Impl> 3832307SN/Avoid 3849444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3859444SAndreas.Sandberg@ARM.com{ 3869444SAndreas.Sandberg@ARM.com DPRINTF(IEW, "Setting rename queue pointer.\n"); 3879444SAndreas.Sandberg@ARM.com renameQueue = rq_ptr; 3889444SAndreas.Sandberg@ARM.com 3899444SAndreas.Sandberg@ARM.com // Setup wire to read information from rename queue. 3909444SAndreas.Sandberg@ARM.com fromRename = renameQueue->getWire(-renameToIEWDelay); 3919444SAndreas.Sandberg@ARM.com} 3929444SAndreas.Sandberg@ARM.com 3939444SAndreas.Sandberg@ARM.comtemplate<class Impl> 3949444SAndreas.Sandberg@ARM.comvoid 3959444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3969444SAndreas.Sandberg@ARM.com{ 3979783Sandreas.hansson@arm.com DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3989783Sandreas.hansson@arm.com iewQueue = iq_ptr; 3999783Sandreas.hansson@arm.com 4009783Sandreas.hansson@arm.com // Setup wire to write instructions to commit. 4019783Sandreas.hansson@arm.com toCommit = iewQueue->getWire(0); 4029783Sandreas.hansson@arm.com} 4039783Sandreas.hansson@arm.com 4049783Sandreas.hansson@arm.comtemplate<class Impl> 4059444SAndreas.Sandberg@ARM.comvoid 4061681SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 4071681SN/A{ 4082316SN/A DPRINTF(IEW, "Setting active threads list pointer.\n"); 4091681SN/A activeThreads = at_ptr; 4109444SAndreas.Sandberg@ARM.com 4112843Sktlim@umich.edu ldstQueue.setActiveThreads(at_ptr); 4129444SAndreas.Sandberg@ARM.com instQueue.setActiveThreads(at_ptr); 4132843Sktlim@umich.edu} 4149444SAndreas.Sandberg@ARM.com 4159444SAndreas.Sandberg@ARM.comtemplate<class Impl> 4161681SN/Avoid 4171681SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 4182307SN/A{ 4191681SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 4202307SN/A scoreboard = sb_ptr; 4211060SN/A} 4222348SN/A 4232307SN/A#if 0 4242307SN/Atemplate<class Impl> 4252307SN/Avoid 4261060SN/ADefaultIEW<Impl>::setPageTable(PageTable *pt_ptr) 4272307SN/A{ 4282307SN/A ldstQueue.setPageTable(pt_ptr); 4299444SAndreas.Sandberg@ARM.com} 4301060SN/A#endif 4319427SAndreas.Sandberg@ARM.com 4322307SN/Atemplate <class Impl> 4331060SN/Avoid 4346221Snate@binkert.orgDefaultIEW<Impl>::switchOut() 4356221Snate@binkert.org{ 4366221Snate@binkert.org cpu->signalSwitched(); 4372307SN/A} 4381060SN/A 4392307SN/Atemplate <class Impl> 4402307SN/Avoid 4412873Sktlim@umich.eduDefaultIEW<Impl>::doSwitchOut() 4422307SN/A{ 4431060SN/A switchedOut = true; 4441060SN/A 4451060SN/A instQueue.switchOut(); 4461681SN/A ldstQueue.switchOut(); 4471060SN/A fuPool->switchOut(); 4486221Snate@binkert.org 4492107SN/A for (int i = 0; i < numThreads; i++) { 4506221Snate@binkert.org while (!insts[i].empty()) 4512107SN/A insts[i].pop(); 4522292SN/A while (!skidBuffer[i].empty()) 4532292SN/A skidBuffer[i].pop(); 4542107SN/A } 4552292SN/A} 4562326SN/A 4572292SN/Atemplate <class Impl> 4582107SN/Avoid 4592292SN/ADefaultIEW<Impl>::takeOverFrom() 4602935Sksewell@umich.edu{ 4614632Sgblack@eecs.umich.edu _status = Active; 4622935Sksewell@umich.edu exeStatus = Running; 4632292SN/A wbStatus = Idle; 46410239Sbinhpham@cs.rutgers.edu switchedOut = false; 46510239Sbinhpham@cs.rutgers.edu 46610239Sbinhpham@cs.rutgers.edu instQueue.takeOverFrom(); 46710239Sbinhpham@cs.rutgers.edu ldstQueue.takeOverFrom(); 46810239Sbinhpham@cs.rutgers.edu fuPool->takeOverFrom(); 4692292SN/A 4702107SN/A initStage(); 4712292SN/A cpu->activityThisCycle(); 4722107SN/A 4732292SN/A for (int i=0; i < numThreads; i++) { 4742292SN/A dispatchStatus[i] = Running; 4752107SN/A stalls[i].commit = false; 4762702Sktlim@umich.edu fetchRedirect[i] = false; 4772107SN/A } 4782107SN/A 4792107SN/A updateLSQNextCycle = false; 4802107SN/A 4816221Snate@binkert.org // @todo: Fix hardcoded number 4822292SN/A for (int i = 0; i < 6; ++i) { 4837720Sgblack@eecs.umich.edu issueToExecQueue.advance(); 4847720Sgblack@eecs.umich.edu } 4852292SN/A} 48610231Ssteve.reinhardt@amd.com 4877852SMatt.Horsnell@arm.comtemplate<class Impl> 4887852SMatt.Horsnell@arm.comvoid 4897852SMatt.Horsnell@arm.comDefaultIEW<Impl>::squash(unsigned tid) 4907852SMatt.Horsnell@arm.com{ 4912935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4927852SMatt.Horsnell@arm.com tid); 4937852SMatt.Horsnell@arm.com 4942292SN/A // Tell the IQ to start squashing. 4957852SMatt.Horsnell@arm.com instQueue.squash(tid); 4967852SMatt.Horsnell@arm.com 4977852SMatt.Horsnell@arm.com // Tell the LDSTQ to start squashing. 4982292SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4997852SMatt.Horsnell@arm.com 5007852SMatt.Horsnell@arm.com updatedQueues = true; 5017852SMatt.Horsnell@arm.com 5022292SN/A // Clear the skid buffer in case it has any data in it. 5032292SN/A while (!skidBuffer[tid].empty()) { 5042292SN/A 5052292SN/A if (skidBuffer[tid].front()->isLoad() || 5066221Snate@binkert.org skidBuffer[tid].front()->isStore() ) { 5072292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 5088513SGiacomo.Gabrielli@arm.com } 5098513SGiacomo.Gabrielli@arm.com 5108513SGiacomo.Gabrielli@arm.com toRename->iewInfo[tid].dispatched++; 5118513SGiacomo.Gabrielli@arm.com 5128513SGiacomo.Gabrielli@arm.com skidBuffer[tid].pop(); 5138513SGiacomo.Gabrielli@arm.com } 5148513SGiacomo.Gabrielli@arm.com 5158513SGiacomo.Gabrielli@arm.com while (!insts[tid].empty()) { 51610231Ssteve.reinhardt@amd.com if (insts[tid].front()->isLoad() || 5178513SGiacomo.Gabrielli@arm.com insts[tid].front()->isStore() ) { 5188513SGiacomo.Gabrielli@arm.com toRename->iewInfo[tid].dispatchedToLSQ++; 5192292SN/A } 5207852SMatt.Horsnell@arm.com 5218513SGiacomo.Gabrielli@arm.com toRename->iewInfo[tid].dispatched++; 5228137SAli.Saidi@ARM.com 5232292SN/A insts[tid].pop(); 5248513SGiacomo.Gabrielli@arm.com } 5258513SGiacomo.Gabrielli@arm.com} 5262292SN/A 5277852SMatt.Horsnell@arm.comtemplate<class Impl> 5287852SMatt.Horsnell@arm.comvoid 5292292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 5302292SN/A{ 5312292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 5322292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5336221Snate@binkert.org 5342292SN/A toCommit->squash[tid] = true; 5352292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5367720Sgblack@eecs.umich.edu toCommit->mispredPC[tid] = inst->readPC(); 53710231Ssteve.reinhardt@amd.com toCommit->nextPC[tid] = inst->readNextPC(); 5387852SMatt.Horsnell@arm.com toCommit->branchMispredict[tid] = true; 5397852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->readNextPC() != 5402292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 5417852SMatt.Horsnell@arm.com 5427852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 5438137SAli.Saidi@ARM.com 5442292SN/A wroteToTimeBuffer = true; 5457852SMatt.Horsnell@arm.com} 5467852SMatt.Horsnell@arm.com 5472292SN/Atemplate<class Impl> 5487852SMatt.Horsnell@arm.comvoid 5492292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 5507852SMatt.Horsnell@arm.com{ 5517852SMatt.Horsnell@arm.com DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 5522292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5532292SN/A 5542292SN/A toCommit->squash[tid] = true; 5552292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5566221Snate@binkert.org toCommit->nextPC[tid] = inst->readNextPC(); 5572292SN/A 5582292SN/A toCommit->includeSquashInst[tid] = false; 5592292SN/A 5602292SN/A wroteToTimeBuffer = true; 5612292SN/A} 5622292SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5662292SN/A{ 5672292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5682292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5692292SN/A 5702292SN/A toCommit->squash[tid] = true; 5712292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5722292SN/A toCommit->nextPC[tid] = inst->readPC(); 5732292SN/A 5742292SN/A toCommit->includeSquashInst[tid] = true; 5756221Snate@binkert.org 5762292SN/A ldstQueue.setLoadBlockedHandled(tid); 5772292SN/A 5782292SN/A wroteToTimeBuffer = true; 5792292SN/A} 5802292SN/A 5812292SN/Atemplate<class Impl> 5822292SN/Avoid 5832292SN/ADefaultIEW<Impl>::block(unsigned tid) 5842292SN/A{ 5852292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5862292SN/A 5872292SN/A if (dispatchStatus[tid] != Blocked && 5882292SN/A dispatchStatus[tid] != Unblocking) { 5892292SN/A toRename->iewBlock[tid] = true; 5902292SN/A wroteToTimeBuffer = true; 5912292SN/A } 5922292SN/A 5931060SN/A // Add the current inputs to the skid buffer so they can be 5941681SN/A // reprocessed when this stage unblocks. 5951060SN/A skidInsert(tid); 5961060SN/A 5972292SN/A dispatchStatus[tid] = Blocked; 5982292SN/A} 5992292SN/A 6002292SN/Atemplate<class Impl> 6012292SN/Avoid 6022292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 6031681SN/A{ 6041681SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 6051060SN/A "buffer %u.\n",tid, tid); 6062292SN/A 6071060SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 6082292SN/A // Also switch status to running. 6092292SN/A if (skidBuffer[tid].empty()) { 6101060SN/A toRename->iewUnblock[tid] = true; 6112292SN/A wroteToTimeBuffer = true; 6122292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 6132292SN/A dispatchStatus[tid] = Running; 6142292SN/A } 6153221Sktlim@umich.edu} 6163221Sktlim@umich.edu 6173221Sktlim@umich.edutemplate<class Impl> 6183221Sktlim@umich.eduvoid 6193221Sktlim@umich.eduDefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 6202292SN/A{ 6212292SN/A instQueue.wakeDependents(inst); 6222292SN/A} 6232292SN/A 6242326SN/Atemplate<class Impl> 6252292SN/Avoid 6262292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6272820Sktlim@umich.edu{ 6282292SN/A instQueue.rescheduleMemInst(inst); 6292292SN/A} 6302292SN/A 6312292SN/Atemplate<class Impl> 6322292SN/Avoid 6332353SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6342353SN/A{ 6352292SN/A instQueue.replayMemInst(inst); 6362292SN/A} 6372292SN/A 6382292SN/Atemplate<class Impl> 6392292SN/Avoid 6402292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6412292SN/A{ 6422292SN/A // First check the time slot that this instruction will write 6432292SN/A // to. If there are free write ports at the time, then go ahead 6442292SN/A // and write the instruction to that time. If there are not, 6452292SN/A // keep looking back to see where's the first time there's a 6462292SN/A // free slot. 6472731Sktlim@umich.edu while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6482292SN/A ++wbNumInst; 6492292SN/A if (wbNumInst == issueWidth) { 6502292SN/A ++wbCycle; 6512292SN/A wbNumInst = 0; 6522292SN/A } 6532292SN/A 6542292SN/A assert(wbCycle < 5); 6552292SN/A } 6566221Snate@binkert.org 6572292SN/A // Add finished instruction to queue to commit. 6582292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6592292SN/A (*iewQueue)[wbCycle].size++; 6602292SN/A} 6612292SN/A 6622292SN/Atemplate <class Impl> 6632292SN/Aunsigned 6642292SN/ADefaultIEW<Impl>::validInstsFromRename() 6659937SFaissal.Sleiman@arm.com{ 6662292SN/A unsigned inst_count = 0; 6677720Sgblack@eecs.umich.edu 6682292SN/A for (int i=0; i<fromRename->size; i++) { 6692292SN/A if (!fromRename->insts[i]->squashed) 6702292SN/A inst_count++; 6712292SN/A } 6722292SN/A 6732292SN/A return inst_count; 6742292SN/A} 6752292SN/A 6762292SN/Atemplate<class Impl> 6772292SN/Avoid 6782292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6792292SN/A{ 6802292SN/A DynInstPtr inst = NULL; 6812292SN/A 6826221Snate@binkert.org while (!insts[tid].empty()) { 6836221Snate@binkert.org inst = insts[tid].front(); 6842292SN/A 6853867Sbinkertn@umich.edu insts[tid].pop(); 6866221Snate@binkert.org 6873867Sbinkertn@umich.edu DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6882292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6892292SN/A inst->readPC(),tid); 6902292SN/A 6912292SN/A skidBuffer[tid].push(inst); 6922292SN/A } 6932292SN/A 6942292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6952292SN/A "Skidbuffer Exceeded Max Size"); 6962292SN/A} 6972292SN/A 6982292SN/Atemplate<class Impl> 6996221Snate@binkert.orgint 7006221Snate@binkert.orgDefaultIEW<Impl>::skidCount() 7012292SN/A{ 7023867Sbinkertn@umich.edu int max=0; 7036221Snate@binkert.org 7043867Sbinkertn@umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 7053867Sbinkertn@umich.edu 7062292SN/A while (threads != (*activeThreads).end()) { 7072292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 7082292SN/A if (max < thread_count) 7092292SN/A max = thread_count; 7101062SN/A } 7111062SN/A 7121681SN/A return max; 7131062SN/A} 7142292SN/A 7151062SN/Atemplate<class Impl> 7162292SN/Abool 7171062SN/ADefaultIEW<Impl>::skidsEmpty() 7186221Snate@binkert.org{ 7196221Snate@binkert.org list<unsigned>::iterator threads = (*activeThreads).begin(); 7201062SN/A 7213867Sbinkertn@umich.edu while (threads != (*activeThreads).end()) { 7226221Snate@binkert.org if (!skidBuffer[*threads++].empty()) 7231062SN/A return false; 7242292SN/A } 7252292SN/A 7262292SN/A return true; 7272292SN/A} 7282292SN/A 7291062SN/Atemplate <class Impl> 7302292SN/Avoid 7312292SN/ADefaultIEW<Impl>::updateStatus() 7322292SN/A{ 7337897Shestness@cs.utexas.edu bool any_unblocking = false; 7342292SN/A 7352292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7362292SN/A 7371062SN/A threads = (*activeThreads).begin(); 7382292SN/A 7391062SN/A while (threads != (*activeThreads).end()) { 7402292SN/A unsigned tid = *threads++; 7412292SN/A 7422292SN/A if (dispatchStatus[tid] == Unblocking) { 7432292SN/A any_unblocking = true; 7442292SN/A break; 7452292SN/A } 7461062SN/A } 7472292SN/A 7481062SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7492292SN/A // and there's no stores waiting to write back, and dispatch is not 7501062SN/A // unblocking, then there is no internal activity for the IEW stage. 7511062SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7521062SN/A !ldstQueue.willWB() && !any_unblocking) { 7531681SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7541062SN/A 7552292SN/A deactivateStage(); 7561062SN/A 7572292SN/A _status = Inactive; 7582292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7592292SN/A ldstQueue.willWB() || 7601062SN/A any_unblocking)) { 7612292SN/A // Otherwise there is internal activity. Set to active. 7622292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7636221Snate@binkert.org 7642292SN/A activateStage(); 7652292SN/A 7662292SN/A _status = Active; 76710328Smitch.hayenga@arm.com } 7682292SN/A} 7692292SN/A 7702292SN/Atemplate <class Impl> 7712292SN/Avoid 7722292SN/ADefaultIEW<Impl>::resetEntries() 7732292SN/A{ 7742292SN/A instQueue.resetEntries(); 7752292SN/A ldstQueue.resetEntries(); 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7806221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(unsigned tid) 7812292SN/A{ 7822292SN/A if (fromCommit->commitBlock[tid]) { 7832292SN/A stalls[tid].commit = true; 7842292SN/A } 7852292SN/A 7862292SN/A if (fromCommit->commitUnblock[tid]) { 7872292SN/A assert(stalls[tid].commit); 7882292SN/A stalls[tid].commit = false; 7892292SN/A } 7902292SN/A} 7912292SN/A 7922292SN/Atemplate <class Impl> 7932292SN/Abool 7942292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7952292SN/A{ 7962292SN/A bool ret_val(false); 7972292SN/A 7982292SN/A if (stalls[tid].commit) { 7992292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 8002292SN/A ret_val = true; 8012292SN/A } else if (instQueue.isFull(tid)) { 8022292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 8032292SN/A ret_val = true; 8042702Sktlim@umich.edu } else if (ldstQueue.isFull(tid)) { 8052292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 8062292SN/A 8072702Sktlim@umich.edu if (ldstQueue.numLoads(tid) > 0 ) { 8082702Sktlim@umich.edu 8092292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 8102292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8112292SN/A } 8122292SN/A 8132292SN/A if (ldstQueue.numStores(tid) > 0) { 8142292SN/A 8152292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8162292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8172292SN/A } 8182292SN/A 8192292SN/A ret_val = true; 8202292SN/A } else if (ldstQueue.isStalled(tid)) { 8212292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8222292SN/A ret_val = true; 8232292SN/A } 8242292SN/A 8252292SN/A return ret_val; 8262292SN/A} 8272292SN/A 8282292SN/Atemplate <class Impl> 8292292SN/Avoid 8302292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 8312292SN/A{ 8322292SN/A // Check if there's a squash signal, squash if there is 8332292SN/A // Check stall signals, block if there is. 8342292SN/A // If status was Blocked 8352292SN/A // if so then go to unblocking 8362292SN/A // If status was Squashing 8372292SN/A // check if squashing is not high. Switch to running this cycle. 8382292SN/A 8392292SN/A readStallSignals(tid); 8402292SN/A 8412292SN/A if (fromCommit->commitInfo[tid].squash) { 8422292SN/A squash(tid); 8432292SN/A 8442292SN/A if (dispatchStatus[tid] == Blocked || 8452292SN/A dispatchStatus[tid] == Unblocking) { 8462292SN/A toRename->iewUnblock[tid] = true; 8472326SN/A wroteToTimeBuffer = true; 8486221Snate@binkert.org } 8496221Snate@binkert.org 8502326SN/A dispatchStatus[tid] = Squashing; 8512292SN/A 8522292SN/A fetchRedirect[tid] = false; 8532292SN/A return; 8542292SN/A } 8552292SN/A 8562292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8572292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); 8586221Snate@binkert.org 8592702Sktlim@umich.edu dispatchStatus[tid] = Squashing; 8604632Sgblack@eecs.umich.edu 8612935Sksewell@umich.edu return; 8622702Sktlim@umich.edu } 8632935Sksewell@umich.edu 86410239Sbinhpham@cs.rutgers.edu if (checkStall(tid)) { 86510239Sbinhpham@cs.rutgers.edu block(tid); 86610239Sbinhpham@cs.rutgers.edu dispatchStatus[tid] = Blocked; 86710239Sbinhpham@cs.rutgers.edu return; 86810239Sbinhpham@cs.rutgers.edu } 8692702Sktlim@umich.edu 8702702Sktlim@umich.edu if (dispatchStatus[tid] == Blocked) { 8712702Sktlim@umich.edu // Status from previous cycle was blocked, but there are no more stall 8722702Sktlim@umich.edu // conditions. Switch over to unblocking. 8732702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8742702Sktlim@umich.edu tid); 8752702Sktlim@umich.edu 8762702Sktlim@umich.edu dispatchStatus[tid] = Unblocking; 8772702Sktlim@umich.edu 8782702Sktlim@umich.edu unblock(tid); 8792292SN/A 8802292SN/A return; 8812292SN/A } 8822292SN/A 8832292SN/A if (dispatchStatus[tid] == Squashing) { 8842292SN/A // Switch status to running if rename isn't being told to block or 8852292SN/A // squash this cycle. 8862292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8872292SN/A tid); 8882292SN/A 8892292SN/A dispatchStatus[tid] = Running; 8902292SN/A 8912292SN/A return; 8922292SN/A } 8932292SN/A} 8942292SN/A 8952292SN/Atemplate <class Impl> 8962292SN/Avoid 8972733Sktlim@umich.eduDefaultIEW<Impl>::sortInsts() 8982292SN/A{ 8992292SN/A int insts_from_rename = fromRename->size; 9002292SN/A#ifdef DEBUG 9012292SN/A for (int i = 0; i < numThreads; i++) 9022292SN/A assert(insts[i].empty()); 9032292SN/A#endif 9042292SN/A for (int i = 0; i < insts_from_rename; ++i) { 9052733Sktlim@umich.edu insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 9062292SN/A } 9072292SN/A} 9082292SN/A 9092292SN/Atemplate <class Impl> 9106221Snate@binkert.orgvoid 9112292SN/ADefaultIEW<Impl>::wakeCPU() 9122292SN/A{ 9132292SN/A cpu->wakeCPU(); 9142292SN/A} 9152292SN/A 9162292SN/Atemplate <class Impl> 9172292SN/Avoid 9182292SN/ADefaultIEW<Impl>::activityThisCycle() 9192292SN/A{ 9202292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9212292SN/A cpu->activityThisCycle(); 9222292SN/A} 9232292SN/A 9242292SN/Atemplate <class Impl> 9252292SN/Ainline void 9262292SN/ADefaultIEW<Impl>::activateStage() 9272292SN/A{ 9282292SN/A DPRINTF(Activity, "Activating stage.\n"); 9292292SN/A cpu->activateStage(FullCPU::IEWIdx); 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Ainline void 9342292SN/ADefaultIEW<Impl>::deactivateStage() 9352292SN/A{ 9362292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9372292SN/A cpu->deactivateStage(FullCPU::IEWIdx); 9382292SN/A} 9392292SN/A 9402292SN/Atemplate<class Impl> 9412292SN/Avoid 9422292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 9432292SN/A{ 9442292SN/A // If status is Running or idle, 9452292SN/A // call dispatchInsts() 9465215Sgblack@eecs.umich.edu // If status is Unblocking, 9472292SN/A // buffer any instructions coming from rename 9482292SN/A // continue trying to empty skid buffer 9492292SN/A // check if stall conditions have passed 9502292SN/A 9512292SN/A if (dispatchStatus[tid] == Blocked) { 9522292SN/A ++iewBlockCycles; 9532292SN/A 9542292SN/A } else if (dispatchStatus[tid] == Squashing) { 9552292SN/A ++iewSquashCycles; 9562292SN/A } 9572292SN/A 9586221Snate@binkert.org // Dispatch should try to dispatch as many instructions as its bandwidth 9592292SN/A // will allow, as long as it is not currently blocked. 9602292SN/A if (dispatchStatus[tid] == Running || 9612292SN/A dispatchStatus[tid] == Idle) { 9622292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9632292SN/A "dispatch.\n", tid); 9642292SN/A 9652292SN/A dispatchInsts(tid); 9662292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9672292SN/A // Make sure that the skid buffer has something in it if the 9682292SN/A // status is unblocking. 9692292SN/A assert(!skidsEmpty()); 9702292SN/A 9712292SN/A // If the status was unblocking, then instructions from the skid 9722292SN/A // buffer were used. Remove those instructions and handle 9732292SN/A // the rest of unblocking. 9742292SN/A dispatchInsts(tid); 9752820Sktlim@umich.edu 9762292SN/A ++iewUnblockCycles; 9772292SN/A 9782292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9792292SN/A // Add the current inputs to the skid buffer so they can be 9802292SN/A // reprocessed when this stage unblocks. 9812292SN/A skidInsert(tid); 9822292SN/A } 9832292SN/A 9842292SN/A unblock(tid); 9852292SN/A } 9862292SN/A} 9872292SN/A 9887720Sgblack@eecs.umich.edutemplate <class Impl> 9892292SN/Avoid 9907720Sgblack@eecs.umich.eduDefaultIEW<Impl>::dispatchInsts(unsigned tid) 9912292SN/A{ 9922292SN/A dispatchedAllInsts = true; 9932292SN/A 9942292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9952292SN/A // otherwise. 9962292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9972292SN/A dispatchStatus[tid] == Unblocking ? 9982292SN/A skidBuffer[tid] : insts[tid]; 9992292SN/A 10002292SN/A int insts_to_add = insts_to_dispatch.size(); 10012292SN/A 10022292SN/A DynInstPtr inst; 10032292SN/A bool add_to_iq = false; 10042292SN/A int dis_num_inst = 0; 10052292SN/A 100610239Sbinhpham@cs.rutgers.edu // Loop through the instructions, putting them in the instruction 100710239Sbinhpham@cs.rutgers.edu // queue. 10082292SN/A for ( ; dis_num_inst < insts_to_add && 100910239Sbinhpham@cs.rutgers.edu dis_num_inst < issueReadWidth; 101010239Sbinhpham@cs.rutgers.edu ++dis_num_inst) 101110239Sbinhpham@cs.rutgers.edu { 101210239Sbinhpham@cs.rutgers.edu inst = insts_to_dispatch.front(); 10132292SN/A 10142292SN/A if (dispatchStatus[tid] == Unblocking) { 10152292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10162292SN/A "buffer\n", tid); 10172292SN/A } 10182292SN/A 10192292SN/A // Make sure there's a valid instruction there. 10202292SN/A assert(inst); 10212292SN/A 10222292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 10232292SN/A "IQ.\n", 10242292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 10252292SN/A 10262292SN/A // Be sure to mark these instructions as ready so that the 10272292SN/A // commit stage can go ahead and execute them, and mark 10282292SN/A // them as issued so the IQ doesn't reprocess them. 10292292SN/A 10302292SN/A // Check for squashed instructions. 10312292SN/A if (inst->isSquashed()) { 103210240Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 103310240Sbinhpham@cs.rutgers.edu "not adding to IQ.\n", tid); 103410240Sbinhpham@cs.rutgers.edu 103510240Sbinhpham@cs.rutgers.edu ++iewDispSquashedInsts; 103610240Sbinhpham@cs.rutgers.edu 103710240Sbinhpham@cs.rutgers.edu insts_to_dispatch.pop(); 103810240Sbinhpham@cs.rutgers.edu 10392292SN/A //Tell Rename That An Instruction has been processed 10402292SN/A if (inst->isLoad() || inst->isStore()) { 10412292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10422292SN/A } 10432292SN/A toRename->iewInfo[tid].dispatched++; 10442292SN/A 10452292SN/A continue; 10462292SN/A } 10472292SN/A 10482292SN/A // Check for full conditions. 10492292SN/A if (instQueue.isFull(tid)) { 10502292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10512292SN/A 10522292SN/A // Call function to start blocking. 10532292SN/A block(tid); 10542292SN/A 10552292SN/A // Set unblock to false. Special case where we are using 10562292SN/A // skidbuffer (unblocking) instructions but then we still 10572292SN/A // get full in the IQ. 10582292SN/A toRename->iewUnblock[tid] = false; 10592292SN/A 10602292SN/A dispatchedAllInsts = false; 10612292SN/A 10622292SN/A ++iewIQFullEvents; 10632292SN/A break; 10642292SN/A } else if (ldstQueue.isFull(tid)) { 106510239Sbinhpham@cs.rutgers.edu DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10662292SN/A 10672292SN/A // Call function to start blocking. 10682292SN/A block(tid); 10692292SN/A 10702292SN/A // Set unblock to false. Special case where we are using 10712292SN/A // skidbuffer (unblocking) instructions but then we still 10722292SN/A // get full in the IQ. 10732292SN/A toRename->iewUnblock[tid] = false; 10742336SN/A 10752336SN/A dispatchedAllInsts = false; 10762336SN/A 10772336SN/A ++iewLSQFullEvents; 10782348SN/A break; 10792292SN/A } 10802292SN/A 10812292SN/A // Otherwise issue the instruction just fine. 10822292SN/A if (inst->isLoad()) { 10832292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10842292SN/A "encountered, adding to LSQ.\n", tid); 10852292SN/A 10862292SN/A // Reserve a spot in the load store queue for this 10872292SN/A // memory access. 108810239Sbinhpham@cs.rutgers.edu ldstQueue.insertLoad(inst); 10892292SN/A 10902326SN/A ++iewDispLoadInsts; 10912292SN/A 10922292SN/A add_to_iq = true; 10932292SN/A 10942292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10952292SN/A } else if (inst->isStore()) { 10962292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10972292SN/A "encountered, adding to LSQ.\n", tid); 10982292SN/A 10992292SN/A ldstQueue.insertStore(inst); 11002292SN/A 11012292SN/A ++iewDispStoreInsts; 11022326SN/A 11032292SN/A if (inst->isNonSpeculative()) { 11042727Sktlim@umich.edu // Non-speculative stores (namely store conditionals) 11052301SN/A // need to be set as "canCommit()" so that commit can 11062292SN/A // process them when they reach the head of commit. 11072292SN/A inst->setCanCommit(); 11082292SN/A instQueue.insertNonSpec(inst); 11092292SN/A add_to_iq = false; 11102292SN/A 11112292SN/A ++iewDispNonSpecInsts; 11122292SN/A } else { 11132292SN/A add_to_iq = true; 11142292SN/A } 11152326SN/A 11162292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11172292SN/A#if FULL_SYSTEM 11182292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11192292SN/A // Same as non-speculative stores. 11202292SN/A inst->setCanCommit(); 11214033Sktlim@umich.edu instQueue.insertBarrier(inst); 11224033Sktlim@umich.edu add_to_iq = false; 11234033Sktlim@umich.edu#endif 11244033Sktlim@umich.edu } else if (inst->isNonSpeculative()) { 11254033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11264033Sktlim@umich.edu "encountered, skipping.\n", tid); 11274033Sktlim@umich.edu 11284033Sktlim@umich.edu // Same as non-speculative stores. 11294033Sktlim@umich.edu inst->setCanCommit(); 11304033Sktlim@umich.edu 11314033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11324033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11334033Sktlim@umich.edu 11344033Sktlim@umich.edu ++iewDispNonSpecInsts; 11352292SN/A 11362292SN/A add_to_iq = false; 11372292SN/A } else if (inst->isNop()) { 11382292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11392292SN/A "skipping.\n", tid); 11402292SN/A 11412292SN/A inst->setIssued(); 11422292SN/A inst->setExecuted(); 11432292SN/A inst->setCanCommit(); 11442292SN/A 11452292SN/A instQueue.recordProducer(inst); 11462292SN/A 11478471SGiacomo.Gabrielli@arm.com exeNop[tid]++; 11488471SGiacomo.Gabrielli@arm.com 11499046SAli.Saidi@ARM.com add_to_iq = false; 11508471SGiacomo.Gabrielli@arm.com } else if (inst->isExecuted()) { 115110023Smatt.horsnell@ARM.com assert(0 && "Instruction shouldn't be executed.\n"); 11522292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11532292SN/A "skipping.\n"); 11542292SN/A 11552935Sksewell@umich.edu inst->setIssued(); 11562292SN/A inst->setCanCommit(); 11572292SN/A 11582292SN/A instQueue.recordProducer(inst); 11592292SN/A 11602292SN/A add_to_iq = false; 11612292SN/A } else { 11622292SN/A add_to_iq = true; 11632292SN/A } 11642292SN/A 11652292SN/A // If the instruction queue is not full, then add the 11662292SN/A // instruction. 11672292SN/A if (add_to_iq) { 11682292SN/A instQueue.insert(inst); 11692292SN/A } 11702292SN/A 11712292SN/A insts_to_dispatch.pop(); 11722292SN/A 11732292SN/A toRename->iewInfo[tid].dispatched++; 11742292SN/A 11752980Sgblack@eecs.umich.edu ++iewDispatchedInsts; 11762292SN/A } 11772292SN/A 11782292SN/A if (!insts_to_dispatch.empty()) { 11792980Sgblack@eecs.umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11802292SN/A block(tid); 11817720Sgblack@eecs.umich.edu toRename->iewUnblock[tid] = false; 11822292SN/A } 11832292SN/A 11842292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11852292SN/A dispatchStatus[tid] = Running; 11862292SN/A 11872292SN/A updatedQueues = true; 11882292SN/A } 11892980Sgblack@eecs.umich.edu 11902292SN/A dis_num_inst = 0; 11912292SN/A} 11922292SN/A 11932292SN/Atemplate <class Impl> 11942292SN/Avoid 11952292SN/ADefaultIEW<Impl>::printAvailableInsts() 11962292SN/A{ 11972292SN/A int inst = 0; 11982292SN/A 11996221Snate@binkert.org cout << "Available Instructions: "; 12006221Snate@binkert.org 12012292SN/A while (fromIssue->insts[inst]) { 12023867Sbinkertn@umich.edu 12036221Snate@binkert.org if (inst%3==0) cout << "\n\t"; 12042292SN/A 12052292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 12062292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 12072698Sktlim@umich.edu << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12087599Sminkyu.jeong@arm.com 12092698Sktlim@umich.edu inst++; 12101062SN/A 12111062SN/A } 12122333SN/A 12132292SN/A cout << "\n"; 12142333SN/A} 12152326SN/A 12161062SN/Atemplate <class Impl> 12172292SN/Avoid 12181062SN/ADefaultIEW<Impl>::executeInsts() 12192333SN/A{ 12201062SN/A wbNumInst = 0; 12217720Sgblack@eecs.umich.edu wbCycle = 0; 12227720Sgblack@eecs.umich.edu 12231062SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12241062SN/A 12251062SN/A while (threads != (*activeThreads).end()) { 12268315Sgeoffrey.blake@arm.com unsigned tid = *threads++; 12278315Sgeoffrey.blake@arm.com fetchRedirect[tid] = false; 12288315Sgeoffrey.blake@arm.com } 12291062SN/A 12301062SN/A#if 0 12311062SN/A printAvailableInsts(); 12321062SN/A#endif 12331062SN/A 12342292SN/A // Execute/writeback any instructions that are available. 12352292SN/A int insts_to_execute = fromIssue->size; 12362292SN/A int inst_num = 0; 12371062SN/A for (; inst_num < insts_to_execute; 12381062SN/A ++inst_num) { 12391062SN/A 12401062SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12411062SN/A 12421062SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12432292SN/A 12441062SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 12451062SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12461062SN/A 12471062SN/A // Check if the instruction is squashed; if so then skip it 12487850SMatt.Horsnell@arm.com if (inst->isSquashed()) { 12492292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12501062SN/A 12511062SN/A // Consider this instruction executed so that commit can go 12521062SN/A // ahead and retire the instruction. 12531062SN/A inst->setExecuted(); 12542292SN/A 12552292SN/A // Not sure if I should set this here or just let commit try to 12562292SN/A // commit any squashed instructions. I like the latter a bit more. 12577944SGiacomo.Gabrielli@arm.com inst->setCanCommit(); 12587944SGiacomo.Gabrielli@arm.com 12597944SGiacomo.Gabrielli@arm.com ++iewExecSquashedInsts; 12607944SGiacomo.Gabrielli@arm.com 12617944SGiacomo.Gabrielli@arm.com continue; 12627944SGiacomo.Gabrielli@arm.com } 12637944SGiacomo.Gabrielli@arm.com 12647944SGiacomo.Gabrielli@arm.com Fault fault = NoFault; 12657944SGiacomo.Gabrielli@arm.com 12667944SGiacomo.Gabrielli@arm.com // Execute instruction. 12677944SGiacomo.Gabrielli@arm.com // Note that if the instruction faults, it will be handled 12687850SMatt.Horsnell@arm.com // at the commit stage. 12698073SAli.Saidi@ARM.com if (inst->isMemRef() && 12707850SMatt.Horsnell@arm.com (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12711062SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12722367SN/A "reference.\n"); 12731062SN/A 12747944SGiacomo.Gabrielli@arm.com // Tell the LDSTQ to execute this instruction (if it is a load). 12757944SGiacomo.Gabrielli@arm.com if (inst->isLoad()) { 12767944SGiacomo.Gabrielli@arm.com // Loads will mark themselves as executed, and their writeback 12777944SGiacomo.Gabrielli@arm.com // event adds the instruction to the queue to commit 12787944SGiacomo.Gabrielli@arm.com fault = ldstQueue.executeLoad(inst); 12797944SGiacomo.Gabrielli@arm.com } else if (inst->isStore()) { 12807944SGiacomo.Gabrielli@arm.com ldstQueue.executeStore(inst); 12817944SGiacomo.Gabrielli@arm.com 12827944SGiacomo.Gabrielli@arm.com // If the store had a fault then it may not have a mem req 12837944SGiacomo.Gabrielli@arm.com if (inst->req && !(inst->req->flags & LOCKED)) { 12842292SN/A inst->setExecuted(); 128510231Ssteve.reinhardt@amd.com 12867782Sminkyu.jeong@arm.com instToCommit(inst); 12877782Sminkyu.jeong@arm.com } 12887782Sminkyu.jeong@arm.com 12892367SN/A // Store conditionals will mark themselves as 12902367SN/A // executed, and their writeback event will add the 12912367SN/A // instruction to the queue to commit. 12922367SN/A } else { 12932367SN/A panic("Unexpected memory type!\n"); 12942292SN/A } 12952326SN/A 12962326SN/A } else { 12972326SN/A inst->execute(); 12982326SN/A 12991062SN/A inst->setExecuted(); 13002292SN/A 13011062SN/A instToCommit(inst); 13021062SN/A } 13031062SN/A 13047847Sminkyu.jeong@arm.com updateExeInstStats(inst); 13057847Sminkyu.jeong@arm.com 13067847Sminkyu.jeong@arm.com // Check if branch prediction was correct, if not then we need 13077847Sminkyu.jeong@arm.com // to tell commit to squash in flight instructions. Only 13087847Sminkyu.jeong@arm.com // handle this if there hasn't already been something that 13097847Sminkyu.jeong@arm.com // redirects fetch in this group of instructions. 131010231Ssteve.reinhardt@amd.com 13117848SAli.Saidi@ARM.com // This probably needs to prioritize the redirects if a different 13127847Sminkyu.jeong@arm.com // scheduler is used. Currently the scheduler schedules the oldest 13131062SN/A // instruction first, so the branch resolution order will be correct. 13142292SN/A unsigned tid = inst->threadNumber; 13152292SN/A 13162292SN/A if (!fetchRedirect[tid]) { 13171062SN/A 13181062SN/A if (inst->mispredicted()) { 13192301SN/A fetchRedirect[tid] = true; 13201681SN/A 13212326SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13222326SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13232326SN/A inst->nextPC); 13242107SN/A 13251681SN/A // If incorrect, then signal the ROB that it must be squashed. 13262292SN/A squashDueToBranch(inst, tid); 13272292SN/A 13282292SN/A if (inst->predTaken()) { 13296221Snate@binkert.org predictedTakenIncorrect++; 13301062SN/A } else { 13313732Sktlim@umich.edu predictedNotTakenIncorrect++; 13327852SMatt.Horsnell@arm.com } 13333732Sktlim@umich.edu } else if (ldstQueue.violation(tid)) { 13341062SN/A fetchRedirect[tid] = true; 13357856SMatt.Horsnell@arm.com 13367856SMatt.Horsnell@arm.com // If there was an ordering violation, then get the 13377856SMatt.Horsnell@arm.com // DynInst that caused the violation. Note that this 13387856SMatt.Horsnell@arm.com // clears the violation signal. 13397856SMatt.Horsnell@arm.com DynInstPtr violator; 13402292SN/A violator = ldstQueue.getMemDepViolator(tid); 13411062SN/A 13422292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13438674Snilay@cs.wisc.edu "%#x, inst PC: %#x. Addr is: %#x.\n", 13448674Snilay@cs.wisc.edu violator->readPC(), inst->readPC(), inst->physEffAddr); 13457720Sgblack@eecs.umich.edu 13468674Snilay@cs.wisc.edu // Tell the instruction queue that a violation has occured. 13471062SN/A instQueue.violation(inst, violator); 13482292SN/A 13491062SN/A // Squash. 135010023Smatt.horsnell@ARM.com squashDueToMemOrder(inst,tid); 135110023Smatt.horsnell@ARM.com 13523795Sgblack@eecs.umich.edu ++memOrderViolationEvents; 13531062SN/A } else if (ldstQueue.loadBlocked(tid) && 13542292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13552292SN/A fetchRedirect[tid] = true; 13561062SN/A 13572292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13584033Sktlim@umich.edu "memory system is blocked. PC: %#x [sn:%lli]\n", 13592326SN/A inst->readPC(), inst->seqNum); 13602326SN/A 13612292SN/A squashDueToMemBlocked(inst, tid); 13622292SN/A } 13632292SN/A } 13641062SN/A } 13657720Sgblack@eecs.umich.edu 13667720Sgblack@eecs.umich.edu if (inst_num) { 13677720Sgblack@eecs.umich.edu if (exeStatus == Idle) { 13687720Sgblack@eecs.umich.edu exeStatus = Running; 13697720Sgblack@eecs.umich.edu } 13703732Sktlim@umich.edu 13713732Sktlim@umich.edu updatedQueues = true; 13721062SN/A 13731062SN/A cpu->activityThisCycle(); 13741062SN/A } 13751062SN/A 13768513SGiacomo.Gabrielli@arm.com // Need to reset this in case a writeback event needs to write into the 13771062SN/A // iew queue. That way the writeback event will write into the correct 13781062SN/A // spot in the queue. 13792292SN/A wbNumInst = 0; 13802292SN/A} 13812292SN/A 13822292SN/Atemplate <class Impl> 13832292SN/Avoid 13847720Sgblack@eecs.umich.eduDefaultIEW<Impl>::writebackInsts() 13857720Sgblack@eecs.umich.edu{ 13862292SN/A // Loop through the head of the time buffer and wake any 13872292SN/A // dependents. These instructions are about to write back. Also 13881062SN/A // mark scoreboard that this instruction is finally complete. 13894033Sktlim@umich.edu // Either have IEW have direct access to scoreboard, or have this 13904033Sktlim@umich.edu // as part of backwards communication. 13914033Sktlim@umich.edu for (int inst_num = 0; inst_num < issueWidth && 13924033Sktlim@umich.edu toCommit->insts[inst_num]; inst_num++) { 13934033Sktlim@umich.edu DynInstPtr inst = toCommit->insts[inst_num]; 13944033Sktlim@umich.edu int tid = inst->threadNumber; 13954033Sktlim@umich.edu 13964033Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n", 13974033Sktlim@umich.edu inst->readPC()); 13987720Sgblack@eecs.umich.edu 13997720Sgblack@eecs.umich.edu iewInstsToCommit[tid]++; 14007720Sgblack@eecs.umich.edu 14014033Sktlim@umich.edu // Some instructions will be sent to commit without having 14024033Sktlim@umich.edu // executed because they need commit to handle them. 14034033Sktlim@umich.edu // E.g. Uncached loads have not actually executed when they 14044033Sktlim@umich.edu // are first sent to commit. Instead commit must tell the LSQ 14054033Sktlim@umich.edu // when it's ready to execute the uncached load. 14064033Sktlim@umich.edu if (!inst->isSquashed() && inst->isExecuted()) { 14074033Sktlim@umich.edu int dependents = instQueue.wakeDependents(inst); 14084033Sktlim@umich.edu 14097720Sgblack@eecs.umich.edu for (int i = 0; i < inst->numDestRegs(); i++) { 14107720Sgblack@eecs.umich.edu //mark as Ready 14114033Sktlim@umich.edu DPRINTF(IEW,"Setting Destination Register %i\n", 14124033Sktlim@umich.edu inst->renamedDestRegIdx(i)); 14134033Sktlim@umich.edu scoreboard->setReg(inst->renamedDestRegIdx(i)); 14144033Sktlim@umich.edu } 14154033Sktlim@umich.edu 14164033Sktlim@umich.edu producerInst[tid]++; 14171062SN/A consumerInst[tid]+= dependents; 14181062SN/A writebackCount[tid]++; 14192292SN/A } 14202348SN/A } 14212292SN/A} 14222292SN/A 14232292SN/Atemplate<class Impl> 14242292SN/Avoid 14252292SN/ADefaultIEW<Impl>::tick() 14262292SN/A{ 14272292SN/A wbNumInst = 0; 14282292SN/A wbCycle = 0; 14292292SN/A 14302292SN/A wroteToTimeBuffer = false; 14312292SN/A updatedQueues = false; 14322292SN/A 14332292SN/A sortInsts(); 14342292SN/A 14357852SMatt.Horsnell@arm.com // Free function units marked as being freed this cycle. 14362107SN/A fuPool->processFreeUnits(); 14372107SN/A 14382292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 14392107SN/A 14402292SN/A // Check stall and squash signals, dispatch any instructions. 14412107SN/A while (threads != (*activeThreads).end()) { 14422326SN/A unsigned tid = *threads++; 14432326SN/A 14442326SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14452326SN/A 14462326SN/A checkSignalsAndUpdate(tid); 14473958Sgblack@eecs.umich.edu dispatch(tid); 14482292SN/A } 14492107SN/A 14506221Snate@binkert.org if (exeStatus != Squashing) { 14512107SN/A executeInsts(); 14527720Sgblack@eecs.umich.edu 14537720Sgblack@eecs.umich.edu writebackInsts(); 14542107SN/A 14552301SN/A // Have the instruction queue try to schedule any ready instructions. 14562301SN/A // (In actuality, this scheduling is for instructions that will 14572292SN/A // be executed next cycle.) 14582292SN/A instQueue.scheduleReadyInsts(); 14592292SN/A 14602292SN/A // Also should advance its own time buffers if the stage ran. 14612292SN/A // Not the best place for it, but this works (hopefully). 14622367SN/A issueToExecQueue.advance(); 14632301SN/A } 14642107SN/A 14652292SN/A bool broadcast_free_entries = false; 14662292SN/A 14672292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14682292SN/A exeStatus = Idle; 14692292SN/A updateLSQNextCycle = false; 14702107SN/A 14712301SN/A broadcast_free_entries = true; 14722348SN/A } 14732348SN/A 14742348SN/A // Writeback any stores using any leftover bandwidth. 14752348SN/A ldstQueue.writebackStores(); 14762326SN/A 14772107SN/A // Check the committed load/store signals to see if there's a load 14782107SN/A // or store to commit. Also check if it's being told to execute a 14791060SN/A // nonspeculative instruction. 14801060SN/A // This is pretty inefficient... 14811681SN/A 14821060SN/A threads = (*activeThreads).begin(); 14832292SN/A while (threads != (*activeThreads).end()) { 14841060SN/A unsigned tid = (*threads++); 14852292SN/A 14862292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14871060SN/A 14882292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14892292SN/A !fromCommit->commitInfo[tid].squash && 14901060SN/A !fromCommit->commitInfo[tid].robSquashing) { 14912292SN/A 14921060SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14932326SN/A 14942326SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14951062SN/A 14966221Snate@binkert.org updateLSQNextCycle = true; 14976221Snate@binkert.org instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14981060SN/A } 14992326SN/A 15003867Sbinkertn@umich.edu if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15016221Snate@binkert.org 15021060SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15032292SN/A if (fromCommit->commitInfo[tid].uncached) { 15041060SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15052292SN/A } else { 15062292SN/A instQueue.scheduleNonSpec( 15071060SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15081060SN/A } 15092292SN/A } 15102292SN/A 15111060SN/A if (broadcast_free_entries) { 15122292SN/A toFetch->iewInfo[tid].iqCount = 15132292SN/A instQueue.getCount(tid); 15142292SN/A toFetch->iewInfo[tid].ldstqCount = 15152292SN/A ldstQueue.getCount(tid); 15162292SN/A 15172292SN/A toRename->iewInfo[tid].usedIQ = true; 15182292SN/A toRename->iewInfo[tid].freeIQEntries = 15192292SN/A instQueue.numFreeEntries(); 15202292SN/A toRename->iewInfo[tid].usedLSQ = true; 15212292SN/A toRename->iewInfo[tid].freeLSQEntries = 15222292SN/A ldstQueue.numFreeEntries(tid); 15232292SN/A 15242292SN/A wroteToTimeBuffer = true; 15252292SN/A } 15262292SN/A 15272292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15282292SN/A tid, toRename->iewInfo[tid].dispatched); 15292292SN/A } 15302292SN/A 15312292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15322292SN/A "LSQ has %i free entries.\n", 15332292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15341681SN/A ldstQueue.numFreeEntries()); 15351681SN/A 15361061SN/A updateStatus(); 15371061SN/A 15381061SN/A if (wroteToTimeBuffer) { 15391681SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15402292SN/A cpu->activityThisCycle(); 15413867Sbinkertn@umich.edu } 15423867Sbinkertn@umich.edu} 15436221Snate@binkert.org 15442292SN/Atemplate <class Impl> 15452292SN/Avoid 15462292SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15472348SN/A{ 15482292SN/A int thread_number = inst->threadNumber; 15492292SN/A 15502292SN/A // 15512292SN/A // Pick off the software prefetches 15522292SN/A // 15532292SN/A#ifdef TARGET_ALPHA 15542292SN/A if (inst->isDataPrefetch()) 15552292SN/A exeSwp[thread_number]++; 15562292SN/A else 15572292SN/A iewExecutedInsts++; 15582292SN/A#else 15592292SN/A iewExecutedInsts[thread_number]++; 15602292SN/A#endif 15612292SN/A 15622292SN/A // 15632292SN/A // Control operations 15642292SN/A // 15654033Sktlim@umich.edu if (inst->isControl()) 15662292SN/A exeBranches[thread_number]++; 15672292SN/A 15682292SN/A // 15692292SN/A // Memory operations 15702292SN/A // 15712292SN/A if (inst->isMemRef()) { 15722292SN/A exeRefs[thread_number]++; 15732292SN/A 15742292SN/A if (inst->isLoad()) { 15752292SN/A iewExecLoadInsts[thread_number]++; 15762292SN/A } 15772292SN/A } 15782292SN/A} 15792292SN/A