iew_impl.hh revision 2333
11689SN/A/* 27598Sminkyu.jeong@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 67598Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 77598Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 87598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 97598Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 107598Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 117598Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 127598Sminkyu.jeong@arm.com * neither the name of the copyright holders nor the names of its 137598Sminkyu.jeong@arm.com * contributors may be used to endorse or promote products derived from 142326SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291689SN/A// @todo: Fix the instantaneous communication among all the stages within 301689SN/A// iew. There's a clear delay between issue and execute, yet backwards 311689SN/A// communication happens simultaneously. 321689SN/A 331689SN/A#include <queue> 341689SN/A 351689SN/A#include "base/timebuf.hh" 361689SN/A#include "cpu/o3/fu_pool.hh" 371689SN/A#include "cpu/o3/iew.hh" 381689SN/A 392665Ssaidi@eecs.umich.eduusing namespace std; 402665Ssaidi@eecs.umich.edu 411689SN/Atemplate<class Impl> 421689SN/ADefaultIEW<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst, 431060SN/A DefaultIEW<Impl> *_iew) 441060SN/A : Event(&mainEventQueue), inst(_inst), iewStage(_iew) 451689SN/A{ 461060SN/A this->setFlags(Event::AutoDelete); 471060SN/A} 481060SN/A 498230Snate@binkert.orgtemplate<class Impl> 506658Snate@binkert.orgvoid 512292SN/ADefaultIEW<Impl>::LdWritebackEvent::process() 521717SN/A{ 538229Snate@binkert.org DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum); 548232Snate@binkert.org DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 558232Snate@binkert.org 568232Snate@binkert.org //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 575529Snate@binkert.org 581060SN/A if (iewStage->isSwitchedOut()) { 596221Snate@binkert.org inst = NULL; 606221Snate@binkert.org return; 611681SN/A } else if (inst->isSquashed()) { 625529Snate@binkert.org iewStage->wakeCPU(); 632873Sktlim@umich.edu inst = NULL; 644329Sktlim@umich.edu return; 654329Sktlim@umich.edu } 664329Sktlim@umich.edu 672292SN/A iewStage->wakeCPU(); 682292SN/A 692292SN/A if (!inst->isExecuted()) { 702292SN/A inst->setExecuted(); 712820Sktlim@umich.edu 722292SN/A // Complete access to copy data to proper place. 732820Sktlim@umich.edu if (inst->isStore()) { 742820Sktlim@umich.edu inst->completeAcc(); 755529Snate@binkert.org } 762307SN/A } 771060SN/A 782292SN/A // Need to insert instruction into queue to commit 792292SN/A iewStage->instToCommit(inst); 802292SN/A 811060SN/A iewStage->activityThisCycle(); 821060SN/A 831060SN/A inst = NULL; 841060SN/A} 851060SN/A 861060SN/Atemplate<class Impl> 871681SN/Aconst char * 886221Snate@binkert.orgDefaultIEW<Impl>::LdWritebackEvent::description() 896221Snate@binkert.org{ 906221Snate@binkert.org return "Load writeback event"; 916221Snate@binkert.org} 922292SN/A 932292SN/Atemplate<class Impl> 942820Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(Params *params) 952820Sktlim@umich.edu : // @todo: Make this into a parameter. 962292SN/A issueToExecQueue(5, 5), 972292SN/A instQueue(params), 982820Sktlim@umich.edu ldstQueue(params), 992820Sktlim@umich.edu fuPool(params->fuPool), 1002292SN/A commitToIEWDelay(params->commitToIEWDelay), 1012292SN/A renameToIEWDelay(params->renameToIEWDelay), 1022292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 1032292SN/A issueReadWidth(params->issueWidth), 1042292SN/A issueWidth(params->issueWidth), 1052292SN/A executeWidth(params->executeWidth), 1062292SN/A numThreads(params->numberOfThreads), 1072292SN/A switchedOut(false) 1081060SN/A{ 1091060SN/A _status = Active; 1101681SN/A exeStatus = Running; 1111062SN/A wbStatus = Idle; 1122292SN/A 1131062SN/A // Setup wire to read instructions coming from issue. 1142301SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 1152301SN/A 1161062SN/A // Instruction queue needs the queue between issue and execute. 1172727Sktlim@umich.edu instQueue.setIssueToExecuteQueue(&issueToExecQueue); 1181062SN/A 1191062SN/A instQueue.setIEW(this); 1201062SN/A ldstQueue.setIEW(this); 1211062SN/A 1221062SN/A for (int i=0; i < numThreads; i++) { 1231062SN/A dispatchStatus[i] = Running; 1241062SN/A stalls[i].commit = false; 1251062SN/A fetchRedirect[i] = false; 1261062SN/A } 1271062SN/A 1281062SN/A updateLSQNextCycle = false; 1291062SN/A 1301062SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1311062SN/A} 1321062SN/A 1331062SN/Atemplate <class Impl> 1341062SN/Astd::string 1351062SN/ADefaultIEW<Impl>::name() const 1361062SN/A{ 1371062SN/A return cpu->name() + ".iew"; 1381062SN/A} 1391062SN/A 1401062SN/Atemplate <class Impl> 1411062SN/Avoid 1421062SN/ADefaultIEW<Impl>::regStats() 1431062SN/A{ 1441062SN/A using namespace Stats; 1451062SN/A 1461062SN/A instQueue.regStats(); 1471062SN/A 1481062SN/A iewIdleCycles 1491062SN/A .name(name() + ".iewIdleCycles") 1501062SN/A .desc("Number of cycles IEW is idle"); 1511062SN/A 1521062SN/A iewSquashCycles 1531062SN/A .name(name() + ".iewSquashCycles") 1541062SN/A .desc("Number of cycles IEW is squashing"); 1551062SN/A 1561062SN/A iewBlockCycles 1571062SN/A .name(name() + ".iewBlockCycles") 1581062SN/A .desc("Number of cycles IEW is blocking"); 1592292SN/A 1602292SN/A iewUnblockCycles 1612292SN/A .name(name() + ".iewUnblockCycles") 1622292SN/A .desc("Number of cycles IEW is unblocking"); 1631062SN/A 1641062SN/A iewDispatchedInsts 1651062SN/A .name(name() + ".iewDispatchedInsts") 1661062SN/A .desc("Number of instructions dispatched to IQ"); 1671062SN/A 1681062SN/A iewDispSquashedInsts 1691062SN/A .name(name() + ".iewDispSquashedInsts") 1702292SN/A .desc("Number of squashed instructions skipped by dispatch"); 1712292SN/A 1722292SN/A iewDispLoadInsts 1732292SN/A .name(name() + ".iewDispLoadInsts") 1742292SN/A .desc("Number of dispatched load instructions"); 1752292SN/A 1762292SN/A iewDispStoreInsts 1772292SN/A .name(name() + ".iewDispStoreInsts") 1782292SN/A .desc("Number of dispatched store instructions"); 1792292SN/A 1802301SN/A iewDispNonSpecInsts 1812727Sktlim@umich.edu .name(name() + ".iewDispNonSpecInsts") 1822353SN/A .desc("Number of dispatched non-speculative instructions"); 1832727Sktlim@umich.edu 1842727Sktlim@umich.edu iewIQFullEvents 1852727Sktlim@umich.edu .name(name() + ".iewIQFullEvents") 1866221Snate@binkert.org .desc("Number of times the IQ has become full, causing a stall"); 1872353SN/A 1882727Sktlim@umich.edu iewLSQFullEvents 1892727Sktlim@umich.edu .name(name() + ".iewLSQFullEvents") 1902727Sktlim@umich.edu .desc("Number of times the LSQ has become full, causing a stall"); 1912727Sktlim@umich.edu 1922353SN/A iewExecutedInsts 1932727Sktlim@umich.edu .name(name() + ".iewExecutedInsts") 1942727Sktlim@umich.edu .desc("Number of executed instructions"); 1952727Sktlim@umich.edu 1966221Snate@binkert.org iewExecLoadInsts 1978240Snate@binkert.org .init(cpu->number_of_threads) 1982301SN/A .name(name() + ".iewExecLoadInsts") 1992727Sktlim@umich.edu .desc("Number of load instructions executed") 2002301SN/A .flags(total); 2012727Sktlim@umich.edu 2026221Snate@binkert.org iewExecSquashedInsts 2038240Snate@binkert.org .name(name() + ".iewExecSquashedInsts") 2042301SN/A .desc("Number of squashed instructions skipped in execute"); 2052727Sktlim@umich.edu 2062301SN/A memOrderViolationEvents 2072727Sktlim@umich.edu .name(name() + ".memOrderViolationEvents") 2086221Snate@binkert.org .desc("Number of memory order violations"); 2098240Snate@binkert.org 2102301SN/A predictedTakenIncorrect 2112727Sktlim@umich.edu .name(name() + ".predictedTakenIncorrect") 2122301SN/A .desc("Number of branches that were predicted taken incorrectly"); 2132727Sktlim@umich.edu 2146221Snate@binkert.org predictedNotTakenIncorrect 2158240Snate@binkert.org .name(name() + ".predictedNotTakenIncorrect") 2162301SN/A .desc("Number of branches that were predicted not taken incorrectly"); 2172727Sktlim@umich.edu 2182301SN/A branchMispredicts 2192301SN/A .name(name() + ".branchMispredicts") 2208240Snate@binkert.org .desc("Number of branch mispredicts detected at execute"); 2212301SN/A 2222727Sktlim@umich.edu branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 2232727Sktlim@umich.edu 2242727Sktlim@umich.edu exeSwp 2252727Sktlim@umich.edu .init(cpu->number_of_threads) 2268240Snate@binkert.org .name(name() + ".EXEC:swp") 2272727Sktlim@umich.edu .desc("number of swp insts executed") 2282727Sktlim@umich.edu .flags(total) 2292727Sktlim@umich.edu ; 2302727Sktlim@umich.edu 2312301SN/A exeNop 2322301SN/A .init(cpu->number_of_threads) 2336221Snate@binkert.org .name(name() + ".EXEC:nop") 2348240Snate@binkert.org .desc("number of nop insts executed") 2352301SN/A .flags(total) 2362727Sktlim@umich.edu ; 2372301SN/A 2382326SN/A exeRefs 2396221Snate@binkert.org .init(cpu->number_of_threads) 2408240Snate@binkert.org .name(name() + ".EXEC:refs") 2412301SN/A .desc("number of memory reference insts executed") 2422727Sktlim@umich.edu .flags(total) 2432301SN/A ; 2442326SN/A 2456221Snate@binkert.org exeBranches 2468240Snate@binkert.org .init(cpu->number_of_threads) 2472301SN/A .name(name() + ".EXEC:branches") 2482727Sktlim@umich.edu .desc("Number of branches executed") 2492301SN/A .flags(total) 2502326SN/A ; 2516221Snate@binkert.org 2528240Snate@binkert.org issueRate 2532301SN/A .name(name() + ".EXEC:rate") 2542727Sktlim@umich.edu .desc("Inst execution rate") 2552301SN/A .flags(total) 2562326SN/A ; 2576221Snate@binkert.org issueRate = iewExecutedInsts / cpu->numCycles; 2588240Snate@binkert.org 2592301SN/A iewExecStoreInsts 2602727Sktlim@umich.edu .name(name() + ".EXEC:stores") 2612301SN/A .desc("Number of stores executed") 2622326SN/A .flags(total) 2638240Snate@binkert.org ; 2642301SN/A iewExecStoreInsts = exeRefs - iewExecLoadInsts; 2652727Sktlim@umich.edu/* 2662301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2672326SN/A stringstream subname; 2682301SN/A subname << opClassStrings[i] << "_delay"; 2692326SN/A issue_delay_dist.subname(i, subname.str()); 2708240Snate@binkert.org } 2712301SN/A*/ 2722727Sktlim@umich.edu // 2732301SN/A // Other stats 2742326SN/A // 2752301SN/A 2762326SN/A iewInstsToCommit 2778240Snate@binkert.org .init(cpu->number_of_threads) 2782301SN/A .name(name() + ".WB:sent") 2792727Sktlim@umich.edu .desc("cumulative count of insts sent to commit") 2802326SN/A .flags(total) 2811062SN/A ; 2821062SN/A 2831681SN/A writebackCount 2841060SN/A .init(cpu->number_of_threads) 2852292SN/A .name(name() + ".WB:count") 2861060SN/A .desc("cumulative count of insts written-back") 2876221Snate@binkert.org .flags(total) 2882292SN/A ; 2892292SN/A 2902292SN/A producerInst 2912292SN/A .init(cpu->number_of_threads) 2922292SN/A .name(name() + ".WB:producers") 2932292SN/A .desc("num instructions producing a value") 2942292SN/A .flags(total) 2952292SN/A ; 2962292SN/A 2972733Sktlim@umich.edu consumerInst 2981060SN/A .init(cpu->number_of_threads) 2991060SN/A .name(name() + ".WB:consumers") 3001681SN/A .desc("num instructions consuming a value") 3011060SN/A .flags(total) 3022292SN/A ; 3031060SN/A 3041060SN/A wbPenalized 3051060SN/A .init(cpu->number_of_threads) 3061060SN/A .name(name() + ".WB:penalized") 3071060SN/A .desc("number of instrctions required to write to 'other' IQ") 3081060SN/A .flags(total) 3091060SN/A ; 3101060SN/A 3111060SN/A wbPenalizedRate 3122292SN/A .name(name() + ".WB:penalized_rate") 3132292SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 3141060SN/A .flags(total) 3151060SN/A ; 3161060SN/A 3171060SN/A wbPenalizedRate = wbPenalized / writebackCount; 3181681SN/A 3191060SN/A wbFanout 3202292SN/A .name(name() + ".WB:fanout") 3211060SN/A .desc("average fanout of values written-back") 3221060SN/A .flags(total) 3231060SN/A ; 3241060SN/A 3251060SN/A wbFanout = producerInst / consumerInst; 3261060SN/A 3271060SN/A wbRate 3281681SN/A .name(name() + ".WB:rate") 3291060SN/A .desc("insts written-back per cycle") 3302292SN/A .flags(total) 3311060SN/A ; 3321060SN/A wbRate = writebackCount / cpu->numCycles; 3331060SN/A} 3341060SN/A 3351060SN/Atemplate<class Impl> 3361060SN/Avoid 3371060SN/ADefaultIEW<Impl>::initStage() 3381681SN/A{ 3391060SN/A for (int tid=0; tid < numThreads; tid++) { 3406221Snate@binkert.org toRename->iewInfo[tid].usedIQ = true; 3411060SN/A toRename->iewInfo[tid].freeIQEntries = 3422292SN/A instQueue.numFreeEntries(tid); 3432292SN/A 3442292SN/A toRename->iewInfo[tid].usedLSQ = true; 3452292SN/A toRename->iewInfo[tid].freeLSQEntries = 3461060SN/A ldstQueue.numFreeEntries(tid); 3471060SN/A } 3481681SN/A} 3491060SN/A 3502292SN/Atemplate<class Impl> 3511060SN/Avoid 3522292SN/ADefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 3531060SN/A{ 3541060SN/A DPRINTF(IEW, "Setting CPU pointer.\n"); 3552307SN/A cpu = cpu_ptr; 3562863Sktlim@umich.edu 3572843Sktlim@umich.edu instQueue.setCPU(cpu_ptr); 3582307SN/A ldstQueue.setCPU(cpu_ptr); 3592843Sktlim@umich.edu 3602843Sktlim@umich.edu cpu->activateStage(FullCPU::IEWIdx); 3612863Sktlim@umich.edu} 3621681SN/A 3631681SN/Atemplate<class Impl> 3642316SN/Avoid 3651681SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3662843Sktlim@umich.edu{ 3672843Sktlim@umich.edu DPRINTF(IEW, "Setting time buffer pointer.\n"); 3682843Sktlim@umich.edu timeBuffer = tb_ptr; 3692843Sktlim@umich.edu 3702843Sktlim@umich.edu // Setup wire to read information from time buffer, from commit. 3712843Sktlim@umich.edu fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3722843Sktlim@umich.edu 3731681SN/A // Setup wire to write information back to previous stages. 3742348SN/A toRename = timeBuffer->getWire(0); 3752307SN/A 3762367SN/A toFetch = timeBuffer->getWire(0); 3772367SN/A 3781681SN/A // Instruction queue also needs main time buffer. 3792307SN/A instQueue.setTimeBuffer(tb_ptr); 3802307SN/A} 3812307SN/A 3822307SN/Atemplate<class Impl> 3836221Snate@binkert.orgvoid 3846221Snate@binkert.orgDefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3856221Snate@binkert.org{ 3866221Snate@binkert.org DPRINTF(IEW, "Setting rename queue pointer.\n"); 3876221Snate@binkert.org renameQueue = rq_ptr; 3882307SN/A 3891681SN/A // Setup wire to read information from rename queue. 3901681SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3912307SN/A} 3921681SN/A 3932307SN/Atemplate<class Impl> 3941060SN/Avoid 3952348SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3962307SN/A{ 3972307SN/A DPRINTF(IEW, "Setting IEW queue pointer.\n"); 3982307SN/A iewQueue = iq_ptr; 3992307SN/A 4001060SN/A // Setup wire to write instructions to commit. 4012307SN/A toCommit = iewQueue->getWire(0); 4022307SN/A} 4032307SN/A 4041060SN/Atemplate<class Impl> 4052307SN/Avoid 4062307SN/ADefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 4071060SN/A{ 4086221Snate@binkert.org DPRINTF(IEW, "Setting active threads list pointer.\n"); 4096221Snate@binkert.org activeThreads = at_ptr; 4106221Snate@binkert.org 4116221Snate@binkert.org ldstQueue.setActiveThreads(at_ptr); 4122307SN/A instQueue.setActiveThreads(at_ptr); 4131060SN/A} 4142307SN/A 4152307SN/Atemplate<class Impl> 4162873Sktlim@umich.eduvoid 4172307SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 4181060SN/A{ 4191060SN/A DPRINTF(IEW, "Setting scoreboard pointer.\n"); 4201060SN/A scoreboard = sb_ptr; 4211681SN/A} 4221060SN/A 4236221Snate@binkert.org#if 0 4242107SN/Atemplate<class Impl> 4256221Snate@binkert.orgvoid 4262107SN/ADefaultIEW<Impl>::setPageTable(PageTable *pt_ptr) 4272292SN/A{ 4282292SN/A ldstQueue.setPageTable(pt_ptr); 4292107SN/A} 4302292SN/A#endif 4312326SN/A 4322292SN/Atemplate <class Impl> 4332107SN/Avoid 4342292SN/ADefaultIEW<Impl>::switchOut() 4352935Sksewell@umich.edu{ 4364632Sgblack@eecs.umich.edu cpu->signalSwitched(); 4372935Sksewell@umich.edu} 4382292SN/A 4392292SN/Atemplate <class Impl> 4402292SN/Avoid 4412292SN/ADefaultIEW<Impl>::doSwitchOut() 4422292SN/A{ 4432107SN/A switchedOut = true; 4442292SN/A 4452107SN/A instQueue.switchOut(); 4462292SN/A ldstQueue.switchOut(); 4472292SN/A fuPool->switchOut(); 4482107SN/A 4492702Sktlim@umich.edu for (int i = 0; i < numThreads; i++) { 4502107SN/A while (!insts[i].empty()) 4512107SN/A insts[i].pop(); 4522107SN/A while (!skidBuffer[i].empty()) 4532107SN/A skidBuffer[i].pop(); 4546221Snate@binkert.org } 4552292SN/A} 4567720Sgblack@eecs.umich.edu 4577720Sgblack@eecs.umich.edutemplate <class Impl> 4582292SN/Avoid 4597852SMatt.Horsnell@arm.comDefaultIEW<Impl>::takeOverFrom() 4607852SMatt.Horsnell@arm.com{ 4617852SMatt.Horsnell@arm.com _status = Active; 4627852SMatt.Horsnell@arm.com exeStatus = Running; 4637852SMatt.Horsnell@arm.com wbStatus = Idle; 4642935Sksewell@umich.edu switchedOut = false; 4657852SMatt.Horsnell@arm.com 4667852SMatt.Horsnell@arm.com instQueue.takeOverFrom(); 4672292SN/A ldstQueue.takeOverFrom(); 4687852SMatt.Horsnell@arm.com fuPool->takeOverFrom(); 4697852SMatt.Horsnell@arm.com 4707852SMatt.Horsnell@arm.com initStage(); 4712292SN/A cpu->activityThisCycle(); 4727852SMatt.Horsnell@arm.com 4737852SMatt.Horsnell@arm.com for (int i=0; i < numThreads; i++) { 4747852SMatt.Horsnell@arm.com dispatchStatus[i] = Running; 4752292SN/A stalls[i].commit = false; 4762292SN/A fetchRedirect[i] = false; 4772292SN/A } 4782292SN/A 4796221Snate@binkert.org updateLSQNextCycle = false; 4802292SN/A 4818513SGiacomo.Gabrielli@arm.com // @todo: Fix hardcoded number 4828513SGiacomo.Gabrielli@arm.com for (int i = 0; i < 6; ++i) { 4838513SGiacomo.Gabrielli@arm.com issueToExecQueue.advance(); 4848513SGiacomo.Gabrielli@arm.com } 4858513SGiacomo.Gabrielli@arm.com} 4868513SGiacomo.Gabrielli@arm.com 4878513SGiacomo.Gabrielli@arm.comtemplate<class Impl> 4888513SGiacomo.Gabrielli@arm.comvoid 4898513SGiacomo.Gabrielli@arm.comDefaultIEW<Impl>::squash(unsigned tid) 4908513SGiacomo.Gabrielli@arm.com{ 4918513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4922292SN/A tid); 4937852SMatt.Horsnell@arm.com 4948513SGiacomo.Gabrielli@arm.com // Tell the IQ to start squashing. 4958137SAli.Saidi@ARM.com instQueue.squash(tid); 4962292SN/A 4978513SGiacomo.Gabrielli@arm.com // Tell the LDSTQ to start squashing. 4988513SGiacomo.Gabrielli@arm.com ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4992292SN/A 5007852SMatt.Horsnell@arm.com updatedQueues = true; 5017852SMatt.Horsnell@arm.com 5022292SN/A // Clear the skid buffer in case it has any data in it. 5032292SN/A while (!skidBuffer[tid].empty()) { 5042292SN/A 5052292SN/A if (skidBuffer[tid].front()->isLoad() || 5066221Snate@binkert.org skidBuffer[tid].front()->isStore() ) { 5072292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 5082292SN/A } 5097720Sgblack@eecs.umich.edu 5107852SMatt.Horsnell@arm.com toRename->iewInfo[tid].dispatched++; 5117852SMatt.Horsnell@arm.com 5127852SMatt.Horsnell@arm.com skidBuffer[tid].pop(); 5132292SN/A } 5147852SMatt.Horsnell@arm.com 5157852SMatt.Horsnell@arm.com while (!insts[tid].empty()) { 5168137SAli.Saidi@ARM.com if (insts[tid].front()->isLoad() || 5172292SN/A insts[tid].front()->isStore() ) { 5187852SMatt.Horsnell@arm.com toRename->iewInfo[tid].dispatchedToLSQ++; 5197852SMatt.Horsnell@arm.com } 5202292SN/A 5217852SMatt.Horsnell@arm.com toRename->iewInfo[tid].dispatched++; 5222292SN/A 5237852SMatt.Horsnell@arm.com insts[tid].pop(); 5247852SMatt.Horsnell@arm.com } 5252292SN/A} 5262292SN/A 5272292SN/Atemplate<class Impl> 5282292SN/Avoid 5296221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 5302292SN/A{ 5312292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 5322292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5332292SN/A 5342292SN/A toCommit->squash[tid] = true; 5352292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5362292SN/A toCommit->mispredPC[tid] = inst->readPC(); 5372292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5382292SN/A toCommit->branchMispredict[tid] = true; 5392292SN/A toCommit->branchTaken[tid] = inst->readNextPC() != 5402292SN/A (inst->readPC() + sizeof(TheISA::MachInst)); 5412292SN/A 5422292SN/A toCommit->includeSquashInst[tid] = false; 5432292SN/A 5442292SN/A wroteToTimeBuffer = true; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate<class Impl> 5486221Snate@binkert.orgvoid 5492292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 5502292SN/A{ 5512292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 5522292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5532292SN/A 5542292SN/A toCommit->squash[tid] = true; 5552292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5562292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 5572292SN/A 5582292SN/A toCommit->includeSquashInst[tid] = false; 5592292SN/A 5602292SN/A wroteToTimeBuffer = true; 5612292SN/A} 5622292SN/A 5632292SN/Atemplate<class Impl> 5642292SN/Avoid 5652292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 5661060SN/A{ 5671681SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5681060SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 5691060SN/A 5702292SN/A toCommit->squash[tid] = true; 5712292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 5722292SN/A toCommit->nextPC[tid] = inst->readPC(); 5732292SN/A 5742292SN/A toCommit->includeSquashInst[tid] = true; 5752292SN/A 5761681SN/A ldstQueue.setLoadBlockedHandled(tid); 5771681SN/A 5781060SN/A wroteToTimeBuffer = true; 5792292SN/A} 5801060SN/A 5812292SN/Atemplate<class Impl> 5822292SN/Avoid 5831060SN/ADefaultIEW<Impl>::block(unsigned tid) 5842292SN/A{ 5852292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5862292SN/A 5872292SN/A if (dispatchStatus[tid] != Blocked && 5883221Sktlim@umich.edu dispatchStatus[tid] != Unblocking) { 5893221Sktlim@umich.edu toRename->iewBlock[tid] = true; 5903221Sktlim@umich.edu wroteToTimeBuffer = true; 5913221Sktlim@umich.edu } 5923221Sktlim@umich.edu 5932292SN/A // Add the current inputs to the skid buffer so they can be 5942292SN/A // reprocessed when this stage unblocks. 5952292SN/A skidInsert(tid); 5962292SN/A 5972326SN/A dispatchStatus[tid] = Blocked; 5982292SN/A} 5992292SN/A 6002820Sktlim@umich.edutemplate<class Impl> 6012292SN/Avoid 6022292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 6032292SN/A{ 6042292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 6052353SN/A "buffer %u.\n",tid, tid); 6062292SN/A 6072292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 6082353SN/A // Also switch status to running. 6092353SN/A if (skidBuffer[tid].empty()) { 6102292SN/A toRename->iewUnblock[tid] = true; 6112292SN/A wroteToTimeBuffer = true; 6122292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 6132292SN/A dispatchStatus[tid] = Running; 6142292SN/A } 6152292SN/A} 6162292SN/A 6172292SN/Atemplate<class Impl> 6182292SN/Avoid 6192292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 6202292SN/A{ 6212292SN/A instQueue.wakeDependents(inst); 6222731Sktlim@umich.edu} 6232292SN/A 6242292SN/Atemplate<class Impl> 6252292SN/Avoid 6262292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 6272292SN/A{ 6282292SN/A instQueue.rescheduleMemInst(inst); 6292292SN/A} 6302292SN/A 6316221Snate@binkert.orgtemplate<class Impl> 6322292SN/Avoid 6332292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 6342292SN/A{ 6352292SN/A instQueue.replayMemInst(inst); 6362292SN/A} 6372292SN/A 6382292SN/Atemplate<class Impl> 6392292SN/Avoid 6407720Sgblack@eecs.umich.eduDefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 6412292SN/A{ 6427720Sgblack@eecs.umich.edu // First check the time slot that this instruction will write 6432292SN/A // to. If there are free write ports at the time, then go ahead 6442292SN/A // and write the instruction to that time. If there are not, 6452292SN/A // keep looking back to see where's the first time there's a 6462292SN/A // free slot. 6472292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6482292SN/A ++wbNumInst; 6492292SN/A if (wbNumInst == issueWidth) { 6502292SN/A ++wbCycle; 6512292SN/A wbNumInst = 0; 6522292SN/A } 6532292SN/A 6542292SN/A assert(wbCycle < 5); 6552292SN/A } 6562292SN/A 6576221Snate@binkert.org // Add finished instruction to queue to commit. 6586221Snate@binkert.org (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6592292SN/A (*iewQueue)[wbCycle].size++; 6603867Sbinkertn@umich.edu} 6616221Snate@binkert.org 6623867Sbinkertn@umich.edutemplate <class Impl> 6632292SN/Aunsigned 6642292SN/ADefaultIEW<Impl>::validInstsFromRename() 6652292SN/A{ 6662292SN/A unsigned inst_count = 0; 6672292SN/A 6682292SN/A for (int i=0; i<fromRename->size; i++) { 6692292SN/A if (!fromRename->insts[i]->squashed) 6702292SN/A inst_count++; 6712292SN/A } 6722292SN/A 6732292SN/A return inst_count; 6746221Snate@binkert.org} 6756221Snate@binkert.org 6762292SN/Atemplate<class Impl> 6773867Sbinkertn@umich.eduvoid 6786221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(unsigned tid) 6793867Sbinkertn@umich.edu{ 6803867Sbinkertn@umich.edu DynInstPtr inst = NULL; 6812292SN/A 6822292SN/A while (!insts[tid].empty()) { 6832292SN/A inst = insts[tid].front(); 6842292SN/A 6851062SN/A insts[tid].pop(); 6861062SN/A 6871681SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6881062SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6892292SN/A inst->readPC(),tid); 6901062SN/A 6912292SN/A skidBuffer[tid].push(inst); 6921062SN/A } 6936221Snate@binkert.org 6946221Snate@binkert.org assert(skidBuffer[tid].size() <= skidBufferMax && 6951062SN/A "Skidbuffer Exceeded Max Size"); 6963867Sbinkertn@umich.edu} 6976221Snate@binkert.org 6981062SN/Atemplate<class Impl> 6992292SN/Aint 7002292SN/ADefaultIEW<Impl>::skidCount() 7012292SN/A{ 7022292SN/A int max=0; 7032292SN/A 7041062SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7052292SN/A 7062292SN/A while (threads != (*activeThreads).end()) { 7072292SN/A unsigned thread_count = skidBuffer[*threads++].size(); 7087897Shestness@cs.utexas.edu if (max < thread_count) 7092292SN/A max = thread_count; 7102292SN/A } 7112292SN/A 7121062SN/A return max; 7132292SN/A} 7141062SN/A 7152292SN/Atemplate<class Impl> 7162292SN/Abool 7172292SN/ADefaultIEW<Impl>::skidsEmpty() 7182292SN/A{ 7192292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7202292SN/A 7211062SN/A while (threads != (*activeThreads).end()) { 7222292SN/A if (!skidBuffer[*threads++].empty()) 7231062SN/A return false; 7242292SN/A } 7251062SN/A 7261062SN/A return true; 7271062SN/A} 7281681SN/A 7291062SN/Atemplate <class Impl> 7302292SN/Avoid 7311062SN/ADefaultIEW<Impl>::updateStatus() 7322292SN/A{ 7332292SN/A bool any_unblocking = false; 7342292SN/A 7351062SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7362292SN/A 7372292SN/A threads = (*activeThreads).begin(); 7386221Snate@binkert.org 7392292SN/A while (threads != (*activeThreads).end()) { 7402292SN/A unsigned tid = *threads++; 7412292SN/A 7422292SN/A if (dispatchStatus[tid] == Unblocking) { 7431062SN/A any_unblocking = true; 7442292SN/A break; 7452292SN/A } 7462292SN/A } 7472292SN/A 7482292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7492292SN/A // and there's no stores waiting to write back, and dispatch is not 7502292SN/A // unblocking, then there is no internal activity for the IEW stage. 7512292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7526221Snate@binkert.org !ldstQueue.willWB() && !any_unblocking) { 7532292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7542292SN/A 7552292SN/A deactivateStage(); 7562292SN/A 7572292SN/A _status = Inactive; 7582292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7592292SN/A ldstQueue.willWB() || 7602292SN/A any_unblocking)) { 7612292SN/A // Otherwise there is internal activity. Set to active. 7622292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7632292SN/A 7642292SN/A activateStage(); 7652292SN/A 7662292SN/A _status = Active; 7672292SN/A } 7682292SN/A} 7692292SN/A 7702292SN/Atemplate <class Impl> 7712292SN/Avoid 7722292SN/ADefaultIEW<Impl>::resetEntries() 7732292SN/A{ 7742292SN/A instQueue.resetEntries(); 7752292SN/A ldstQueue.resetEntries(); 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7802292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7812292SN/A{ 7822292SN/A if (fromCommit->commitBlock[tid]) { 7832292SN/A stalls[tid].commit = true; 7842292SN/A } 7852292SN/A 7862292SN/A if (fromCommit->commitUnblock[tid]) { 7872292SN/A assert(stalls[tid].commit); 7886221Snate@binkert.org stalls[tid].commit = false; 7892292SN/A } 7902292SN/A} 7912292SN/A 7922292SN/Atemplate <class Impl> 7932292SN/Abool 7942292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7952292SN/A{ 7962292SN/A bool ret_val(false); 7972292SN/A 7982292SN/A if (stalls[tid].commit) { 7992292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 8002292SN/A ret_val = true; 8012292SN/A } else if (instQueue.isFull(tid)) { 8022292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 8032292SN/A ret_val = true; 8042292SN/A } else if (ldstQueue.isFull(tid)) { 8052292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 8062292SN/A 8072292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 8082292SN/A 8092292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 8102292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 8112292SN/A } 8122292SN/A 8132292SN/A if (ldstQueue.numStores(tid) > 0) { 8142702Sktlim@umich.edu 8152292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 8162292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 8172702Sktlim@umich.edu } 8182702Sktlim@umich.edu 8192292SN/A ret_val = true; 8202292SN/A } else if (ldstQueue.isStalled(tid)) { 8212292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 8222292SN/A ret_val = true; 8232292SN/A } 8242292SN/A 8252292SN/A return ret_val; 8262292SN/A} 8272292SN/A 8282292SN/Atemplate <class Impl> 8292292SN/Avoid 8302292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 8312292SN/A{ 8322292SN/A // Check if there's a squash signal, squash if there is 8332292SN/A // Check stall signals, block if there is. 8342292SN/A // If status was Blocked 8352292SN/A // if so then go to unblocking 8362292SN/A // If status was Squashing 8372292SN/A // check if squashing is not high. Switch to running this cycle. 8382292SN/A 8392292SN/A readStallSignals(tid); 8402292SN/A 8412292SN/A if (fromCommit->commitInfo[tid].squash) { 8422292SN/A squash(tid); 8432292SN/A 8442292SN/A if (dispatchStatus[tid] == Blocked || 8452292SN/A dispatchStatus[tid] == Unblocking) { 8462292SN/A toRename->iewUnblock[tid] = true; 8472292SN/A wroteToTimeBuffer = true; 8482292SN/A } 8492292SN/A 8502292SN/A dispatchStatus[tid] = Squashing; 8512292SN/A 8522292SN/A fetchRedirect[tid] = false; 8532292SN/A return; 8542292SN/A } 8552292SN/A 8562292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8572292SN/A DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); 8582326SN/A 8596221Snate@binkert.org dispatchStatus[tid] = Squashing; 8606221Snate@binkert.org 8612326SN/A return; 8622292SN/A } 8632292SN/A 8642292SN/A if (checkStall(tid)) { 8652292SN/A block(tid); 8662292SN/A dispatchStatus[tid] = Blocked; 8672292SN/A return; 8682292SN/A } 8696221Snate@binkert.org 8702702Sktlim@umich.edu if (dispatchStatus[tid] == Blocked) { 8714632Sgblack@eecs.umich.edu // Status from previous cycle was blocked, but there are no more stall 8722935Sksewell@umich.edu // conditions. Switch over to unblocking. 8732702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8742935Sksewell@umich.edu tid); 8752702Sktlim@umich.edu 8762702Sktlim@umich.edu dispatchStatus[tid] = Unblocking; 8772702Sktlim@umich.edu 8782702Sktlim@umich.edu unblock(tid); 8792702Sktlim@umich.edu 8802702Sktlim@umich.edu return; 8812702Sktlim@umich.edu } 8822702Sktlim@umich.edu 8832702Sktlim@umich.edu if (dispatchStatus[tid] == Squashing) { 8842702Sktlim@umich.edu // Switch status to running if rename isn't being told to block or 8852702Sktlim@umich.edu // squash this cycle. 8862702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8872702Sktlim@umich.edu tid); 8882292SN/A 8892292SN/A dispatchStatus[tid] = Running; 8902292SN/A 8912292SN/A return; 8922292SN/A } 8932292SN/A} 8942292SN/A 8952292SN/Atemplate <class Impl> 8962292SN/Avoid 8972292SN/ADefaultIEW<Impl>::sortInsts() 8982292SN/A{ 8992292SN/A int insts_from_rename = fromRename->size; 9002292SN/A#ifdef DEBUG 9012292SN/A for (int i = 0; i < numThreads; i++) 9022292SN/A assert(insts[i].empty()); 9032292SN/A#endif 9042292SN/A for (int i = 0; i < insts_from_rename; ++i) { 9052292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 9062733Sktlim@umich.edu } 9072292SN/A} 9082292SN/A 9092292SN/Atemplate <class Impl> 9102292SN/Avoid 9112292SN/ADefaultIEW<Impl>::wakeCPU() 9122292SN/A{ 9132292SN/A cpu->wakeCPU(); 9142733Sktlim@umich.edu} 9152292SN/A 9162292SN/Atemplate <class Impl> 9172292SN/Avoid 9182292SN/ADefaultIEW<Impl>::activityThisCycle() 9196221Snate@binkert.org{ 9202292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9212292SN/A cpu->activityThisCycle(); 9222292SN/A} 9232292SN/A 9242292SN/Atemplate <class Impl> 9252292SN/Ainline void 9262292SN/ADefaultIEW<Impl>::activateStage() 9272292SN/A{ 9282292SN/A DPRINTF(Activity, "Activating stage.\n"); 9292292SN/A cpu->activateStage(FullCPU::IEWIdx); 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332292SN/Ainline void 9342292SN/ADefaultIEW<Impl>::deactivateStage() 9352292SN/A{ 9362292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9372292SN/A cpu->deactivateStage(FullCPU::IEWIdx); 9382292SN/A} 9392292SN/A 9402292SN/Atemplate<class Impl> 9412292SN/Avoid 9422292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 9432292SN/A{ 9442292SN/A // If status is Running or idle, 9452292SN/A // call dispatchInsts() 9462292SN/A // If status is Unblocking, 9472292SN/A // buffer any instructions coming from rename 9482292SN/A // continue trying to empty skid buffer 9492292SN/A // check if stall conditions have passed 9502292SN/A 9512292SN/A if (dispatchStatus[tid] == Blocked) { 9522292SN/A ++iewBlockCycles; 9532292SN/A 9542292SN/A } else if (dispatchStatus[tid] == Squashing) { 9555215Sgblack@eecs.umich.edu ++iewSquashCycles; 9562292SN/A } 9572292SN/A 9582292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9592292SN/A // will allow, as long as it is not currently blocked. 9602292SN/A if (dispatchStatus[tid] == Running || 9612292SN/A dispatchStatus[tid] == Idle) { 9622292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9632292SN/A "dispatch.\n", tid); 9642292SN/A 9652292SN/A dispatchInsts(tid); 9662292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9676221Snate@binkert.org // Make sure that the skid buffer has something in it if the 9682292SN/A // status is unblocking. 9692292SN/A assert(!skidsEmpty()); 9702292SN/A 9712292SN/A // If the status was unblocking, then instructions from the skid 9722292SN/A // buffer were used. Remove those instructions and handle 9732292SN/A // the rest of unblocking. 9742292SN/A dispatchInsts(tid); 9752292SN/A 9762292SN/A ++iewUnblockCycles; 9772292SN/A 9782292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9792292SN/A // Add the current inputs to the skid buffer so they can be 9802292SN/A // reprocessed when this stage unblocks. 9812292SN/A skidInsert(tid); 9822292SN/A } 9832292SN/A 9842820Sktlim@umich.edu unblock(tid); 9852292SN/A } 9862292SN/A} 9872292SN/A 9882292SN/Atemplate <class Impl> 9892292SN/Avoid 9902292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9912292SN/A{ 9922292SN/A dispatchedAllInsts = true; 9932292SN/A 9942292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9952292SN/A // otherwise. 9962292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9977720Sgblack@eecs.umich.edu dispatchStatus[tid] == Unblocking ? 9982292SN/A skidBuffer[tid] : insts[tid]; 9997720Sgblack@eecs.umich.edu 10002292SN/A int insts_to_add = insts_to_dispatch.size(); 10012292SN/A 10022292SN/A DynInstPtr inst; 10032292SN/A bool add_to_iq = false; 10042292SN/A int dis_num_inst = 0; 10052292SN/A 10062292SN/A // Loop through the instructions, putting them in the instruction 10072292SN/A // queue. 10082292SN/A for ( ; dis_num_inst < insts_to_add && 10092292SN/A dis_num_inst < issueReadWidth; 10102292SN/A ++dis_num_inst) 10112292SN/A { 10122292SN/A inst = insts_to_dispatch.front(); 10132292SN/A 10142292SN/A if (dispatchStatus[tid] == Unblocking) { 10152292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 10162292SN/A "buffer\n", tid); 10172292SN/A } 10182292SN/A 10192292SN/A // Make sure there's a valid instruction there. 10202292SN/A assert(inst); 10212292SN/A 10222292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 10232292SN/A "IQ.\n", 10242292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 10252292SN/A 10262292SN/A // Be sure to mark these instructions as ready so that the 10272292SN/A // commit stage can go ahead and execute them, and mark 10282292SN/A // them as issued so the IQ doesn't reprocess them. 10292292SN/A 10302292SN/A // Check for squashed instructions. 10312292SN/A if (inst->isSquashed()) { 10322292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10332292SN/A "not adding to IQ.\n", tid); 10342292SN/A 10352292SN/A ++iewDispSquashedInsts; 10362292SN/A 10372292SN/A insts_to_dispatch.pop(); 10382292SN/A 10392292SN/A //Tell Rename That An Instruction has been processed 10402292SN/A if (inst->isLoad() || inst->isStore()) { 10412292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10422292SN/A } 10432292SN/A toRename->iewInfo[tid].dispatched++; 10442292SN/A 10452292SN/A continue; 10462292SN/A } 10472292SN/A 10482292SN/A // Check for full conditions. 10492292SN/A if (instQueue.isFull(tid)) { 10502292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10512292SN/A 10522292SN/A // Call function to start blocking. 10532292SN/A block(tid); 10542292SN/A 10552292SN/A // Set unblock to false. Special case where we are using 10562292SN/A // skidbuffer (unblocking) instructions but then we still 10572292SN/A // get full in the IQ. 10582292SN/A toRename->iewUnblock[tid] = false; 10592292SN/A 10602292SN/A dispatchedAllInsts = false; 10612292SN/A 10622292SN/A ++iewIQFullEvents; 10632292SN/A break; 10642292SN/A } else if (ldstQueue.isFull(tid)) { 10652292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10662292SN/A 10672292SN/A // Call function to start blocking. 10682292SN/A block(tid); 10692292SN/A 10702292SN/A // Set unblock to false. Special case where we are using 10712292SN/A // skidbuffer (unblocking) instructions but then we still 10722292SN/A // get full in the IQ. 10732292SN/A toRename->iewUnblock[tid] = false; 10742336SN/A 10752336SN/A dispatchedAllInsts = false; 10762336SN/A 10772336SN/A ++iewLSQFullEvents; 10782348SN/A break; 10792292SN/A } 10802292SN/A 10812292SN/A // Otherwise issue the instruction just fine. 10822292SN/A if (inst->isLoad()) { 10832292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10842292SN/A "encountered, adding to LSQ.\n", tid); 10852292SN/A 10862292SN/A // Reserve a spot in the load store queue for this 10872292SN/A // memory access. 10882292SN/A ldstQueue.insertLoad(inst); 10892292SN/A 10902326SN/A ++iewDispLoadInsts; 10912292SN/A 10922292SN/A add_to_iq = true; 10932292SN/A 10942292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10952292SN/A } else if (inst->isStore()) { 10962292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10972292SN/A "encountered, adding to LSQ.\n", tid); 10982292SN/A 10992292SN/A ldstQueue.insertStore(inst); 11002292SN/A 11012292SN/A ++iewDispStoreInsts; 11022326SN/A 11032292SN/A if (inst->isNonSpeculative()) { 11042727Sktlim@umich.edu // Non-speculative stores (namely store conditionals) 11052301SN/A // need to be set as "canCommit()" so that commit can 11062292SN/A // process them when they reach the head of commit. 11072292SN/A inst->setCanCommit(); 11082292SN/A instQueue.insertNonSpec(inst); 11092292SN/A add_to_iq = false; 11102292SN/A 11112292SN/A ++iewDispNonSpecInsts; 11122292SN/A } else { 11132292SN/A add_to_iq = true; 11142292SN/A } 11152326SN/A 11162292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 11172292SN/A#if FULL_SYSTEM 11182292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 11192292SN/A // Same as non-speculative stores. 11202292SN/A inst->setCanCommit(); 11214033Sktlim@umich.edu instQueue.insertBarrier(inst); 11224033Sktlim@umich.edu add_to_iq = false; 11234033Sktlim@umich.edu#endif 11244033Sktlim@umich.edu } else if (inst->isNonSpeculative()) { 11254033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11264033Sktlim@umich.edu "encountered, skipping.\n", tid); 11274033Sktlim@umich.edu 11284033Sktlim@umich.edu // Same as non-speculative stores. 11294033Sktlim@umich.edu inst->setCanCommit(); 11304033Sktlim@umich.edu 11314033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11324033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11334033Sktlim@umich.edu 11344033Sktlim@umich.edu ++iewDispNonSpecInsts; 11352292SN/A 11362292SN/A add_to_iq = false; 11372292SN/A } else if (inst->isNop()) { 11382292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11392292SN/A "skipping.\n", tid); 11402292SN/A 11412292SN/A inst->setIssued(); 11422292SN/A inst->setExecuted(); 11432292SN/A inst->setCanCommit(); 11442292SN/A 11452292SN/A instQueue.recordProducer(inst); 11462292SN/A 11478471SGiacomo.Gabrielli@arm.com exeNop[tid]++; 11488471SGiacomo.Gabrielli@arm.com 11498471SGiacomo.Gabrielli@arm.com add_to_iq = false; 11508471SGiacomo.Gabrielli@arm.com } else if (inst->isExecuted()) { 11512292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11522292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11532292SN/A "skipping.\n"); 11542935Sksewell@umich.edu 11552292SN/A inst->setIssued(); 11562292SN/A inst->setCanCommit(); 11572292SN/A 11582292SN/A instQueue.recordProducer(inst); 11592292SN/A 11602292SN/A add_to_iq = false; 11612292SN/A } else { 11622292SN/A add_to_iq = true; 11632292SN/A } 11642292SN/A 11652292SN/A // If the instruction queue is not full, then add the 11662292SN/A // instruction. 11672292SN/A if (add_to_iq) { 11682292SN/A instQueue.insert(inst); 11692292SN/A } 11702292SN/A 11712292SN/A insts_to_dispatch.pop(); 11722292SN/A 11732292SN/A toRename->iewInfo[tid].dispatched++; 11742980Sgblack@eecs.umich.edu 11752292SN/A ++iewDispatchedInsts; 11762292SN/A } 11772292SN/A 11782980Sgblack@eecs.umich.edu if (!insts_to_dispatch.empty()) { 11792292SN/A DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 11807720Sgblack@eecs.umich.edu block(tid); 11812292SN/A toRename->iewUnblock[tid] = false; 11822292SN/A } 11832292SN/A 11842292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11852292SN/A dispatchStatus[tid] = Running; 11862292SN/A 11872292SN/A updatedQueues = true; 11882980Sgblack@eecs.umich.edu } 11892292SN/A 11902292SN/A dis_num_inst = 0; 11912292SN/A} 11922292SN/A 11932292SN/Atemplate <class Impl> 11942292SN/Avoid 11952292SN/ADefaultIEW<Impl>::printAvailableInsts() 11962292SN/A{ 11972292SN/A int inst = 0; 11986221Snate@binkert.org 11996221Snate@binkert.org cout << "Available Instructions: "; 12002292SN/A 12013867Sbinkertn@umich.edu while (fromIssue->insts[inst]) { 12026221Snate@binkert.org 12032292SN/A if (inst%3==0) cout << "\n\t"; 12042292SN/A 12052292SN/A cout << "PC: " << fromIssue->insts[inst]->readPC() 12062698Sktlim@umich.edu << " TN: " << fromIssue->insts[inst]->threadNumber 12077599Sminkyu.jeong@arm.com << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 12082698Sktlim@umich.edu 12091062SN/A inst++; 12101062SN/A 12112333SN/A } 12122292SN/A 12132333SN/A cout << "\n"; 12142326SN/A} 12151062SN/A 12162292SN/Atemplate <class Impl> 12171062SN/Avoid 12182333SN/ADefaultIEW<Impl>::executeInsts() 12191062SN/A{ 12207720Sgblack@eecs.umich.edu wbNumInst = 0; 12217720Sgblack@eecs.umich.edu wbCycle = 0; 12221062SN/A 12231062SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 12241062SN/A 12258315Sgeoffrey.blake@arm.com while (threads != (*activeThreads).end()) { 12268315Sgeoffrey.blake@arm.com unsigned tid = *threads++; 12278315Sgeoffrey.blake@arm.com fetchRedirect[tid] = false; 12281062SN/A } 12291062SN/A 12301062SN/A#if 0 12311062SN/A printAvailableInsts(); 12321062SN/A#endif 12332292SN/A 12342292SN/A // Execute/writeback any instructions that are available. 12352292SN/A int insts_to_execute = fromIssue->size; 12361062SN/A int inst_num = 0; 12371062SN/A for (; inst_num < insts_to_execute; 12381062SN/A ++inst_num) { 12392820Sktlim@umich.edu 12401062SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12411062SN/A 12421062SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12432292SN/A 12441062SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 12451062SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12461062SN/A 12471062SN/A // Check if the instruction is squashed; if so then skip it 12487850SMatt.Horsnell@arm.com if (inst->isSquashed()) { 12492292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12501062SN/A 12511062SN/A // Consider this instruction executed so that commit can go 12521062SN/A // ahead and retire the instruction. 12531062SN/A inst->setExecuted(); 12542292SN/A 12552292SN/A // Not sure if I should set this here or just let commit try to 12562292SN/A // commit any squashed instructions. I like the latter a bit more. 12577944SGiacomo.Gabrielli@arm.com inst->setCanCommit(); 12587944SGiacomo.Gabrielli@arm.com 12597944SGiacomo.Gabrielli@arm.com ++iewExecSquashedInsts; 12607944SGiacomo.Gabrielli@arm.com 12617944SGiacomo.Gabrielli@arm.com continue; 12627944SGiacomo.Gabrielli@arm.com } 12637944SGiacomo.Gabrielli@arm.com 12647944SGiacomo.Gabrielli@arm.com Fault fault = NoFault; 12657944SGiacomo.Gabrielli@arm.com 12667944SGiacomo.Gabrielli@arm.com // Execute instruction. 12677944SGiacomo.Gabrielli@arm.com // Note that if the instruction faults, it will be handled 12687850SMatt.Horsnell@arm.com // at the commit stage. 12698073SAli.Saidi@ARM.com if (inst->isMemRef() && 12707850SMatt.Horsnell@arm.com (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12711062SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12722367SN/A "reference.\n"); 12731062SN/A 12747944SGiacomo.Gabrielli@arm.com // Tell the LDSTQ to execute this instruction (if it is a load). 12757944SGiacomo.Gabrielli@arm.com if (inst->isLoad()) { 12767944SGiacomo.Gabrielli@arm.com // Loads will mark themselves as executed, and their writeback 12777944SGiacomo.Gabrielli@arm.com // event adds the instruction to the queue to commit 12787944SGiacomo.Gabrielli@arm.com fault = ldstQueue.executeLoad(inst); 12797944SGiacomo.Gabrielli@arm.com } else if (inst->isStore()) { 12807944SGiacomo.Gabrielli@arm.com ldstQueue.executeStore(inst); 12817944SGiacomo.Gabrielli@arm.com 12827944SGiacomo.Gabrielli@arm.com // If the store had a fault then it may not have a mem req 12837944SGiacomo.Gabrielli@arm.com if (inst->req && !(inst->req->flags & LOCKED)) { 12842292SN/A inst->setExecuted(); 12857782Sminkyu.jeong@arm.com 12867782Sminkyu.jeong@arm.com instToCommit(inst); 12877782Sminkyu.jeong@arm.com } 12887782Sminkyu.jeong@arm.com 12892367SN/A // Store conditionals will mark themselves as 12902367SN/A // executed, and their writeback event will add the 12912367SN/A // instruction to the queue to commit. 12922367SN/A } else { 12932367SN/A panic("Unexpected memory type!\n"); 12942292SN/A } 12952326SN/A 12962326SN/A } else { 12972326SN/A inst->execute(); 12982326SN/A 12991062SN/A inst->setExecuted(); 13002292SN/A 13011062SN/A instToCommit(inst); 13021062SN/A } 13031062SN/A 13047847Sminkyu.jeong@arm.com updateExeInstStats(inst); 13057847Sminkyu.jeong@arm.com 13067847Sminkyu.jeong@arm.com // Check if branch prediction was correct, if not then we need 13077847Sminkyu.jeong@arm.com // to tell commit to squash in flight instructions. Only 13087847Sminkyu.jeong@arm.com // handle this if there hasn't already been something that 13097847Sminkyu.jeong@arm.com // redirects fetch in this group of instructions. 13107848SAli.Saidi@ARM.com 13117848SAli.Saidi@ARM.com // This probably needs to prioritize the redirects if a different 13127847Sminkyu.jeong@arm.com // scheduler is used. Currently the scheduler schedules the oldest 13131062SN/A // instruction first, so the branch resolution order will be correct. 13142292SN/A unsigned tid = inst->threadNumber; 13152292SN/A 13162292SN/A if (!fetchRedirect[tid]) { 13171062SN/A 13181062SN/A if (inst->mispredicted()) { 13192301SN/A fetchRedirect[tid] = true; 13201681SN/A 13212326SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13222326SN/A DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 13232326SN/A inst->nextPC); 13242107SN/A 13251681SN/A // If incorrect, then signal the ROB that it must be squashed. 13262292SN/A squashDueToBranch(inst, tid); 13272292SN/A 13282292SN/A if (inst->predTaken()) { 13296221Snate@binkert.org predictedTakenIncorrect++; 13301062SN/A } else { 13313732Sktlim@umich.edu predictedNotTakenIncorrect++; 13327852SMatt.Horsnell@arm.com } 13333732Sktlim@umich.edu } else if (ldstQueue.violation(tid)) { 13341062SN/A fetchRedirect[tid] = true; 13357856SMatt.Horsnell@arm.com 13367856SMatt.Horsnell@arm.com // If there was an ordering violation, then get the 13377856SMatt.Horsnell@arm.com // DynInst that caused the violation. Note that this 13387856SMatt.Horsnell@arm.com // clears the violation signal. 13397856SMatt.Horsnell@arm.com DynInstPtr violator; 13402292SN/A violator = ldstQueue.getMemDepViolator(tid); 13411062SN/A 13422292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13438674Snilay@cs.wisc.edu "%#x, inst PC: %#x. Addr is: %#x.\n", 13448674Snilay@cs.wisc.edu violator->readPC(), inst->readPC(), inst->physEffAddr); 13457720Sgblack@eecs.umich.edu 13468674Snilay@cs.wisc.edu // Tell the instruction queue that a violation has occured. 13471062SN/A instQueue.violation(inst, violator); 13482292SN/A 13491062SN/A // Squash. 13503795Sgblack@eecs.umich.edu squashDueToMemOrder(inst,tid); 13511062SN/A 13522292SN/A ++memOrderViolationEvents; 13532292SN/A } else if (ldstQueue.loadBlocked(tid) && 13541062SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13552292SN/A fetchRedirect[tid] = true; 13564033Sktlim@umich.edu 13572326SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13582326SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13592292SN/A inst->readPC(), inst->seqNum); 13602292SN/A 13612292SN/A squashDueToMemBlocked(inst, tid); 13621062SN/A } 13637720Sgblack@eecs.umich.edu } 13647720Sgblack@eecs.umich.edu } 13657720Sgblack@eecs.umich.edu 13667720Sgblack@eecs.umich.edu if (inst_num) { 13677720Sgblack@eecs.umich.edu if (exeStatus == Idle) { 13683732Sktlim@umich.edu exeStatus = Running; 13693732Sktlim@umich.edu } 13701062SN/A 13711062SN/A updatedQueues = true; 13721062SN/A 13731062SN/A cpu->activityThisCycle(); 13748513SGiacomo.Gabrielli@arm.com } 13751062SN/A 13761062SN/A // Need to reset this in case a writeback event needs to write into the 13772292SN/A // iew queue. That way the writeback event will write into the correct 13782292SN/A // spot in the queue. 13792292SN/A wbNumInst = 0; 13802292SN/A} 13812292SN/A 13827720Sgblack@eecs.umich.edutemplate <class Impl> 13837720Sgblack@eecs.umich.eduvoid 13842292SN/ADefaultIEW<Impl>::writebackInsts() 13852292SN/A{ 13861062SN/A // Loop through the head of the time buffer and wake any 13874033Sktlim@umich.edu // dependents. These instructions are about to write back. Also 13884033Sktlim@umich.edu // mark scoreboard that this instruction is finally complete. 13894033Sktlim@umich.edu // Either have IEW have direct access to scoreboard, or have this 13904033Sktlim@umich.edu // as part of backwards communication. 13914033Sktlim@umich.edu for (int inst_num = 0; inst_num < issueWidth && 13924033Sktlim@umich.edu toCommit->insts[inst_num]; inst_num++) { 13934033Sktlim@umich.edu DynInstPtr inst = toCommit->insts[inst_num]; 13944033Sktlim@umich.edu int tid = inst->threadNumber; 13954033Sktlim@umich.edu 13967720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n", 13977720Sgblack@eecs.umich.edu inst->readPC()); 13987720Sgblack@eecs.umich.edu 13994033Sktlim@umich.edu iewInstsToCommit[tid]++; 14004033Sktlim@umich.edu 14014033Sktlim@umich.edu // Some instructions will be sent to commit without having 14024033Sktlim@umich.edu // executed because they need commit to handle them. 14034033Sktlim@umich.edu // E.g. Uncached loads have not actually executed when they 14044033Sktlim@umich.edu // are first sent to commit. Instead commit must tell the LSQ 14054033Sktlim@umich.edu // when it's ready to execute the uncached load. 14064033Sktlim@umich.edu if (!inst->isSquashed() && inst->isExecuted()) { 14077720Sgblack@eecs.umich.edu int dependents = instQueue.wakeDependents(inst); 14087720Sgblack@eecs.umich.edu 14094033Sktlim@umich.edu for (int i = 0; i < inst->numDestRegs(); i++) { 14104033Sktlim@umich.edu //mark as Ready 14114033Sktlim@umich.edu DPRINTF(IEW,"Setting Destination Register %i\n", 14124033Sktlim@umich.edu inst->renamedDestRegIdx(i)); 14134033Sktlim@umich.edu scoreboard->setReg(inst->renamedDestRegIdx(i)); 14144033Sktlim@umich.edu } 14151062SN/A 14161062SN/A producerInst[tid]++; 14172292SN/A consumerInst[tid]+= dependents; 14182348SN/A writebackCount[tid]++; 14192292SN/A } 14202292SN/A } 14212292SN/A} 14222292SN/A 14232292SN/Atemplate<class Impl> 14242292SN/Avoid 14252292SN/ADefaultIEW<Impl>::tick() 14262292SN/A{ 14272292SN/A wbNumInst = 0; 14282292SN/A wbCycle = 0; 14292292SN/A 14302292SN/A wroteToTimeBuffer = false; 14312292SN/A updatedQueues = false; 14322292SN/A 14337852SMatt.Horsnell@arm.com sortInsts(); 14342107SN/A 14352107SN/A // Free function units marked as being freed this cycle. 14362292SN/A fuPool->processFreeUnits(); 14372107SN/A 14382292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 14392107SN/A 14402326SN/A // Check stall and squash signals, dispatch any instructions. 14412326SN/A while (threads != (*activeThreads).end()) { 14422326SN/A unsigned tid = *threads++; 14432326SN/A 14442326SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14453958Sgblack@eecs.umich.edu 14462292SN/A checkSignalsAndUpdate(tid); 14472107SN/A dispatch(tid); 14486221Snate@binkert.org } 14492107SN/A 14507720Sgblack@eecs.umich.edu if (exeStatus != Squashing) { 14517720Sgblack@eecs.umich.edu executeInsts(); 14522107SN/A 14532301SN/A writebackInsts(); 14542301SN/A 14552292SN/A // Have the instruction queue try to schedule any ready instructions. 14562292SN/A // (In actuality, this scheduling is for instructions that will 14572292SN/A // be executed next cycle.) 14582292SN/A instQueue.scheduleReadyInsts(); 14592292SN/A 14602367SN/A // Also should advance its own time buffers if the stage ran. 14612301SN/A // Not the best place for it, but this works (hopefully). 14622107SN/A issueToExecQueue.advance(); 14632292SN/A } 14642292SN/A 14652292SN/A bool broadcast_free_entries = false; 14662292SN/A 14672292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14682107SN/A exeStatus = Idle; 14692301SN/A updateLSQNextCycle = false; 14702348SN/A 14712348SN/A broadcast_free_entries = true; 14722348SN/A } 14732348SN/A 14742326SN/A // Writeback any stores using any leftover bandwidth. 14752107SN/A ldstQueue.writebackStores(); 14762820Sktlim@umich.edu 14772820Sktlim@umich.edu // Check the committed load/store signals to see if there's a load 14782107SN/A // or store to commit. Also check if it's being told to execute a 14791060SN/A // nonspeculative instruction. 14801060SN/A // This is pretty inefficient... 14811681SN/A 14821060SN/A threads = (*activeThreads).begin(); 14832292SN/A while (threads != (*activeThreads).end()) { 14841060SN/A unsigned tid = (*threads++); 14852292SN/A 14862292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14871060SN/A 14882292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 14892292SN/A !fromCommit->commitInfo[tid].squash && 14901060SN/A !fromCommit->commitInfo[tid].robSquashing) { 14912292SN/A 14921060SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 14932326SN/A 14942326SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 14951062SN/A 14966221Snate@binkert.org updateLSQNextCycle = true; 14976221Snate@binkert.org instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 14981060SN/A } 14992326SN/A 15003867Sbinkertn@umich.edu if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15016221Snate@binkert.org 15021060SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15032292SN/A if (fromCommit->commitInfo[tid].uncached) { 15041060SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15052292SN/A } else { 15062292SN/A instQueue.scheduleNonSpec( 15071060SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15081060SN/A } 15092292SN/A } 15102292SN/A 15111060SN/A if (broadcast_free_entries) { 15122292SN/A toFetch->iewInfo[tid].iqCount = 15132292SN/A instQueue.getCount(tid); 15142292SN/A toFetch->iewInfo[tid].ldstqCount = 15152292SN/A ldstQueue.getCount(tid); 15162292SN/A 15172292SN/A toRename->iewInfo[tid].usedIQ = true; 15182292SN/A toRename->iewInfo[tid].freeIQEntries = 15192292SN/A instQueue.numFreeEntries(); 15202292SN/A toRename->iewInfo[tid].usedLSQ = true; 15212292SN/A toRename->iewInfo[tid].freeLSQEntries = 15222292SN/A ldstQueue.numFreeEntries(tid); 15232292SN/A 15242292SN/A wroteToTimeBuffer = true; 15252292SN/A } 15262292SN/A 15272292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15282292SN/A tid, toRename->iewInfo[tid].dispatched); 15292292SN/A } 15302292SN/A 15312292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15322292SN/A "LSQ has %i free entries.\n", 15332292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15341681SN/A ldstQueue.numFreeEntries()); 15351681SN/A 15361061SN/A updateStatus(); 15371061SN/A 15381061SN/A if (wroteToTimeBuffer) { 15391681SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15402292SN/A cpu->activityThisCycle(); 15413867Sbinkertn@umich.edu } 15423867Sbinkertn@umich.edu} 15436221Snate@binkert.org 15442292SN/Atemplate <class Impl> 15452292SN/Avoid 15462292SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15472348SN/A{ 15482292SN/A int thread_number = inst->threadNumber; 15492292SN/A 15502292SN/A // 15512292SN/A // Pick off the software prefetches 15522292SN/A // 15532292SN/A#ifdef TARGET_ALPHA 15542292SN/A if (inst->isDataPrefetch()) 15552292SN/A exeSwp[thread_number]++; 15562292SN/A else 15572292SN/A iewExecutedInsts++; 15582292SN/A#else 15592292SN/A iewExecutedInsts[thread_number]++; 15602292SN/A#endif 15612292SN/A 15622292SN/A // 15632292SN/A // Control operations 15642292SN/A // 15654033Sktlim@umich.edu if (inst->isControl()) 15662292SN/A exeBranches[thread_number]++; 15672292SN/A 15682292SN/A // 15692292SN/A // Memory operations 15702292SN/A // 15712292SN/A if (inst->isMemRef()) { 15722292SN/A exeRefs[thread_number]++; 15732292SN/A 15742292SN/A if (inst->isLoad()) { 15752292SN/A iewExecLoadInsts[thread_number]++; 15762292SN/A } 15772292SN/A } 15782292SN/A} 15792292SN/A