fetch.hh revision 1060
113014Sciro.santilli@arm.com// Todo: add in statistics, only get the MachInst and let decode actually 213014Sciro.santilli@arm.com// decode, think about SMT fetch, 313014Sciro.santilli@arm.com// fix up branch prediction stuff into one thing, 413014Sciro.santilli@arm.com// Figure out where to advance time buffer. Add a way to get a 513014Sciro.santilli@arm.com// stage's current status. 613014Sciro.santilli@arm.com 713014Sciro.santilli@arm.com#ifndef __SIMPLE_FETCH_HH__ 813014Sciro.santilli@arm.com#define __SIMPLE_FETCH_HH__ 913014Sciro.santilli@arm.com 1013014Sciro.santilli@arm.com//Will want to include: time buffer, structs, MemInterface, Event, 1113014Sciro.santilli@arm.com//whatever class bzero uses, MemReqPtr 1213014Sciro.santilli@arm.com 1313014Sciro.santilli@arm.com#include "base/timebuf.hh" 1413014Sciro.santilli@arm.com#include "sim/eventq.hh" 1513014Sciro.santilli@arm.com#include "cpu/pc_event.hh" 1613014Sciro.santilli@arm.com#include "cpu/beta_cpu/comm.hh" 1713014Sciro.santilli@arm.com#include "mem/mem_interface.hh" 1813014Sciro.santilli@arm.com 1913014Sciro.santilli@arm.comusing namespace std; 2013014Sciro.santilli@arm.com 2113014Sciro.santilli@arm.com/** 2213014Sciro.santilli@arm.com * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch 2313014Sciro.santilli@arm.com * will stall if there's an Icache miss, but otherwise assumes a one cycle 2413014Sciro.santilli@arm.com * Icache hit. This will be replaced with a more fleshed out class in the 2513014Sciro.santilli@arm.com * future. 2613014Sciro.santilli@arm.com */ 2713014Sciro.santilli@arm.com 2813014Sciro.santilli@arm.comtemplate <class Impl> 2913014Sciro.santilli@arm.comclass SimpleFetch 3013014Sciro.santilli@arm.com{ 3113014Sciro.santilli@arm.com public: 3213014Sciro.santilli@arm.com /** Typedefs from Impl. */ 3313014Sciro.santilli@arm.com typedef typename Impl::ISA ISA; 3413014Sciro.santilli@arm.com typedef typename Impl::DynInst DynInst; 3513014Sciro.santilli@arm.com typedef typename Impl::FullCPU FullCPU; 3613014Sciro.santilli@arm.com typedef typename Impl::Params Params; 3713014Sciro.santilli@arm.com 3813014Sciro.santilli@arm.com typedef typename Impl::FetchStruct FetchStruct; 3913014Sciro.santilli@arm.com typedef typename Impl::TimeStruct TimeStruct; 4013014Sciro.santilli@arm.com 4113014Sciro.santilli@arm.com /** Typedefs from ISA. */ 4213014Sciro.santilli@arm.com typedef typename ISA::MachInst MachInst; 4313014Sciro.santilli@arm.com 4413014Sciro.santilli@arm.com public: 4513014Sciro.santilli@arm.com enum Status { 4613014Sciro.santilli@arm.com Running, 4713014Sciro.santilli@arm.com Idle, 4813014Sciro.santilli@arm.com Squashing, 4913014Sciro.santilli@arm.com Blocked, 5013014Sciro.santilli@arm.com IcacheMissStall, 5113014Sciro.santilli@arm.com IcacheMissComplete 5213014Sciro.santilli@arm.com }; 5313014Sciro.santilli@arm.com 5413014Sciro.santilli@arm.com // May eventually need statuses on a per thread basis. 5513014Sciro.santilli@arm.com Status _status; 5613014Sciro.santilli@arm.com 5713014Sciro.santilli@arm.com bool stalled; 5813014Sciro.santilli@arm.com 5913014Sciro.santilli@arm.com public: 6013014Sciro.santilli@arm.com /** SimpleFetch constructor. */ 6113014Sciro.santilli@arm.com SimpleFetch(Params ¶ms); 6213014Sciro.santilli@arm.com 6313014Sciro.santilli@arm.com void setCPU(FullCPU *cpu_ptr); 6413014Sciro.santilli@arm.com 6513014Sciro.santilli@arm.com void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 6613014Sciro.santilli@arm.com 6713014Sciro.santilli@arm.com void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 6813014Sciro.santilli@arm.com 6913014Sciro.santilli@arm.com void tick(); 7013014Sciro.santilli@arm.com 7113014Sciro.santilli@arm.com void fetch(); 7213014Sciro.santilli@arm.com 7313014Sciro.santilli@arm.com void processCacheCompletion(); 7413014Sciro.santilli@arm.com 7513014Sciro.santilli@arm.com// private: 7613014Sciro.santilli@arm.com // Figure out PC vs next PC and how it should be updated 7713014Sciro.santilli@arm.com void squash(Addr newPC); 7813014Sciro.santilli@arm.com 7913014Sciro.santilli@arm.com public: 8013014Sciro.santilli@arm.com class CacheCompletionEvent : public Event 8113014Sciro.santilli@arm.com { 8213014Sciro.santilli@arm.com private: 8313014Sciro.santilli@arm.com SimpleFetch *fetch; 8413014Sciro.santilli@arm.com 8513014Sciro.santilli@arm.com public: 8613014Sciro.santilli@arm.com CacheCompletionEvent(SimpleFetch *_fetch); 8713014Sciro.santilli@arm.com 8813014Sciro.santilli@arm.com virtual void process(); 8913014Sciro.santilli@arm.com virtual const char *description(); 9013014Sciro.santilli@arm.com }; 9113014Sciro.santilli@arm.com 9213014Sciro.santilli@arm.com CacheCompletionEvent cacheCompletionEvent; 9313014Sciro.santilli@arm.com 9413014Sciro.santilli@arm.com private: 9513014Sciro.santilli@arm.com /** Pointer to the FullCPU. */ 9613014Sciro.santilli@arm.com FullCPU *cpu; 9713014Sciro.santilli@arm.com 9813014Sciro.santilli@arm.com /** Time buffer interface. */ 9913014Sciro.santilli@arm.com TimeBuffer<TimeStruct> *timeBuffer; 10013014Sciro.santilli@arm.com 10113014Sciro.santilli@arm.com /** Wire to get decode's information from backwards time buffer. */ 10213014Sciro.santilli@arm.com typename TimeBuffer<TimeStruct>::wire fromDecode; 10313014Sciro.santilli@arm.com 10413014Sciro.santilli@arm.com /** Wire to get rename's information from backwards time buffer. */ 10513014Sciro.santilli@arm.com typename TimeBuffer<TimeStruct>::wire fromRename; 10613014Sciro.santilli@arm.com 10713014Sciro.santilli@arm.com /** Wire to get iew's information from backwards time buffer. */ 10813014Sciro.santilli@arm.com typename TimeBuffer<TimeStruct>::wire fromIEW; 10913014Sciro.santilli@arm.com 11013014Sciro.santilli@arm.com /** Wire to get commit's information from backwards time buffer. */ 11113014Sciro.santilli@arm.com typename TimeBuffer<TimeStruct>::wire fromCommit; 11213014Sciro.santilli@arm.com 11313014Sciro.santilli@arm.com // Will probably have this sit in the FullCPU and just pass a pointr in. 11413014Sciro.santilli@arm.com // Simplifies the constructors of all stages. 11513014Sciro.santilli@arm.com /** Internal fetch instruction queue. */ 11613014Sciro.santilli@arm.com TimeBuffer<FetchStruct> *fetchQueue; 11713014Sciro.santilli@arm.com 11813014Sciro.santilli@arm.com //Might be annoying how this name is different than the queue. 11913014Sciro.santilli@arm.com /** Wire used to write any information heading to decode. */ 12013014Sciro.santilli@arm.com typename TimeBuffer<FetchStruct>::wire toDecode; 12113014Sciro.santilli@arm.com 12213014Sciro.santilli@arm.com /** Icache interface. */ 12313014Sciro.santilli@arm.com MemInterface *icacheInterface; 12413014Sciro.santilli@arm.com 12513014Sciro.santilli@arm.com /** Memory request used to access cache. */ 12613014Sciro.santilli@arm.com MemReqPtr memReq; 12713014Sciro.santilli@arm.com 12813014Sciro.santilli@arm.com /** Decode to fetch delay, in ticks. */ 12913014Sciro.santilli@arm.com unsigned decodeToFetchDelay; 13013014Sciro.santilli@arm.com 13113014Sciro.santilli@arm.com /** Rename to fetch delay, in ticks. */ 13213014Sciro.santilli@arm.com unsigned renameToFetchDelay; 13313014Sciro.santilli@arm.com 13413014Sciro.santilli@arm.com /** IEW to fetch delay, in ticks. */ 13513014Sciro.santilli@arm.com unsigned iewToFetchDelay; 13613014Sciro.santilli@arm.com 13713014Sciro.santilli@arm.com /** Commit to fetch delay, in ticks. */ 13813014Sciro.santilli@arm.com unsigned commitToFetchDelay; 13913014Sciro.santilli@arm.com 14013014Sciro.santilli@arm.com /** The width of fetch in instructions. */ 14113014Sciro.santilli@arm.com unsigned fetchWidth; 14213014Sciro.santilli@arm.com 14313014Sciro.santilli@arm.com /** Cache block size. */ 14413014Sciro.santilli@arm.com int blkSize; 14513014Sciro.santilli@arm.com 14613014Sciro.santilli@arm.com /** Mask to get a cache block's address. */ 14713014Sciro.santilli@arm.com Addr cacheBlockMask; 14813014Sciro.santilli@arm.com 14913014Sciro.santilli@arm.com /** The instruction being fetched. */ 15013014Sciro.santilli@arm.com MachInst inst; 15113014Sciro.santilli@arm.com 15213014Sciro.santilli@arm.com /** Size of instructions. */ 15313014Sciro.santilli@arm.com int instSize; 15413014Sciro.santilli@arm.com 15513014Sciro.santilli@arm.com /** Icache stall statistics. */ 15613014Sciro.santilli@arm.com// Stats::Scalar<> icacheStallCycles; 15713014Sciro.santilli@arm.com// Counter lastIcacheStall; 15813014Sciro.santilli@arm.com}; 15913014Sciro.santilli@arm.com 16013014Sciro.santilli@arm.com#endif //__SIMPLE_FETCH_HH__ 16113014Sciro.santilli@arm.com