fetch.hh revision 1060 
1// Todo: add in statistics, only get the MachInst and let decode actually
2// decode, think about SMT fetch,
3// fix up branch prediction stuff into one thing,
4// Figure out where to advance time buffer.  Add a way to get a
5// stage's current status.
6
7#ifndef __SIMPLE_FETCH_HH__
8#define __SIMPLE_FETCH_HH__
9
10//Will want to include: time buffer, structs, MemInterface, Event,
11//whatever class bzero uses, MemReqPtr
12
13#include "base/timebuf.hh"
14#include "sim/eventq.hh"
15#include "cpu/pc_event.hh"
16#include "cpu/beta_cpu/comm.hh"
17#include "mem/mem_interface.hh"
18
19using namespace std;
20
21/**
22 * SimpleFetch class to fetch a single instruction each cycle.  SimpleFetch
23 * will stall if there's an Icache miss, but otherwise assumes a one cycle
24 * Icache hit.  This will be replaced with a more fleshed out class in the
25 * future.
26 */
27
28template <class Impl>
29class SimpleFetch
30{
31  public:
32    /** Typedefs from Impl. */
33    typedef typename Impl::ISA ISA;
34    typedef typename Impl::DynInst DynInst;
35    typedef typename Impl::FullCPU FullCPU;
36    typedef typename Impl::Params Params;
37
38    typedef typename Impl::FetchStruct FetchStruct;
39    typedef typename Impl::TimeStruct TimeStruct;
40
41    /** Typedefs from ISA. */
42    typedef typename ISA::MachInst MachInst;
43
44  public:
45    enum Status {
46        Running,
47        Idle,
48        Squashing,
49        Blocked,
50        IcacheMissStall,
51        IcacheMissComplete
52    };
53
54    // May eventually need statuses on a per thread basis.
55    Status _status;
56
57    bool stalled;
58
59  public:
60    /** SimpleFetch constructor. */
61    SimpleFetch(Params &params);
62
63    void setCPU(FullCPU *cpu_ptr);
64
65    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
66
67    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
68
69    void tick();
70
71    void fetch();
72
73    void processCacheCompletion();
74
75//  private:
76    // Figure out PC vs next PC and how it should be updated
77    void squash(Addr newPC);
78
79  public:
80    class CacheCompletionEvent : public Event
81    {
82      private:
83        SimpleFetch *fetch;
84
85      public:
86        CacheCompletionEvent(SimpleFetch *_fetch);
87
88        virtual void process();
89        virtual const char *description();
90    };
91
92    CacheCompletionEvent cacheCompletionEvent;
93
94  private:
95    /** Pointer to the FullCPU. */
96    FullCPU *cpu;
97
98    /** Time buffer interface. */
99    TimeBuffer<TimeStruct> *timeBuffer;
100
101    /** Wire to get decode's information from backwards time buffer. */
102    typename TimeBuffer<TimeStruct>::wire fromDecode;
103
104    /** Wire to get rename's information from backwards time buffer. */
105    typename TimeBuffer<TimeStruct>::wire fromRename;
106
107    /** Wire to get iew's information from backwards time buffer. */
108    typename TimeBuffer<TimeStruct>::wire fromIEW;
109
110    /** Wire to get commit's information from backwards time buffer. */
111    typename TimeBuffer<TimeStruct>::wire fromCommit;
112
113    // Will probably have this sit in the FullCPU and just pass a pointr in.
114    // Simplifies the constructors of all stages.
115    /** Internal fetch instruction queue. */
116    TimeBuffer<FetchStruct> *fetchQueue;
117
118    //Might be annoying how this name is different than the queue.
119    /** Wire used to write any information heading to decode. */
120    typename TimeBuffer<FetchStruct>::wire toDecode;
121
122    /** Icache interface. */
123    MemInterface *icacheInterface;
124
125    /** Memory request used to access cache. */
126    MemReqPtr memReq;
127
128    /** Decode to fetch delay, in ticks. */
129    unsigned decodeToFetchDelay;
130
131    /** Rename to fetch delay, in ticks. */
132    unsigned renameToFetchDelay;
133
134    /** IEW to fetch delay, in ticks. */
135    unsigned iewToFetchDelay;
136
137    /** Commit to fetch delay, in ticks. */
138    unsigned commitToFetchDelay;
139
140    /** The width of fetch in instructions. */
141    unsigned fetchWidth;
142
143    /** Cache block size. */
144    int blkSize;
145
146    /** Mask to get a cache block's address. */
147    Addr cacheBlockMask;
148
149    /** The instruction being fetched. */
150    MachInst inst;
151
152    /** Size of instructions. */
153    int instSize;
154
155    /** Icache stall statistics. */
156//     Stats::Scalar<> icacheStallCycles;
157//     Counter lastIcacheStall;
158};
159
160#endif //__SIMPLE_FETCH_HH__
161