misc.hh revision 11324
14684SN/A/* 25419SN/A * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34684SN/A * All rights reserved. 44684SN/A * 57087SN/A * The license below extends only to copyright in the software and shall 67087SN/A * not be construed as granting a license to any other intellectual 77087SN/A * property including but not limited to intellectual property relating 87087SN/A * to a hardware implementation of the functionality of the software 97087SN/A * licensed hereunder. You may use the software subject to the license 107087SN/A * terms below provided that you ensure that this notice is replicated 117087SN/A * unmodified and in its entirety in all distributions of the software, 127087SN/A * modified or unmodified, in source code or in binary form. 134684SN/A * 147087SN/A * Redistribution and use in source and binary forms, with or without 157087SN/A * modification, are permitted provided that the following conditions are 167087SN/A * met: redistributions of source code must retain the above copyright 177087SN/A * notice, this list of conditions and the following disclaimer; 187087SN/A * redistributions in binary form must reproduce the above copyright 197087SN/A * notice, this list of conditions and the following disclaimer in the 207087SN/A * documentation and/or other materials provided with the distribution; 217087SN/A * neither the name of the copyright holders nor the names of its 224684SN/A * contributors may be used to endorse or promote products derived from 237087SN/A * this software without specific prior written permission. 244684SN/A * 254684SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264684SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274684SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284684SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294684SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304684SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314684SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324684SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334684SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344684SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354684SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364684SN/A * 374684SN/A * Authors: Gabe Black 384684SN/A */ 394684SN/A 404684SN/A#ifndef __ARCH_X86_MISCREGS_HH__ 414684SN/A#define __ARCH_X86_MISCREGS_HH__ 424684SN/A 437629Sgblack@eecs.umich.edu#include "arch/x86/regs/segment.hh" 445025SN/A#include "arch/x86/x86_traits.hh" 454684SN/A#include "base/bitunion.hh" 464684SN/A 475086SN/A//These get defined in some system headers (at least termbits.h). That confuses 485086SN/A//things here significantly. 495086SN/A#undef CR0 505086SN/A#undef CR2 515086SN/A#undef CR3 525086SN/A 534684SN/Anamespace X86ISA 544684SN/A{ 554684SN/A enum CondFlagBit { 564684SN/A CFBit = 1 << 0, 574684SN/A PFBit = 1 << 2, 584684SN/A ECFBit = 1 << 3, 594684SN/A AFBit = 1 << 4, 604684SN/A EZFBit = 1 << 5, 614684SN/A ZFBit = 1 << 6, 624684SN/A SFBit = 1 << 7, 634868SN/A DFBit = 1 << 10, 644684SN/A OFBit = 1 << 11 654684SN/A }; 664684SN/A 679010Snilay@cs.wisc.edu const uint32_t cfofMask = CFBit | OFBit; 689211Snilay@cs.wisc.edu const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit; 699010Snilay@cs.wisc.edu 705426SN/A enum RFLAGBit { 715426SN/A TFBit = 1 << 8, 725426SN/A IFBit = 1 << 9, 735426SN/A NTBit = 1 << 14, 745426SN/A RFBit = 1 << 16, 755426SN/A VMBit = 1 << 17, 765426SN/A ACBit = 1 << 18, 775426SN/A VIFBit = 1 << 19, 785426SN/A VIPBit = 1 << 20, 795426SN/A IDBit = 1 << 21 805426SN/A }; 815426SN/A 829470Snilay@cs.wisc.edu enum X87StatusBit { 839470Snilay@cs.wisc.edu // Exception Flags 849470Snilay@cs.wisc.edu IEBit = 1 << 0, 859470Snilay@cs.wisc.edu DEBit = 1 << 1, 869470Snilay@cs.wisc.edu ZEBit = 1 << 2, 879470Snilay@cs.wisc.edu OEBit = 1 << 3, 889470Snilay@cs.wisc.edu UEBit = 1 << 4, 899470Snilay@cs.wisc.edu PEBit = 1 << 5, 909470Snilay@cs.wisc.edu 919470Snilay@cs.wisc.edu // !Exception Flags 929470Snilay@cs.wisc.edu StackFaultBit = 1 << 6, 939470Snilay@cs.wisc.edu ErrSummaryBit = 1 << 7, 949470Snilay@cs.wisc.edu CC0Bit = 1 << 8, 959470Snilay@cs.wisc.edu CC1Bit = 1 << 9, 969470Snilay@cs.wisc.edu CC2Bit = 1 << 10, 979470Snilay@cs.wisc.edu CC3Bit = 1 << 14, 989470Snilay@cs.wisc.edu BusyBit = 1 << 15, 999470Snilay@cs.wisc.edu }; 1009470Snilay@cs.wisc.edu 1014700SN/A enum MiscRegIndex 1024700SN/A { 1034700SN/A // Control registers 10411324Ssteve.reinhardt@amd.com // Most of these are invalid. See isValidMiscReg() below. 1054862SN/A MISCREG_CR_BASE, 1064862SN/A MISCREG_CR0 = MISCREG_CR_BASE, 1074700SN/A MISCREG_CR1, 1084700SN/A MISCREG_CR2, 1094700SN/A MISCREG_CR3, 1104700SN/A MISCREG_CR4, 1114700SN/A MISCREG_CR5, 1124700SN/A MISCREG_CR6, 1134700SN/A MISCREG_CR7, 1144700SN/A MISCREG_CR8, 1154700SN/A MISCREG_CR9, 1164700SN/A MISCREG_CR10, 1174700SN/A MISCREG_CR11, 1184700SN/A MISCREG_CR12, 1194700SN/A MISCREG_CR13, 1204700SN/A MISCREG_CR14, 1214700SN/A MISCREG_CR15, 1224700SN/A 1234700SN/A // Debug registers 1245025SN/A MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1254862SN/A MISCREG_DR0 = MISCREG_DR_BASE, 1264700SN/A MISCREG_DR1, 1274700SN/A MISCREG_DR2, 1284700SN/A MISCREG_DR3, 1294700SN/A MISCREG_DR4, 1304700SN/A MISCREG_DR5, 1314700SN/A MISCREG_DR6, 1324700SN/A MISCREG_DR7, 1334700SN/A 1344700SN/A // Flags register 1355025SN/A MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1364700SN/A 1375429SN/A //Register to keep handy values like the CPU mode in. 1385429SN/A MISCREG_M5_REG, 1395429SN/A 1405138SN/A /* 1415138SN/A * Model Specific Registers 1425138SN/A */ 1435138SN/A // Time stamp counter 1445138SN/A MISCREG_TSC, 1455138SN/A 1465138SN/A MISCREG_MTRRCAP, 1475138SN/A 1485138SN/A MISCREG_SYSENTER_CS, 1495138SN/A MISCREG_SYSENTER_ESP, 1505138SN/A MISCREG_SYSENTER_EIP, 1515138SN/A 1525138SN/A MISCREG_MCG_CAP, 1535138SN/A MISCREG_MCG_STATUS, 1545138SN/A MISCREG_MCG_CTL, 1555138SN/A 1565138SN/A MISCREG_DEBUG_CTL_MSR, 1575138SN/A 1585138SN/A MISCREG_LAST_BRANCH_FROM_IP, 1595138SN/A MISCREG_LAST_BRANCH_TO_IP, 1605138SN/A MISCREG_LAST_EXCEPTION_FROM_IP, 1615138SN/A MISCREG_LAST_EXCEPTION_TO_IP, 1625138SN/A 1635138SN/A MISCREG_MTRR_PHYS_BASE_BASE, 1645138SN/A MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1655138SN/A MISCREG_MTRR_PHYS_BASE_1, 1665138SN/A MISCREG_MTRR_PHYS_BASE_2, 1675138SN/A MISCREG_MTRR_PHYS_BASE_3, 1685138SN/A MISCREG_MTRR_PHYS_BASE_4, 1695138SN/A MISCREG_MTRR_PHYS_BASE_5, 1705138SN/A MISCREG_MTRR_PHYS_BASE_6, 1715138SN/A MISCREG_MTRR_PHYS_BASE_7, 1726346SN/A MISCREG_MTRR_PHYS_BASE_END, 1735138SN/A 1746346SN/A MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 1755138SN/A MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1765138SN/A MISCREG_MTRR_PHYS_MASK_1, 1775138SN/A MISCREG_MTRR_PHYS_MASK_2, 1785138SN/A MISCREG_MTRR_PHYS_MASK_3, 1795138SN/A MISCREG_MTRR_PHYS_MASK_4, 1805138SN/A MISCREG_MTRR_PHYS_MASK_5, 1815138SN/A MISCREG_MTRR_PHYS_MASK_6, 1825138SN/A MISCREG_MTRR_PHYS_MASK_7, 1836346SN/A MISCREG_MTRR_PHYS_MASK_END, 1845138SN/A 1856346SN/A MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 1865138SN/A MISCREG_MTRR_FIX_16K_80000, 1875138SN/A MISCREG_MTRR_FIX_16K_A0000, 1885138SN/A MISCREG_MTRR_FIX_4K_C0000, 1895149SN/A MISCREG_MTRR_FIX_4K_C8000, 1905138SN/A MISCREG_MTRR_FIX_4K_D0000, 1915138SN/A MISCREG_MTRR_FIX_4K_D8000, 1925138SN/A MISCREG_MTRR_FIX_4K_E0000, 1935138SN/A MISCREG_MTRR_FIX_4K_E8000, 1945138SN/A MISCREG_MTRR_FIX_4K_F0000, 1955138SN/A MISCREG_MTRR_FIX_4K_F8000, 1965138SN/A 1975138SN/A MISCREG_PAT, 1985138SN/A 1995138SN/A MISCREG_DEF_TYPE, 2005138SN/A 2015138SN/A MISCREG_MC_CTL_BASE, 2025138SN/A MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 2035138SN/A MISCREG_MC1_CTL, 2045138SN/A MISCREG_MC2_CTL, 2055138SN/A MISCREG_MC3_CTL, 2065138SN/A MISCREG_MC4_CTL, 2075419SN/A MISCREG_MC5_CTL, 2085419SN/A MISCREG_MC6_CTL, 2095419SN/A MISCREG_MC7_CTL, 2106346SN/A MISCREG_MC_CTL_END, 2115138SN/A 2126346SN/A MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 2135138SN/A MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 2145138SN/A MISCREG_MC1_STATUS, 2155138SN/A MISCREG_MC2_STATUS, 2165138SN/A MISCREG_MC3_STATUS, 2175138SN/A MISCREG_MC4_STATUS, 2185419SN/A MISCREG_MC5_STATUS, 2195419SN/A MISCREG_MC6_STATUS, 2205419SN/A MISCREG_MC7_STATUS, 2216346SN/A MISCREG_MC_STATUS_END, 2225138SN/A 2236346SN/A MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 2245138SN/A MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 2255138SN/A MISCREG_MC1_ADDR, 2265138SN/A MISCREG_MC2_ADDR, 2275138SN/A MISCREG_MC3_ADDR, 2285138SN/A MISCREG_MC4_ADDR, 2295419SN/A MISCREG_MC5_ADDR, 2305419SN/A MISCREG_MC6_ADDR, 2315419SN/A MISCREG_MC7_ADDR, 2326346SN/A MISCREG_MC_ADDR_END, 2335138SN/A 2346346SN/A MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 2355138SN/A MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 2365138SN/A MISCREG_MC1_MISC, 2375138SN/A MISCREG_MC2_MISC, 2385138SN/A MISCREG_MC3_MISC, 2395138SN/A MISCREG_MC4_MISC, 2405419SN/A MISCREG_MC5_MISC, 2415419SN/A MISCREG_MC6_MISC, 2425419SN/A MISCREG_MC7_MISC, 2436346SN/A MISCREG_MC_MISC_END, 2445138SN/A 2455135SN/A // Extended feature enable register 2466346SN/A MISCREG_EFER = MISCREG_MC_MISC_END, 2475135SN/A 2485138SN/A MISCREG_STAR, 2495138SN/A MISCREG_LSTAR, 2505138SN/A MISCREG_CSTAR, 2515138SN/A 2525138SN/A MISCREG_SF_MASK, 2535138SN/A 2545138SN/A MISCREG_KERNEL_GS_BASE, 2555138SN/A 2565138SN/A MISCREG_TSC_AUX, 2575138SN/A 2585138SN/A MISCREG_PERF_EVT_SEL_BASE, 2595138SN/A MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 2605138SN/A MISCREG_PERF_EVT_SEL1, 2615138SN/A MISCREG_PERF_EVT_SEL2, 2625138SN/A MISCREG_PERF_EVT_SEL3, 2636346SN/A MISCREG_PERF_EVT_SEL_END, 2645138SN/A 2656346SN/A MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 2665138SN/A MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 2675138SN/A MISCREG_PERF_EVT_CTR1, 2685138SN/A MISCREG_PERF_EVT_CTR2, 2695138SN/A MISCREG_PERF_EVT_CTR3, 2706346SN/A MISCREG_PERF_EVT_CTR_END, 2715138SN/A 2726346SN/A MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 2735138SN/A 2745138SN/A MISCREG_IORR_BASE_BASE, 2755138SN/A MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 2765138SN/A MISCREG_IORR_BASE1, 2776346SN/A MISCREG_IORR_BASE_END, 2785138SN/A 2796346SN/A MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 2805138SN/A MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 2815138SN/A MISCREG_IORR_MASK1, 2826346SN/A MISCREG_IORR_MASK_END, 2835138SN/A 2846346SN/A MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 2855138SN/A MISCREG_TOP_MEM2, 2865138SN/A 2875138SN/A MISCREG_VM_CR, 2885138SN/A MISCREG_IGNNE, 2895138SN/A MISCREG_SMM_CTL, 2905138SN/A MISCREG_VM_HSAVE_PA, 2915138SN/A 2925138SN/A /* 2935138SN/A * Segment registers 2945138SN/A */ 2954700SN/A // Segment selectors 2964862SN/A MISCREG_SEG_SEL_BASE, 2974862SN/A MISCREG_ES = MISCREG_SEG_SEL_BASE, 2984700SN/A MISCREG_CS, 2994700SN/A MISCREG_SS, 3004700SN/A MISCREG_DS, 3014700SN/A MISCREG_FS, 3024700SN/A MISCREG_GS, 3035294SN/A MISCREG_HS, 3045294SN/A MISCREG_TSL, 3055294SN/A MISCREG_TSG, 3065294SN/A MISCREG_LS, 3075294SN/A MISCREG_MS, 3085294SN/A MISCREG_TR, 3095294SN/A MISCREG_IDTR, 3104700SN/A 3114700SN/A // Hidden segment base field 3125294SN/A MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 3134862SN/A MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 3144700SN/A MISCREG_CS_BASE, 3154700SN/A MISCREG_SS_BASE, 3164700SN/A MISCREG_DS_BASE, 3174700SN/A MISCREG_FS_BASE, 3184700SN/A MISCREG_GS_BASE, 3195294SN/A MISCREG_HS_BASE, 3205294SN/A MISCREG_TSL_BASE, 3215294SN/A MISCREG_TSG_BASE, 3225294SN/A MISCREG_LS_BASE, 3235294SN/A MISCREG_MS_BASE, 3245294SN/A MISCREG_TR_BASE, 3255294SN/A MISCREG_IDTR_BASE, 3264700SN/A 3275289SN/A // The effective segment base, ie what is actually added to an 3285289SN/A // address. In 64 bit mode this can be different from the above, 3295289SN/A // namely 0. 3305294SN/A MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 3315289SN/A MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 3325289SN/A MISCREG_CS_EFF_BASE, 3335289SN/A MISCREG_SS_EFF_BASE, 3345289SN/A MISCREG_DS_EFF_BASE, 3355289SN/A MISCREG_FS_EFF_BASE, 3365289SN/A MISCREG_GS_EFF_BASE, 3375294SN/A MISCREG_HS_EFF_BASE, 3385294SN/A MISCREG_TSL_EFF_BASE, 3395294SN/A MISCREG_TSG_EFF_BASE, 3405294SN/A MISCREG_LS_EFF_BASE, 3415294SN/A MISCREG_MS_EFF_BASE, 3425294SN/A MISCREG_TR_EFF_BASE, 3435294SN/A MISCREG_IDTR_EFF_BASE, 3445289SN/A 3454700SN/A // Hidden segment limit field 3465294SN/A MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 3474862SN/A MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 3484700SN/A MISCREG_CS_LIMIT, 3494700SN/A MISCREG_SS_LIMIT, 3504700SN/A MISCREG_DS_LIMIT, 3514700SN/A MISCREG_FS_LIMIT, 3524700SN/A MISCREG_GS_LIMIT, 3535294SN/A MISCREG_HS_LIMIT, 3545294SN/A MISCREG_TSL_LIMIT, 3555294SN/A MISCREG_TSG_LIMIT, 3565294SN/A MISCREG_LS_LIMIT, 3575294SN/A MISCREG_MS_LIMIT, 3585294SN/A MISCREG_TR_LIMIT, 3595294SN/A MISCREG_IDTR_LIMIT, 3604700SN/A 3614700SN/A // Hidden segment limit attributes 3625294SN/A MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 3634862SN/A MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 3644700SN/A MISCREG_CS_ATTR, 3654700SN/A MISCREG_SS_ATTR, 3664700SN/A MISCREG_DS_ATTR, 3674700SN/A MISCREG_FS_ATTR, 3684700SN/A MISCREG_GS_ATTR, 3695294SN/A MISCREG_HS_ATTR, 3705294SN/A MISCREG_TSL_ATTR, 3715294SN/A MISCREG_TSG_ATTR, 3725294SN/A MISCREG_LS_ATTR, 3735294SN/A MISCREG_MS_ATTR, 3744700SN/A MISCREG_TR_ATTR, 3755294SN/A MISCREG_IDTR_ATTR, 3764700SN/A 3775082SN/A // Floating point control registers 3785294SN/A MISCREG_X87_TOP = 3795294SN/A MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 3805082SN/A 3816362SN/A MISCREG_MXCSR, 3826362SN/A MISCREG_FCW, 3836362SN/A MISCREG_FSW, 3846362SN/A MISCREG_FTW, 3856362SN/A MISCREG_FTAG, 3866362SN/A MISCREG_FISEG, 3876362SN/A MISCREG_FIOFF, 3886362SN/A MISCREG_FOSEG, 3896362SN/A MISCREG_FOOFF, 3906362SN/A MISCREG_FOP, 3916362SN/A 3924700SN/A //XXX Add "Model-Specific Registers" 3934700SN/A 3945360SN/A MISCREG_APIC_BASE, 3955360SN/A 3965360SN/A // "Fake" MSRs for internally implemented devices 3975357SN/A MISCREG_PCI_CONFIG_ADDRESS, 3985357SN/A 3995082SN/A NUM_MISCREGS 4004700SN/A }; 4014700SN/A 40211324Ssteve.reinhardt@amd.com static inline bool 40311324Ssteve.reinhardt@amd.com isValidMiscReg(int index) 40411324Ssteve.reinhardt@amd.com { 40511324Ssteve.reinhardt@amd.com return (index >= MISCREG_CR0 && index < NUM_MISCREGS && 40611324Ssteve.reinhardt@amd.com index != MISCREG_CR1 && 40711324Ssteve.reinhardt@amd.com !(index > MISCREG_CR4 && index < MISCREG_CR8) && 40811324Ssteve.reinhardt@amd.com !(index > MISCREG_CR8 && index <= MISCREG_CR15)); 40911324Ssteve.reinhardt@amd.com } 41011324Ssteve.reinhardt@amd.com 4115025SN/A static inline MiscRegIndex 4125025SN/A MISCREG_CR(int index) 4135025SN/A { 4146346SN/A assert(index >= 0 && index < NumCRegs); 4155025SN/A return (MiscRegIndex)(MISCREG_CR_BASE + index); 4165025SN/A } 4175025SN/A 4185025SN/A static inline MiscRegIndex 4195025SN/A MISCREG_DR(int index) 4205025SN/A { 4216346SN/A assert(index >= 0 && index < NumDRegs); 4225025SN/A return (MiscRegIndex)(MISCREG_DR_BASE + index); 4235025SN/A } 4245025SN/A 4255025SN/A static inline MiscRegIndex 4265138SN/A MISCREG_MTRR_PHYS_BASE(int index) 4275138SN/A { 4286346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 4296346SN/A MISCREG_MTRR_PHYS_BASE_BASE)); 4305138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 4315138SN/A } 4325138SN/A 4335138SN/A static inline MiscRegIndex 4345138SN/A MISCREG_MTRR_PHYS_MASK(int index) 4355138SN/A { 4366346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 4376346SN/A MISCREG_MTRR_PHYS_MASK_BASE)); 4385138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 4395138SN/A } 4405138SN/A 4415138SN/A static inline MiscRegIndex 4425138SN/A MISCREG_MC_CTL(int index) 4435138SN/A { 4446346SN/A assert(index >= 0 && index < (MISCREG_MC_CTL_END - 4456346SN/A MISCREG_MC_CTL_BASE)); 4465138SN/A return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 4475138SN/A } 4485138SN/A 4495138SN/A static inline MiscRegIndex 4505138SN/A MISCREG_MC_STATUS(int index) 4515138SN/A { 4526346SN/A assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 4536346SN/A MISCREG_MC_STATUS_BASE)); 4545138SN/A return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 4555138SN/A } 4565138SN/A 4575138SN/A static inline MiscRegIndex 4585138SN/A MISCREG_MC_ADDR(int index) 4595138SN/A { 4606346SN/A assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 4616346SN/A MISCREG_MC_ADDR_BASE)); 4625138SN/A return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 4635138SN/A } 4645138SN/A 4655138SN/A static inline MiscRegIndex 4665138SN/A MISCREG_MC_MISC(int index) 4675138SN/A { 4686346SN/A assert(index >= 0 && index < (MISCREG_MC_MISC_END - 4696346SN/A MISCREG_MC_MISC_BASE)); 4705138SN/A return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 4715138SN/A } 4725138SN/A 4735138SN/A static inline MiscRegIndex 4745138SN/A MISCREG_PERF_EVT_SEL(int index) 4755138SN/A { 4766346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 4776346SN/A MISCREG_PERF_EVT_SEL_BASE)); 4785138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 4795138SN/A } 4805138SN/A 4815138SN/A static inline MiscRegIndex 4825138SN/A MISCREG_PERF_EVT_CTR(int index) 4835138SN/A { 4846346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 4856346SN/A MISCREG_PERF_EVT_CTR_BASE)); 4865138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 4875138SN/A } 4885138SN/A 4895138SN/A static inline MiscRegIndex 4905138SN/A MISCREG_IORR_BASE(int index) 4915138SN/A { 4926346SN/A assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 4936346SN/A MISCREG_IORR_BASE_BASE)); 4945138SN/A return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 4955138SN/A } 4965138SN/A 4975138SN/A static inline MiscRegIndex 4985138SN/A MISCREG_IORR_MASK(int index) 4995138SN/A { 5006346SN/A assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 5016346SN/A MISCREG_IORR_MASK_BASE)); 5025138SN/A return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 5035138SN/A } 5045138SN/A 5055138SN/A static inline MiscRegIndex 5065025SN/A MISCREG_SEG_SEL(int index) 5075025SN/A { 5086346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5095025SN/A return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 5105025SN/A } 5115025SN/A 5125025SN/A static inline MiscRegIndex 5135025SN/A MISCREG_SEG_BASE(int index) 5145025SN/A { 5156346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5165025SN/A return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 5175025SN/A } 5185025SN/A 5195025SN/A static inline MiscRegIndex 5205289SN/A MISCREG_SEG_EFF_BASE(int index) 5215289SN/A { 5226346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5235289SN/A return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 5245289SN/A } 5255289SN/A 5265289SN/A static inline MiscRegIndex 5275025SN/A MISCREG_SEG_LIMIT(int index) 5285025SN/A { 5296346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5305025SN/A return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 5315025SN/A } 5325025SN/A 5335025SN/A static inline MiscRegIndex 5345025SN/A MISCREG_SEG_ATTR(int index) 5355025SN/A { 5366346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5375025SN/A return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 5385025SN/A } 5395025SN/A 5404700SN/A /** 5414700SN/A * A type to describe the condition code bits of the RFLAGS register, 5424700SN/A * plus two flags, EZF and ECF, which are only visible to microcode. 5434700SN/A */ 5444684SN/A BitUnion64(CCFlagBits) 5455138SN/A Bitfield<11> of; 5465138SN/A Bitfield<7> sf; 5475138SN/A Bitfield<6> zf; 5485138SN/A Bitfield<5> ezf; 5495138SN/A Bitfield<4> af; 5505138SN/A Bitfield<3> ecf; 5515138SN/A Bitfield<2> pf; 5525138SN/A Bitfield<0> cf; 5534684SN/A EndBitUnion(CCFlagBits) 5544700SN/A 5554700SN/A /** 5564700SN/A * RFLAGS 5574700SN/A */ 5584700SN/A BitUnion64(RFLAGS) 5595138SN/A Bitfield<21> id; // ID Flag 5605138SN/A Bitfield<20> vip; // Virtual Interrupt Pending 5615138SN/A Bitfield<19> vif; // Virtual Interrupt Flag 5625138SN/A Bitfield<18> ac; // Alignment Check 5635138SN/A Bitfield<17> vm; // Virtual-8086 Mode 5645138SN/A Bitfield<16> rf; // Resume Flag 5655138SN/A Bitfield<14> nt; // Nested Task 5665138SN/A Bitfield<13, 12> iopl; // I/O Privilege Level 5675138SN/A Bitfield<11> of; // Overflow Flag 5685138SN/A Bitfield<10> df; // Direction Flag 5695138SN/A Bitfield<9> intf; // Interrupt Flag 5705138SN/A Bitfield<8> tf; // Trap Flag 5715138SN/A Bitfield<7> sf; // Sign Flag 5725138SN/A Bitfield<6> zf; // Zero Flag 5735138SN/A Bitfield<4> af; // Auxiliary Flag 5745138SN/A Bitfield<2> pf; // Parity Flag 5755138SN/A Bitfield<0> cf; // Carry Flag 5764700SN/A EndBitUnion(RFLAGS) 5774700SN/A 5785429SN/A BitUnion64(HandyM5Reg) 5795429SN/A Bitfield<0> mode; 5805429SN/A Bitfield<3, 1> submode; 5815429SN/A Bitfield<5, 4> cpl; 5826141SN/A Bitfield<6> paging; 5836141SN/A Bitfield<7> prot; 5846142SN/A Bitfield<9, 8> defOp; 5856142SN/A Bitfield<11, 10> altOp; 5866142SN/A Bitfield<13, 12> defAddr; 5876142SN/A Bitfield<15, 14> altAddr; 5886142SN/A Bitfield<17, 16> stack; 5895429SN/A EndBitUnion(HandyM5Reg) 5905429SN/A 5914700SN/A /** 5924700SN/A * Control registers 5934700SN/A */ 5944700SN/A BitUnion64(CR0) 5955138SN/A Bitfield<31> pg; // Paging 5965138SN/A Bitfield<30> cd; // Cache Disable 5975138SN/A Bitfield<29> nw; // Not Writethrough 5985138SN/A Bitfield<18> am; // Alignment Mask 5995138SN/A Bitfield<16> wp; // Write Protect 6005138SN/A Bitfield<5> ne; // Numeric Error 6015138SN/A Bitfield<4> et; // Extension Type 6025138SN/A Bitfield<3> ts; // Task Switched 6035138SN/A Bitfield<2> em; // Emulation 6045138SN/A Bitfield<1> mp; // Monitor Coprocessor 6055138SN/A Bitfield<0> pe; // Protection Enabled 6064700SN/A EndBitUnion(CR0) 6074700SN/A 6084700SN/A // Page Fault Virtual Address 6094700SN/A BitUnion64(CR2) 6104700SN/A Bitfield<31, 0> legacy; 6114700SN/A EndBitUnion(CR2) 6124700SN/A 6134700SN/A BitUnion64(CR3) 6145138SN/A Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 6154700SN/A // Base Address 6165138SN/A Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 6174700SN/A // Base Address 6185138SN/A Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 6194700SN/A // Base Address 6205138SN/A Bitfield<4> pcd; // Page-Level Cache Disable 6215138SN/A Bitfield<3> pwt; // Page-Level Writethrough 6224700SN/A EndBitUnion(CR3) 6234700SN/A 6244700SN/A BitUnion64(CR4) 62510554Salexandru.dutu@amd.com Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States 62610554Salexandru.dutu@amd.com Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE, 62710554Salexandru.dutu@amd.com // WRGSBASE instructions 6285138SN/A Bitfield<10> osxmmexcpt; // Operating System Unmasked 6294700SN/A // Exception Support 6305138SN/A Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 6315138SN/A Bitfield<8> pce; // Performance-Monitoring Counter Enable 6325138SN/A Bitfield<7> pge; // Page-Global Enable 6335138SN/A Bitfield<6> mce; // Machine Check Enable 6345138SN/A Bitfield<5> pae; // Physical-Address Extension 6355138SN/A Bitfield<4> pse; // Page Size Extensions 6365138SN/A Bitfield<3> de; // Debugging Extensions 6375138SN/A Bitfield<2> tsd; // Time Stamp Disable 6385138SN/A Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 6395138SN/A Bitfield<0> vme; // Virtual-8086 Mode Extensions 6404700SN/A EndBitUnion(CR4) 6414700SN/A 6424700SN/A BitUnion64(CR8) 6435138SN/A Bitfield<3, 0> tpr; // Task Priority Register 6445138SN/A EndBitUnion(CR8) 6455138SN/A 6465925SN/A BitUnion64(DR6) 6475925SN/A Bitfield<0> b0; 6485925SN/A Bitfield<1> b1; 6495925SN/A Bitfield<2> b2; 6505925SN/A Bitfield<3> b3; 6515925SN/A Bitfield<13> bd; 6525925SN/A Bitfield<14> bs; 6535925SN/A Bitfield<15> bt; 6545925SN/A EndBitUnion(DR6) 6555925SN/A 6565925SN/A BitUnion64(DR7) 6575925SN/A Bitfield<0> l0; 6585925SN/A Bitfield<1> g0; 6595925SN/A Bitfield<2> l1; 6605925SN/A Bitfield<3> g1; 6615925SN/A Bitfield<4> l2; 6625925SN/A Bitfield<5> g2; 6635925SN/A Bitfield<6> l3; 6645925SN/A Bitfield<7> g3; 6655925SN/A Bitfield<8> le; 6665925SN/A Bitfield<9> ge; 6675925SN/A Bitfield<13> gd; 6685925SN/A Bitfield<17, 16> rw0; 6695925SN/A Bitfield<19, 18> len0; 6705925SN/A Bitfield<21, 20> rw1; 6715925SN/A Bitfield<23, 22> len1; 6725925SN/A Bitfield<25, 24> rw2; 6735925SN/A Bitfield<27, 26> len2; 6745925SN/A Bitfield<29, 28> rw3; 6755925SN/A Bitfield<31, 30> len3; 6765925SN/A EndBitUnion(DR7) 6775925SN/A 6785138SN/A // MTRR capabilities 6795138SN/A BitUnion64(MTRRcap) 6805138SN/A Bitfield<7, 0> vcnt; // Variable-Range Register Count 6815138SN/A Bitfield<8> fix; // Fixed-Range Registers 6825138SN/A Bitfield<10> wc; // Write-Combining 6835138SN/A EndBitUnion(MTRRcap) 6845138SN/A 6855138SN/A /** 6865138SN/A * SYSENTER configuration registers 6875138SN/A */ 6885138SN/A BitUnion64(SysenterCS) 6895138SN/A Bitfield<15, 0> targetCS; 6905138SN/A EndBitUnion(SysenterCS) 6915138SN/A 6925138SN/A BitUnion64(SysenterESP) 6935138SN/A Bitfield<31, 0> targetESP; 6945138SN/A EndBitUnion(SysenterESP) 6955138SN/A 6965138SN/A BitUnion64(SysenterEIP) 6975138SN/A Bitfield<31, 0> targetEIP; 6985138SN/A EndBitUnion(SysenterEIP) 6995138SN/A 7005138SN/A /** 7015138SN/A * Global machine check registers 7025138SN/A */ 7035138SN/A BitUnion64(McgCap) 7045138SN/A Bitfield<7, 0> count; // Number of error reporting register banks 7055138SN/A Bitfield<8> MCGCP; // MCG_CTL register present. 7065138SN/A EndBitUnion(McgCap) 7075138SN/A 7085138SN/A BitUnion64(McgStatus) 7095138SN/A Bitfield<0> ripv; // Restart-IP valid 7105138SN/A Bitfield<1> eipv; // Error-IP valid 7115138SN/A Bitfield<2> mcip; // Machine check in-progress 7125138SN/A EndBitUnion(McgStatus) 7135138SN/A 7145138SN/A BitUnion64(DebugCtlMsr) 7155138SN/A Bitfield<0> lbr; // Last-branch record 7165138SN/A Bitfield<1> btf; // Branch single step 7175138SN/A Bitfield<2> pb0; // Performance monitoring pin control 0 7185138SN/A Bitfield<3> pb1; // Performance monitoring pin control 1 7195138SN/A Bitfield<4> pb2; // Performance monitoring pin control 2 7205138SN/A Bitfield<5> pb3; // Performance monitoring pin control 3 7215138SN/A /*uint64_t pb(int index) 7225138SN/A { 7235138SN/A return bits(__data, index + 2); 7245138SN/A }*/ 7255138SN/A EndBitUnion(DebugCtlMsr) 7265138SN/A 7275138SN/A BitUnion64(MtrrPhysBase) 7285138SN/A Bitfield<7, 0> type; // Default memory type 7295138SN/A Bitfield<51, 12> physbase; // Range physical base address 7305138SN/A EndBitUnion(MtrrPhysBase) 7315138SN/A 7325138SN/A BitUnion64(MtrrPhysMask) 7335138SN/A Bitfield<11> valid; // MTRR pair enable 7345138SN/A Bitfield<51, 12> physmask; // Range physical mask 7355138SN/A EndBitUnion(MtrrPhysMask) 7365138SN/A 7375138SN/A BitUnion64(MtrrFixed) 7385138SN/A /*uint64_t type(int index) 7395138SN/A { 7405138SN/A return bits(__data, index * 8 + 7, index * 8); 7415138SN/A }*/ 7425138SN/A EndBitUnion(MtrrFixed) 7435138SN/A 7445138SN/A BitUnion64(Pat) 7455138SN/A /*uint64_t pa(int index) 7465138SN/A { 7475138SN/A return bits(__data, index * 8 + 2, index * 8); 7485138SN/A }*/ 7495138SN/A EndBitUnion(Pat) 7505138SN/A 7515138SN/A BitUnion64(MtrrDefType) 7525138SN/A Bitfield<7, 0> type; // Default type 7535138SN/A Bitfield<10> fe; // Fixed range enable 7545138SN/A Bitfield<11> e; // MTRR enable 7555138SN/A EndBitUnion(MtrrDefType) 7565138SN/A 7575138SN/A /** 7585138SN/A * Machine check 7595138SN/A */ 7605138SN/A BitUnion64(McStatus) 7615138SN/A Bitfield<15,0> mcaErrorCode; 7625138SN/A Bitfield<31,16> modelSpecificCode; 7635138SN/A Bitfield<56,32> otherInfo; 7645138SN/A Bitfield<57> pcc; // Processor-context corrupt 7655138SN/A Bitfield<58> addrv; // Error-address register valid 7665138SN/A Bitfield<59> miscv; // Miscellaneous-error register valid 7675138SN/A Bitfield<60> en; // Error condition enabled 7685138SN/A Bitfield<61> uc; // Uncorrected error 7695138SN/A Bitfield<62> over; // Status register overflow 7705138SN/A Bitfield<63> val; // Valid 7715138SN/A EndBitUnion(McStatus) 7725138SN/A 7735138SN/A BitUnion64(McCtl) 7745138SN/A /*uint64_t en(int index) 7755138SN/A { 7765138SN/A return bits(__data, index); 7775138SN/A }*/ 7785138SN/A EndBitUnion(McCtl) 7795138SN/A 7805138SN/A // Extended feature enable register 7815138SN/A BitUnion64(Efer) 7825138SN/A Bitfield<0> sce; // System call extensions 7835138SN/A Bitfield<8> lme; // Long mode enable 7845138SN/A Bitfield<10> lma; // Long mode active 7855138SN/A Bitfield<11> nxe; // No-execute enable 7865138SN/A Bitfield<12> svme; // Secure virtual machine enable 7875138SN/A Bitfield<14> ffxsr; // Fast fxsave/fxrstor 7885138SN/A EndBitUnion(Efer) 7895138SN/A 7905138SN/A BitUnion64(Star) 7915138SN/A Bitfield<31,0> targetEip; 7925138SN/A Bitfield<47,32> syscallCsAndSs; 7935138SN/A Bitfield<63,48> sysretCsAndSs; 7945138SN/A EndBitUnion(Star) 7955138SN/A 7965138SN/A BitUnion64(SfMask) 7975138SN/A Bitfield<31,0> mask; 7985138SN/A EndBitUnion(SfMask) 7995138SN/A 8005138SN/A BitUnion64(PerfEvtSel) 8015138SN/A Bitfield<7,0> eventMask; 8025138SN/A Bitfield<15,8> unitMask; 8035138SN/A Bitfield<16> usr; // User mode 8045138SN/A Bitfield<17> os; // Operating-system mode 8055138SN/A Bitfield<18> e; // Edge detect 8065138SN/A Bitfield<19> pc; // Pin control 8075138SN/A Bitfield<20> intEn; // Interrupt enable 8085138SN/A Bitfield<22> en; // Counter enable 8095138SN/A Bitfield<23> inv; // Invert mask 8105138SN/A Bitfield<31,24> counterMask; 8115138SN/A EndBitUnion(PerfEvtSel) 8125138SN/A 8135138SN/A BitUnion32(Syscfg) 8145138SN/A Bitfield<18> mfde; // MtrrFixDramEn 8155138SN/A Bitfield<19> mfdm; // MtrrFixDramModEn 8165138SN/A Bitfield<20> mvdm; // MtrrVarDramEn 8175138SN/A Bitfield<21> tom2; // MtrrTom2En 8185138SN/A EndBitUnion(Syscfg) 8195138SN/A 8205138SN/A BitUnion64(IorrBase) 8215138SN/A Bitfield<3> wr; // WrMem Enable 8225138SN/A Bitfield<4> rd; // RdMem Enable 8235138SN/A Bitfield<51,12> physbase; // Range physical base address 8245138SN/A EndBitUnion(IorrBase) 8255138SN/A 8265138SN/A BitUnion64(IorrMask) 8275138SN/A Bitfield<11> v; // I/O register pair enable (valid) 8285138SN/A Bitfield<51,12> physmask; // Range physical mask 8295138SN/A EndBitUnion(IorrMask) 8305138SN/A 8315138SN/A BitUnion64(Tom) 8325138SN/A Bitfield<51,23> physAddr; // Top of memory physical address 8335138SN/A EndBitUnion(Tom) 8345138SN/A 8355138SN/A BitUnion64(VmCrMsr) 8365138SN/A Bitfield<0> dpd; 8375138SN/A Bitfield<1> rInit; 8385138SN/A Bitfield<2> disA20M; 8395138SN/A EndBitUnion(VmCrMsr) 8405138SN/A 8415138SN/A BitUnion64(IgnneMsr) 8425138SN/A Bitfield<0> ignne; 8435138SN/A EndBitUnion(IgnneMsr) 8445138SN/A 8455138SN/A BitUnion64(SmmCtlMsr) 8465138SN/A Bitfield<0> dismiss; 8475138SN/A Bitfield<1> enter; 8485138SN/A Bitfield<2> smiCycle; 8495138SN/A Bitfield<3> exit; 8505138SN/A Bitfield<4> rsmCycle; 8515138SN/A EndBitUnion(SmmCtlMsr) 8524700SN/A 8534700SN/A /** 8544700SN/A * Segment Selector 8554700SN/A */ 8564700SN/A BitUnion64(SegSelector) 8575294SN/A // The following bitfield is not defined in the ISA, but it's useful 8585294SN/A // when checking selectors in larger data types to make sure they 8595294SN/A // aren't too large. 8605294SN/A Bitfield<63, 3> esi; // Extended selector 8615138SN/A Bitfield<15, 3> si; // Selector Index 8625138SN/A Bitfield<2> ti; // Table Indicator 8635138SN/A Bitfield<1, 0> rpl; // Requestor Privilege Level 8644700SN/A EndBitUnion(SegSelector) 8654700SN/A 8664700SN/A /** 8674700SN/A * Segment Descriptors 8684700SN/A */ 8694700SN/A 8704700SN/A BitUnion64(SegDescriptor) 8714700SN/A Bitfield<63, 56> baseHigh; 8724700SN/A Bitfield<39, 16> baseLow; 8735138SN/A Bitfield<55> g; // Granularity 8745138SN/A Bitfield<54> d; // Default Operand Size 8755138SN/A Bitfield<54> b; // Default Operand Size 8765138SN/A Bitfield<53> l; // Long Attribute Bit 8775138SN/A Bitfield<52> avl; // Available To Software 8784700SN/A Bitfield<51, 48> limitHigh; 8794700SN/A Bitfield<15, 0> limitLow; 8805138SN/A Bitfield<47> p; // Present 8815138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 8825138SN/A Bitfield<44> s; // System 8834700SN/A SubBitUnion(type, 43, 40) 8844700SN/A // Specifies whether this descriptor is for code or data. 8854700SN/A Bitfield<43> codeOrData; 8864700SN/A 8874700SN/A // These bit fields are for code segments 8885138SN/A Bitfield<42> c; // Conforming 8895138SN/A Bitfield<41> r; // Readable 8904700SN/A 8914700SN/A // These bit fields are for data segments 8925138SN/A Bitfield<42> e; // Expand-Down 8935138SN/A Bitfield<41> w; // Writable 8944700SN/A 8954700SN/A // This is used for both code and data segments. 8965138SN/A Bitfield<40> a; // Accessed 8974700SN/A EndSubBitUnion(type) 8984700SN/A EndBitUnion(SegDescriptor) 8994700SN/A 90010554Salexandru.dutu@amd.com /** 90110554Salexandru.dutu@amd.com * TSS Descriptor (long mode - 128 bits) 90210554Salexandru.dutu@amd.com * the lower 64 bits 90310554Salexandru.dutu@amd.com */ 90410554Salexandru.dutu@amd.com BitUnion64(TSSlow) 90510554Salexandru.dutu@amd.com Bitfield<63, 56> baseHigh; 90610554Salexandru.dutu@amd.com Bitfield<39, 16> baseLow; 90710554Salexandru.dutu@amd.com Bitfield<55> g; // Granularity 90810554Salexandru.dutu@amd.com Bitfield<52> avl; // Available To Software 90910554Salexandru.dutu@amd.com Bitfield<51, 48> limitHigh; 91010554Salexandru.dutu@amd.com Bitfield<15, 0> limitLow; 91110554Salexandru.dutu@amd.com Bitfield<47> p; // Present 91210554Salexandru.dutu@amd.com Bitfield<46, 45> dpl; // Descriptor Privilege-Level 91310554Salexandru.dutu@amd.com SubBitUnion(type, 43, 40) 91410554Salexandru.dutu@amd.com // Specifies whether this descriptor is for code or data. 91510554Salexandru.dutu@amd.com Bitfield<43> codeOrData; 91610554Salexandru.dutu@amd.com 91710554Salexandru.dutu@amd.com // These bit fields are for code segments 91810554Salexandru.dutu@amd.com Bitfield<42> c; // Conforming 91910554Salexandru.dutu@amd.com Bitfield<41> r; // Readable 92010554Salexandru.dutu@amd.com 92110554Salexandru.dutu@amd.com // These bit fields are for data segments 92210554Salexandru.dutu@amd.com Bitfield<42> e; // Expand-Down 92310554Salexandru.dutu@amd.com Bitfield<41> w; // Writable 92410554Salexandru.dutu@amd.com 92510554Salexandru.dutu@amd.com // This is used for both code and data segments. 92610554Salexandru.dutu@amd.com Bitfield<40> a; // Accessed 92710554Salexandru.dutu@amd.com EndSubBitUnion(type) 92810554Salexandru.dutu@amd.com EndBitUnion(TSSlow) 92910554Salexandru.dutu@amd.com 93010554Salexandru.dutu@amd.com /** 93110554Salexandru.dutu@amd.com * TSS Descriptor (long mode - 128 bits) 93210554Salexandru.dutu@amd.com * the upper 64 bits 93310554Salexandru.dutu@amd.com */ 93410554Salexandru.dutu@amd.com BitUnion64(TSShigh) 93510554Salexandru.dutu@amd.com Bitfield<31, 0> base; 93610554Salexandru.dutu@amd.com EndBitUnion(TSShigh) 93710554Salexandru.dutu@amd.com 9385138SN/A BitUnion64(SegAttr) 9396222SN/A Bitfield<1, 0> dpl; 9406222SN/A Bitfield<2> unusable; 9416222SN/A Bitfield<3> defaultSize; 9426222SN/A Bitfield<4> longMode; 9436222SN/A Bitfield<5> avl; 9446222SN/A Bitfield<6> granularity; 9456222SN/A Bitfield<7> present; 9466222SN/A Bitfield<11, 8> type; 9476222SN/A Bitfield<12> writable; 9486222SN/A Bitfield<13> readable; 9496222SN/A Bitfield<14> expandDown; 9506222SN/A Bitfield<15> system; 9515138SN/A EndBitUnion(SegAttr) 9525138SN/A 9534700SN/A BitUnion64(GateDescriptor) 9544700SN/A Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 9554700SN/A Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 9564700SN/A Bitfield<31, 16> selector; // Target Code-Segment Selector 9575138SN/A Bitfield<47> p; // Present 9585138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 9594700SN/A Bitfield<43, 40> type; 9604700SN/A Bitfield<36, 32> count; // Parameter Count 9614700SN/A EndBitUnion(GateDescriptor) 9624700SN/A 9634700SN/A /** 96410554Salexandru.dutu@amd.com * Long Mode Gate Descriptor 96510554Salexandru.dutu@amd.com */ 96610554Salexandru.dutu@amd.com BitUnion64(GateDescriptorLow) 96710554Salexandru.dutu@amd.com Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 96810554Salexandru.dutu@amd.com Bitfield<47> p; // Present 96910554Salexandru.dutu@amd.com Bitfield<46, 45> dpl; // Descriptor Privilege-Level 97010554Salexandru.dutu@amd.com Bitfield<43, 40> type; 97110554Salexandru.dutu@amd.com Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling 97210554Salexandru.dutu@amd.com Bitfield<31, 16> selector; // Target Code-Segment Selector 97310554Salexandru.dutu@amd.com Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 97410554Salexandru.dutu@amd.com EndBitUnion(GateDescriptorLow) 97510554Salexandru.dutu@amd.com 97610554Salexandru.dutu@amd.com BitUnion64(GateDescriptorHigh) 97710554Salexandru.dutu@amd.com Bitfield<31, 0> offset; // Target Code-Segment Offset 97810554Salexandru.dutu@amd.com EndBitUnion(GateDescriptorHigh) 97910554Salexandru.dutu@amd.com 98010554Salexandru.dutu@amd.com /** 9814700SN/A * Descriptor-Table Registers 9824700SN/A */ 9834700SN/A BitUnion64(GDTR) 9844700SN/A EndBitUnion(GDTR) 9854700SN/A 9864700SN/A BitUnion64(IDTR) 9874700SN/A EndBitUnion(IDTR) 9884700SN/A 9894700SN/A BitUnion64(LDTR) 9904700SN/A EndBitUnion(LDTR) 9914700SN/A 9924700SN/A /** 9934700SN/A * Task Register 9944700SN/A */ 9954700SN/A BitUnion64(TR) 9964700SN/A EndBitUnion(TR) 9975360SN/A 9985360SN/A 9995360SN/A /** 10005360SN/A * Local APIC Base Register 10015360SN/A */ 10025360SN/A BitUnion64(LocalApicBase) 10035360SN/A Bitfield<51, 12> base; 10045360SN/A Bitfield<11> enable; 10055360SN/A Bitfield<8> bsp; 10065360SN/A EndBitUnion(LocalApicBase) 10078902Sandreas.hansson@arm.com} 10084684SN/A 10094684SN/A#endif // __ARCH_X86_INTREGS_HH__ 1010