misc.hh revision 11324
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_MISCREGS_HH__ 41#define __ARCH_X86_MISCREGS_HH__ 42 43#include "arch/x86/regs/segment.hh" 44#include "arch/x86/x86_traits.hh" 45#include "base/bitunion.hh" 46 47//These get defined in some system headers (at least termbits.h). That confuses 48//things here significantly. 49#undef CR0 50#undef CR2 51#undef CR3 52 53namespace X86ISA 54{ 55 enum CondFlagBit { 56 CFBit = 1 << 0, 57 PFBit = 1 << 2, 58 ECFBit = 1 << 3, 59 AFBit = 1 << 4, 60 EZFBit = 1 << 5, 61 ZFBit = 1 << 6, 62 SFBit = 1 << 7, 63 DFBit = 1 << 10, 64 OFBit = 1 << 11 65 }; 66 67 const uint32_t cfofMask = CFBit | OFBit; 68 const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit; 69 70 enum RFLAGBit { 71 TFBit = 1 << 8, 72 IFBit = 1 << 9, 73 NTBit = 1 << 14, 74 RFBit = 1 << 16, 75 VMBit = 1 << 17, 76 ACBit = 1 << 18, 77 VIFBit = 1 << 19, 78 VIPBit = 1 << 20, 79 IDBit = 1 << 21 80 }; 81 82 enum X87StatusBit { 83 // Exception Flags 84 IEBit = 1 << 0, 85 DEBit = 1 << 1, 86 ZEBit = 1 << 2, 87 OEBit = 1 << 3, 88 UEBit = 1 << 4, 89 PEBit = 1 << 5, 90 91 // !Exception Flags 92 StackFaultBit = 1 << 6, 93 ErrSummaryBit = 1 << 7, 94 CC0Bit = 1 << 8, 95 CC1Bit = 1 << 9, 96 CC2Bit = 1 << 10, 97 CC3Bit = 1 << 14, 98 BusyBit = 1 << 15, 99 }; 100 101 enum MiscRegIndex 102 { 103 // Control registers 104 // Most of these are invalid. See isValidMiscReg() below. 105 MISCREG_CR_BASE, 106 MISCREG_CR0 = MISCREG_CR_BASE, 107 MISCREG_CR1, 108 MISCREG_CR2, 109 MISCREG_CR3, 110 MISCREG_CR4, 111 MISCREG_CR5, 112 MISCREG_CR6, 113 MISCREG_CR7, 114 MISCREG_CR8, 115 MISCREG_CR9, 116 MISCREG_CR10, 117 MISCREG_CR11, 118 MISCREG_CR12, 119 MISCREG_CR13, 120 MISCREG_CR14, 121 MISCREG_CR15, 122 123 // Debug registers 124 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 125 MISCREG_DR0 = MISCREG_DR_BASE, 126 MISCREG_DR1, 127 MISCREG_DR2, 128 MISCREG_DR3, 129 MISCREG_DR4, 130 MISCREG_DR5, 131 MISCREG_DR6, 132 MISCREG_DR7, 133 134 // Flags register 135 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 136 137 //Register to keep handy values like the CPU mode in. 138 MISCREG_M5_REG, 139 140 /* 141 * Model Specific Registers 142 */ 143 // Time stamp counter 144 MISCREG_TSC, 145 146 MISCREG_MTRRCAP, 147 148 MISCREG_SYSENTER_CS, 149 MISCREG_SYSENTER_ESP, 150 MISCREG_SYSENTER_EIP, 151 152 MISCREG_MCG_CAP, 153 MISCREG_MCG_STATUS, 154 MISCREG_MCG_CTL, 155 156 MISCREG_DEBUG_CTL_MSR, 157 158 MISCREG_LAST_BRANCH_FROM_IP, 159 MISCREG_LAST_BRANCH_TO_IP, 160 MISCREG_LAST_EXCEPTION_FROM_IP, 161 MISCREG_LAST_EXCEPTION_TO_IP, 162 163 MISCREG_MTRR_PHYS_BASE_BASE, 164 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 165 MISCREG_MTRR_PHYS_BASE_1, 166 MISCREG_MTRR_PHYS_BASE_2, 167 MISCREG_MTRR_PHYS_BASE_3, 168 MISCREG_MTRR_PHYS_BASE_4, 169 MISCREG_MTRR_PHYS_BASE_5, 170 MISCREG_MTRR_PHYS_BASE_6, 171 MISCREG_MTRR_PHYS_BASE_7, 172 MISCREG_MTRR_PHYS_BASE_END, 173 174 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 175 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 176 MISCREG_MTRR_PHYS_MASK_1, 177 MISCREG_MTRR_PHYS_MASK_2, 178 MISCREG_MTRR_PHYS_MASK_3, 179 MISCREG_MTRR_PHYS_MASK_4, 180 MISCREG_MTRR_PHYS_MASK_5, 181 MISCREG_MTRR_PHYS_MASK_6, 182 MISCREG_MTRR_PHYS_MASK_7, 183 MISCREG_MTRR_PHYS_MASK_END, 184 185 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 186 MISCREG_MTRR_FIX_16K_80000, 187 MISCREG_MTRR_FIX_16K_A0000, 188 MISCREG_MTRR_FIX_4K_C0000, 189 MISCREG_MTRR_FIX_4K_C8000, 190 MISCREG_MTRR_FIX_4K_D0000, 191 MISCREG_MTRR_FIX_4K_D8000, 192 MISCREG_MTRR_FIX_4K_E0000, 193 MISCREG_MTRR_FIX_4K_E8000, 194 MISCREG_MTRR_FIX_4K_F0000, 195 MISCREG_MTRR_FIX_4K_F8000, 196 197 MISCREG_PAT, 198 199 MISCREG_DEF_TYPE, 200 201 MISCREG_MC_CTL_BASE, 202 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 203 MISCREG_MC1_CTL, 204 MISCREG_MC2_CTL, 205 MISCREG_MC3_CTL, 206 MISCREG_MC4_CTL, 207 MISCREG_MC5_CTL, 208 MISCREG_MC6_CTL, 209 MISCREG_MC7_CTL, 210 MISCREG_MC_CTL_END, 211 212 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 213 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 214 MISCREG_MC1_STATUS, 215 MISCREG_MC2_STATUS, 216 MISCREG_MC3_STATUS, 217 MISCREG_MC4_STATUS, 218 MISCREG_MC5_STATUS, 219 MISCREG_MC6_STATUS, 220 MISCREG_MC7_STATUS, 221 MISCREG_MC_STATUS_END, 222 223 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 224 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 225 MISCREG_MC1_ADDR, 226 MISCREG_MC2_ADDR, 227 MISCREG_MC3_ADDR, 228 MISCREG_MC4_ADDR, 229 MISCREG_MC5_ADDR, 230 MISCREG_MC6_ADDR, 231 MISCREG_MC7_ADDR, 232 MISCREG_MC_ADDR_END, 233 234 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 235 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 236 MISCREG_MC1_MISC, 237 MISCREG_MC2_MISC, 238 MISCREG_MC3_MISC, 239 MISCREG_MC4_MISC, 240 MISCREG_MC5_MISC, 241 MISCREG_MC6_MISC, 242 MISCREG_MC7_MISC, 243 MISCREG_MC_MISC_END, 244 245 // Extended feature enable register 246 MISCREG_EFER = MISCREG_MC_MISC_END, 247 248 MISCREG_STAR, 249 MISCREG_LSTAR, 250 MISCREG_CSTAR, 251 252 MISCREG_SF_MASK, 253 254 MISCREG_KERNEL_GS_BASE, 255 256 MISCREG_TSC_AUX, 257 258 MISCREG_PERF_EVT_SEL_BASE, 259 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 260 MISCREG_PERF_EVT_SEL1, 261 MISCREG_PERF_EVT_SEL2, 262 MISCREG_PERF_EVT_SEL3, 263 MISCREG_PERF_EVT_SEL_END, 264 265 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 266 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 267 MISCREG_PERF_EVT_CTR1, 268 MISCREG_PERF_EVT_CTR2, 269 MISCREG_PERF_EVT_CTR3, 270 MISCREG_PERF_EVT_CTR_END, 271 272 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 273 274 MISCREG_IORR_BASE_BASE, 275 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 276 MISCREG_IORR_BASE1, 277 MISCREG_IORR_BASE_END, 278 279 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 280 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 281 MISCREG_IORR_MASK1, 282 MISCREG_IORR_MASK_END, 283 284 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 285 MISCREG_TOP_MEM2, 286 287 MISCREG_VM_CR, 288 MISCREG_IGNNE, 289 MISCREG_SMM_CTL, 290 MISCREG_VM_HSAVE_PA, 291 292 /* 293 * Segment registers 294 */ 295 // Segment selectors 296 MISCREG_SEG_SEL_BASE, 297 MISCREG_ES = MISCREG_SEG_SEL_BASE, 298 MISCREG_CS, 299 MISCREG_SS, 300 MISCREG_DS, 301 MISCREG_FS, 302 MISCREG_GS, 303 MISCREG_HS, 304 MISCREG_TSL, 305 MISCREG_TSG, 306 MISCREG_LS, 307 MISCREG_MS, 308 MISCREG_TR, 309 MISCREG_IDTR, 310 311 // Hidden segment base field 312 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 313 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 314 MISCREG_CS_BASE, 315 MISCREG_SS_BASE, 316 MISCREG_DS_BASE, 317 MISCREG_FS_BASE, 318 MISCREG_GS_BASE, 319 MISCREG_HS_BASE, 320 MISCREG_TSL_BASE, 321 MISCREG_TSG_BASE, 322 MISCREG_LS_BASE, 323 MISCREG_MS_BASE, 324 MISCREG_TR_BASE, 325 MISCREG_IDTR_BASE, 326 327 // The effective segment base, ie what is actually added to an 328 // address. In 64 bit mode this can be different from the above, 329 // namely 0. 330 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 331 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 332 MISCREG_CS_EFF_BASE, 333 MISCREG_SS_EFF_BASE, 334 MISCREG_DS_EFF_BASE, 335 MISCREG_FS_EFF_BASE, 336 MISCREG_GS_EFF_BASE, 337 MISCREG_HS_EFF_BASE, 338 MISCREG_TSL_EFF_BASE, 339 MISCREG_TSG_EFF_BASE, 340 MISCREG_LS_EFF_BASE, 341 MISCREG_MS_EFF_BASE, 342 MISCREG_TR_EFF_BASE, 343 MISCREG_IDTR_EFF_BASE, 344 345 // Hidden segment limit field 346 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 347 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 348 MISCREG_CS_LIMIT, 349 MISCREG_SS_LIMIT, 350 MISCREG_DS_LIMIT, 351 MISCREG_FS_LIMIT, 352 MISCREG_GS_LIMIT, 353 MISCREG_HS_LIMIT, 354 MISCREG_TSL_LIMIT, 355 MISCREG_TSG_LIMIT, 356 MISCREG_LS_LIMIT, 357 MISCREG_MS_LIMIT, 358 MISCREG_TR_LIMIT, 359 MISCREG_IDTR_LIMIT, 360 361 // Hidden segment limit attributes 362 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 363 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 364 MISCREG_CS_ATTR, 365 MISCREG_SS_ATTR, 366 MISCREG_DS_ATTR, 367 MISCREG_FS_ATTR, 368 MISCREG_GS_ATTR, 369 MISCREG_HS_ATTR, 370 MISCREG_TSL_ATTR, 371 MISCREG_TSG_ATTR, 372 MISCREG_LS_ATTR, 373 MISCREG_MS_ATTR, 374 MISCREG_TR_ATTR, 375 MISCREG_IDTR_ATTR, 376 377 // Floating point control registers 378 MISCREG_X87_TOP = 379 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 380 381 MISCREG_MXCSR, 382 MISCREG_FCW, 383 MISCREG_FSW, 384 MISCREG_FTW, 385 MISCREG_FTAG, 386 MISCREG_FISEG, 387 MISCREG_FIOFF, 388 MISCREG_FOSEG, 389 MISCREG_FOOFF, 390 MISCREG_FOP, 391 392 //XXX Add "Model-Specific Registers" 393 394 MISCREG_APIC_BASE, 395 396 // "Fake" MSRs for internally implemented devices 397 MISCREG_PCI_CONFIG_ADDRESS, 398 399 NUM_MISCREGS 400 }; 401 402 static inline bool 403 isValidMiscReg(int index) 404 { 405 return (index >= MISCREG_CR0 && index < NUM_MISCREGS && 406 index != MISCREG_CR1 && 407 !(index > MISCREG_CR4 && index < MISCREG_CR8) && 408 !(index > MISCREG_CR8 && index <= MISCREG_CR15)); 409 } 410 411 static inline MiscRegIndex 412 MISCREG_CR(int index) 413 { 414 assert(index >= 0 && index < NumCRegs); 415 return (MiscRegIndex)(MISCREG_CR_BASE + index); 416 } 417 418 static inline MiscRegIndex 419 MISCREG_DR(int index) 420 { 421 assert(index >= 0 && index < NumDRegs); 422 return (MiscRegIndex)(MISCREG_DR_BASE + index); 423 } 424 425 static inline MiscRegIndex 426 MISCREG_MTRR_PHYS_BASE(int index) 427 { 428 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 429 MISCREG_MTRR_PHYS_BASE_BASE)); 430 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 431 } 432 433 static inline MiscRegIndex 434 MISCREG_MTRR_PHYS_MASK(int index) 435 { 436 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 437 MISCREG_MTRR_PHYS_MASK_BASE)); 438 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 439 } 440 441 static inline MiscRegIndex 442 MISCREG_MC_CTL(int index) 443 { 444 assert(index >= 0 && index < (MISCREG_MC_CTL_END - 445 MISCREG_MC_CTL_BASE)); 446 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 447 } 448 449 static inline MiscRegIndex 450 MISCREG_MC_STATUS(int index) 451 { 452 assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 453 MISCREG_MC_STATUS_BASE)); 454 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 455 } 456 457 static inline MiscRegIndex 458 MISCREG_MC_ADDR(int index) 459 { 460 assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 461 MISCREG_MC_ADDR_BASE)); 462 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 463 } 464 465 static inline MiscRegIndex 466 MISCREG_MC_MISC(int index) 467 { 468 assert(index >= 0 && index < (MISCREG_MC_MISC_END - 469 MISCREG_MC_MISC_BASE)); 470 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 471 } 472 473 static inline MiscRegIndex 474 MISCREG_PERF_EVT_SEL(int index) 475 { 476 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 477 MISCREG_PERF_EVT_SEL_BASE)); 478 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 479 } 480 481 static inline MiscRegIndex 482 MISCREG_PERF_EVT_CTR(int index) 483 { 484 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 485 MISCREG_PERF_EVT_CTR_BASE)); 486 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 487 } 488 489 static inline MiscRegIndex 490 MISCREG_IORR_BASE(int index) 491 { 492 assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 493 MISCREG_IORR_BASE_BASE)); 494 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 495 } 496 497 static inline MiscRegIndex 498 MISCREG_IORR_MASK(int index) 499 { 500 assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 501 MISCREG_IORR_MASK_BASE)); 502 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 503 } 504 505 static inline MiscRegIndex 506 MISCREG_SEG_SEL(int index) 507 { 508 assert(index >= 0 && index < NUM_SEGMENTREGS); 509 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 510 } 511 512 static inline MiscRegIndex 513 MISCREG_SEG_BASE(int index) 514 { 515 assert(index >= 0 && index < NUM_SEGMENTREGS); 516 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 517 } 518 519 static inline MiscRegIndex 520 MISCREG_SEG_EFF_BASE(int index) 521 { 522 assert(index >= 0 && index < NUM_SEGMENTREGS); 523 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 524 } 525 526 static inline MiscRegIndex 527 MISCREG_SEG_LIMIT(int index) 528 { 529 assert(index >= 0 && index < NUM_SEGMENTREGS); 530 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 531 } 532 533 static inline MiscRegIndex 534 MISCREG_SEG_ATTR(int index) 535 { 536 assert(index >= 0 && index < NUM_SEGMENTREGS); 537 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 538 } 539 540 /** 541 * A type to describe the condition code bits of the RFLAGS register, 542 * plus two flags, EZF and ECF, which are only visible to microcode. 543 */ 544 BitUnion64(CCFlagBits) 545 Bitfield<11> of; 546 Bitfield<7> sf; 547 Bitfield<6> zf; 548 Bitfield<5> ezf; 549 Bitfield<4> af; 550 Bitfield<3> ecf; 551 Bitfield<2> pf; 552 Bitfield<0> cf; 553 EndBitUnion(CCFlagBits) 554 555 /** 556 * RFLAGS 557 */ 558 BitUnion64(RFLAGS) 559 Bitfield<21> id; // ID Flag 560 Bitfield<20> vip; // Virtual Interrupt Pending 561 Bitfield<19> vif; // Virtual Interrupt Flag 562 Bitfield<18> ac; // Alignment Check 563 Bitfield<17> vm; // Virtual-8086 Mode 564 Bitfield<16> rf; // Resume Flag 565 Bitfield<14> nt; // Nested Task 566 Bitfield<13, 12> iopl; // I/O Privilege Level 567 Bitfield<11> of; // Overflow Flag 568 Bitfield<10> df; // Direction Flag 569 Bitfield<9> intf; // Interrupt Flag 570 Bitfield<8> tf; // Trap Flag 571 Bitfield<7> sf; // Sign Flag 572 Bitfield<6> zf; // Zero Flag 573 Bitfield<4> af; // Auxiliary Flag 574 Bitfield<2> pf; // Parity Flag 575 Bitfield<0> cf; // Carry Flag 576 EndBitUnion(RFLAGS) 577 578 BitUnion64(HandyM5Reg) 579 Bitfield<0> mode; 580 Bitfield<3, 1> submode; 581 Bitfield<5, 4> cpl; 582 Bitfield<6> paging; 583 Bitfield<7> prot; 584 Bitfield<9, 8> defOp; 585 Bitfield<11, 10> altOp; 586 Bitfield<13, 12> defAddr; 587 Bitfield<15, 14> altAddr; 588 Bitfield<17, 16> stack; 589 EndBitUnion(HandyM5Reg) 590 591 /** 592 * Control registers 593 */ 594 BitUnion64(CR0) 595 Bitfield<31> pg; // Paging 596 Bitfield<30> cd; // Cache Disable 597 Bitfield<29> nw; // Not Writethrough 598 Bitfield<18> am; // Alignment Mask 599 Bitfield<16> wp; // Write Protect 600 Bitfield<5> ne; // Numeric Error 601 Bitfield<4> et; // Extension Type 602 Bitfield<3> ts; // Task Switched 603 Bitfield<2> em; // Emulation 604 Bitfield<1> mp; // Monitor Coprocessor 605 Bitfield<0> pe; // Protection Enabled 606 EndBitUnion(CR0) 607 608 // Page Fault Virtual Address 609 BitUnion64(CR2) 610 Bitfield<31, 0> legacy; 611 EndBitUnion(CR2) 612 613 BitUnion64(CR3) 614 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 615 // Base Address 616 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 617 // Base Address 618 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 619 // Base Address 620 Bitfield<4> pcd; // Page-Level Cache Disable 621 Bitfield<3> pwt; // Page-Level Writethrough 622 EndBitUnion(CR3) 623 624 BitUnion64(CR4) 625 Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States 626 Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE, 627 // WRGSBASE instructions 628 Bitfield<10> osxmmexcpt; // Operating System Unmasked 629 // Exception Support 630 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 631 Bitfield<8> pce; // Performance-Monitoring Counter Enable 632 Bitfield<7> pge; // Page-Global Enable 633 Bitfield<6> mce; // Machine Check Enable 634 Bitfield<5> pae; // Physical-Address Extension 635 Bitfield<4> pse; // Page Size Extensions 636 Bitfield<3> de; // Debugging Extensions 637 Bitfield<2> tsd; // Time Stamp Disable 638 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 639 Bitfield<0> vme; // Virtual-8086 Mode Extensions 640 EndBitUnion(CR4) 641 642 BitUnion64(CR8) 643 Bitfield<3, 0> tpr; // Task Priority Register 644 EndBitUnion(CR8) 645 646 BitUnion64(DR6) 647 Bitfield<0> b0; 648 Bitfield<1> b1; 649 Bitfield<2> b2; 650 Bitfield<3> b3; 651 Bitfield<13> bd; 652 Bitfield<14> bs; 653 Bitfield<15> bt; 654 EndBitUnion(DR6) 655 656 BitUnion64(DR7) 657 Bitfield<0> l0; 658 Bitfield<1> g0; 659 Bitfield<2> l1; 660 Bitfield<3> g1; 661 Bitfield<4> l2; 662 Bitfield<5> g2; 663 Bitfield<6> l3; 664 Bitfield<7> g3; 665 Bitfield<8> le; 666 Bitfield<9> ge; 667 Bitfield<13> gd; 668 Bitfield<17, 16> rw0; 669 Bitfield<19, 18> len0; 670 Bitfield<21, 20> rw1; 671 Bitfield<23, 22> len1; 672 Bitfield<25, 24> rw2; 673 Bitfield<27, 26> len2; 674 Bitfield<29, 28> rw3; 675 Bitfield<31, 30> len3; 676 EndBitUnion(DR7) 677 678 // MTRR capabilities 679 BitUnion64(MTRRcap) 680 Bitfield<7, 0> vcnt; // Variable-Range Register Count 681 Bitfield<8> fix; // Fixed-Range Registers 682 Bitfield<10> wc; // Write-Combining 683 EndBitUnion(MTRRcap) 684 685 /** 686 * SYSENTER configuration registers 687 */ 688 BitUnion64(SysenterCS) 689 Bitfield<15, 0> targetCS; 690 EndBitUnion(SysenterCS) 691 692 BitUnion64(SysenterESP) 693 Bitfield<31, 0> targetESP; 694 EndBitUnion(SysenterESP) 695 696 BitUnion64(SysenterEIP) 697 Bitfield<31, 0> targetEIP; 698 EndBitUnion(SysenterEIP) 699 700 /** 701 * Global machine check registers 702 */ 703 BitUnion64(McgCap) 704 Bitfield<7, 0> count; // Number of error reporting register banks 705 Bitfield<8> MCGCP; // MCG_CTL register present. 706 EndBitUnion(McgCap) 707 708 BitUnion64(McgStatus) 709 Bitfield<0> ripv; // Restart-IP valid 710 Bitfield<1> eipv; // Error-IP valid 711 Bitfield<2> mcip; // Machine check in-progress 712 EndBitUnion(McgStatus) 713 714 BitUnion64(DebugCtlMsr) 715 Bitfield<0> lbr; // Last-branch record 716 Bitfield<1> btf; // Branch single step 717 Bitfield<2> pb0; // Performance monitoring pin control 0 718 Bitfield<3> pb1; // Performance monitoring pin control 1 719 Bitfield<4> pb2; // Performance monitoring pin control 2 720 Bitfield<5> pb3; // Performance monitoring pin control 3 721 /*uint64_t pb(int index) 722 { 723 return bits(__data, index + 2); 724 }*/ 725 EndBitUnion(DebugCtlMsr) 726 727 BitUnion64(MtrrPhysBase) 728 Bitfield<7, 0> type; // Default memory type 729 Bitfield<51, 12> physbase; // Range physical base address 730 EndBitUnion(MtrrPhysBase) 731 732 BitUnion64(MtrrPhysMask) 733 Bitfield<11> valid; // MTRR pair enable 734 Bitfield<51, 12> physmask; // Range physical mask 735 EndBitUnion(MtrrPhysMask) 736 737 BitUnion64(MtrrFixed) 738 /*uint64_t type(int index) 739 { 740 return bits(__data, index * 8 + 7, index * 8); 741 }*/ 742 EndBitUnion(MtrrFixed) 743 744 BitUnion64(Pat) 745 /*uint64_t pa(int index) 746 { 747 return bits(__data, index * 8 + 2, index * 8); 748 }*/ 749 EndBitUnion(Pat) 750 751 BitUnion64(MtrrDefType) 752 Bitfield<7, 0> type; // Default type 753 Bitfield<10> fe; // Fixed range enable 754 Bitfield<11> e; // MTRR enable 755 EndBitUnion(MtrrDefType) 756 757 /** 758 * Machine check 759 */ 760 BitUnion64(McStatus) 761 Bitfield<15,0> mcaErrorCode; 762 Bitfield<31,16> modelSpecificCode; 763 Bitfield<56,32> otherInfo; 764 Bitfield<57> pcc; // Processor-context corrupt 765 Bitfield<58> addrv; // Error-address register valid 766 Bitfield<59> miscv; // Miscellaneous-error register valid 767 Bitfield<60> en; // Error condition enabled 768 Bitfield<61> uc; // Uncorrected error 769 Bitfield<62> over; // Status register overflow 770 Bitfield<63> val; // Valid 771 EndBitUnion(McStatus) 772 773 BitUnion64(McCtl) 774 /*uint64_t en(int index) 775 { 776 return bits(__data, index); 777 }*/ 778 EndBitUnion(McCtl) 779 780 // Extended feature enable register 781 BitUnion64(Efer) 782 Bitfield<0> sce; // System call extensions 783 Bitfield<8> lme; // Long mode enable 784 Bitfield<10> lma; // Long mode active 785 Bitfield<11> nxe; // No-execute enable 786 Bitfield<12> svme; // Secure virtual machine enable 787 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 788 EndBitUnion(Efer) 789 790 BitUnion64(Star) 791 Bitfield<31,0> targetEip; 792 Bitfield<47,32> syscallCsAndSs; 793 Bitfield<63,48> sysretCsAndSs; 794 EndBitUnion(Star) 795 796 BitUnion64(SfMask) 797 Bitfield<31,0> mask; 798 EndBitUnion(SfMask) 799 800 BitUnion64(PerfEvtSel) 801 Bitfield<7,0> eventMask; 802 Bitfield<15,8> unitMask; 803 Bitfield<16> usr; // User mode 804 Bitfield<17> os; // Operating-system mode 805 Bitfield<18> e; // Edge detect 806 Bitfield<19> pc; // Pin control 807 Bitfield<20> intEn; // Interrupt enable 808 Bitfield<22> en; // Counter enable 809 Bitfield<23> inv; // Invert mask 810 Bitfield<31,24> counterMask; 811 EndBitUnion(PerfEvtSel) 812 813 BitUnion32(Syscfg) 814 Bitfield<18> mfde; // MtrrFixDramEn 815 Bitfield<19> mfdm; // MtrrFixDramModEn 816 Bitfield<20> mvdm; // MtrrVarDramEn 817 Bitfield<21> tom2; // MtrrTom2En 818 EndBitUnion(Syscfg) 819 820 BitUnion64(IorrBase) 821 Bitfield<3> wr; // WrMem Enable 822 Bitfield<4> rd; // RdMem Enable 823 Bitfield<51,12> physbase; // Range physical base address 824 EndBitUnion(IorrBase) 825 826 BitUnion64(IorrMask) 827 Bitfield<11> v; // I/O register pair enable (valid) 828 Bitfield<51,12> physmask; // Range physical mask 829 EndBitUnion(IorrMask) 830 831 BitUnion64(Tom) 832 Bitfield<51,23> physAddr; // Top of memory physical address 833 EndBitUnion(Tom) 834 835 BitUnion64(VmCrMsr) 836 Bitfield<0> dpd; 837 Bitfield<1> rInit; 838 Bitfield<2> disA20M; 839 EndBitUnion(VmCrMsr) 840 841 BitUnion64(IgnneMsr) 842 Bitfield<0> ignne; 843 EndBitUnion(IgnneMsr) 844 845 BitUnion64(SmmCtlMsr) 846 Bitfield<0> dismiss; 847 Bitfield<1> enter; 848 Bitfield<2> smiCycle; 849 Bitfield<3> exit; 850 Bitfield<4> rsmCycle; 851 EndBitUnion(SmmCtlMsr) 852 853 /** 854 * Segment Selector 855 */ 856 BitUnion64(SegSelector) 857 // The following bitfield is not defined in the ISA, but it's useful 858 // when checking selectors in larger data types to make sure they 859 // aren't too large. 860 Bitfield<63, 3> esi; // Extended selector 861 Bitfield<15, 3> si; // Selector Index 862 Bitfield<2> ti; // Table Indicator 863 Bitfield<1, 0> rpl; // Requestor Privilege Level 864 EndBitUnion(SegSelector) 865 866 /** 867 * Segment Descriptors 868 */ 869 870 BitUnion64(SegDescriptor) 871 Bitfield<63, 56> baseHigh; 872 Bitfield<39, 16> baseLow; 873 Bitfield<55> g; // Granularity 874 Bitfield<54> d; // Default Operand Size 875 Bitfield<54> b; // Default Operand Size 876 Bitfield<53> l; // Long Attribute Bit 877 Bitfield<52> avl; // Available To Software 878 Bitfield<51, 48> limitHigh; 879 Bitfield<15, 0> limitLow; 880 Bitfield<47> p; // Present 881 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 882 Bitfield<44> s; // System 883 SubBitUnion(type, 43, 40) 884 // Specifies whether this descriptor is for code or data. 885 Bitfield<43> codeOrData; 886 887 // These bit fields are for code segments 888 Bitfield<42> c; // Conforming 889 Bitfield<41> r; // Readable 890 891 // These bit fields are for data segments 892 Bitfield<42> e; // Expand-Down 893 Bitfield<41> w; // Writable 894 895 // This is used for both code and data segments. 896 Bitfield<40> a; // Accessed 897 EndSubBitUnion(type) 898 EndBitUnion(SegDescriptor) 899 900 /** 901 * TSS Descriptor (long mode - 128 bits) 902 * the lower 64 bits 903 */ 904 BitUnion64(TSSlow) 905 Bitfield<63, 56> baseHigh; 906 Bitfield<39, 16> baseLow; 907 Bitfield<55> g; // Granularity 908 Bitfield<52> avl; // Available To Software 909 Bitfield<51, 48> limitHigh; 910 Bitfield<15, 0> limitLow; 911 Bitfield<47> p; // Present 912 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 913 SubBitUnion(type, 43, 40) 914 // Specifies whether this descriptor is for code or data. 915 Bitfield<43> codeOrData; 916 917 // These bit fields are for code segments 918 Bitfield<42> c; // Conforming 919 Bitfield<41> r; // Readable 920 921 // These bit fields are for data segments 922 Bitfield<42> e; // Expand-Down 923 Bitfield<41> w; // Writable 924 925 // This is used for both code and data segments. 926 Bitfield<40> a; // Accessed 927 EndSubBitUnion(type) 928 EndBitUnion(TSSlow) 929 930 /** 931 * TSS Descriptor (long mode - 128 bits) 932 * the upper 64 bits 933 */ 934 BitUnion64(TSShigh) 935 Bitfield<31, 0> base; 936 EndBitUnion(TSShigh) 937 938 BitUnion64(SegAttr) 939 Bitfield<1, 0> dpl; 940 Bitfield<2> unusable; 941 Bitfield<3> defaultSize; 942 Bitfield<4> longMode; 943 Bitfield<5> avl; 944 Bitfield<6> granularity; 945 Bitfield<7> present; 946 Bitfield<11, 8> type; 947 Bitfield<12> writable; 948 Bitfield<13> readable; 949 Bitfield<14> expandDown; 950 Bitfield<15> system; 951 EndBitUnion(SegAttr) 952 953 BitUnion64(GateDescriptor) 954 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 955 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 956 Bitfield<31, 16> selector; // Target Code-Segment Selector 957 Bitfield<47> p; // Present 958 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 959 Bitfield<43, 40> type; 960 Bitfield<36, 32> count; // Parameter Count 961 EndBitUnion(GateDescriptor) 962 963 /** 964 * Long Mode Gate Descriptor 965 */ 966 BitUnion64(GateDescriptorLow) 967 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 968 Bitfield<47> p; // Present 969 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 970 Bitfield<43, 40> type; 971 Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling 972 Bitfield<31, 16> selector; // Target Code-Segment Selector 973 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 974 EndBitUnion(GateDescriptorLow) 975 976 BitUnion64(GateDescriptorHigh) 977 Bitfield<31, 0> offset; // Target Code-Segment Offset 978 EndBitUnion(GateDescriptorHigh) 979 980 /** 981 * Descriptor-Table Registers 982 */ 983 BitUnion64(GDTR) 984 EndBitUnion(GDTR) 985 986 BitUnion64(IDTR) 987 EndBitUnion(IDTR) 988 989 BitUnion64(LDTR) 990 EndBitUnion(LDTR) 991 992 /** 993 * Task Register 994 */ 995 BitUnion64(TR) 996 EndBitUnion(TR) 997 998 999 /** 1000 * Local APIC Base Register 1001 */ 1002 BitUnion64(LocalApicBase) 1003 Bitfield<51, 12> base; 1004 Bitfield<11> enable; 1005 Bitfield<8> bsp; 1006 EndBitUnion(LocalApicBase) 1007} 1008 1009#endif // __ARCH_X86_INTREGS_HH__ 1010