interrupts.cc revision 9805
12135SN/A/* 22135SN/A * Copyright (c) 2012-2013 ARM Limited 35268Sksewell@umich.edu * All rights reserved 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65268Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75268Sksewell@umich.edu * property including but not limited to intellectual property relating 85268Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95268Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105268Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115268Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125268Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135268Sksewell@umich.edu * 145268Sksewell@umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 155268Sksewell@umich.edu * All rights reserved. 165268Sksewell@umich.edu * 175268Sksewell@umich.edu * The license below extends only to copyright in the software and shall 185268Sksewell@umich.edu * not be construed as granting a license to any other intellectual 195268Sksewell@umich.edu * property including but not limited to intellectual property relating 205268Sksewell@umich.edu * to a hardware implementation of the functionality of the software 215268Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 225268Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 235268Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 245268Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 255268Sksewell@umich.edu * 265268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 275268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 285268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 295268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 302706Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 312038SN/A * notice, this list of conditions and the following disclaimer in the 322038SN/A * documentation and/or other materials provided with the distribution; 332038SN/A * neither the name of the copyright holders nor the names of its 342038SN/A * contributors may be used to endorse or promote products derived from 352038SN/A * this software without specific prior written permission. 362038SN/A * 372038SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 382135SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 392038SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 402038SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 412038SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 422038SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 432038SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 442038SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 452038SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 462038SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 472038SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 482038SN/A * 492686Sksewell@umich.edu * Authors: Gabe Black 502686Sksewell@umich.edu */ 512686Sksewell@umich.edu 522686Sksewell@umich.edu#include "arch/x86/regs/apic.hh" 532686Sksewell@umich.edu#include "arch/x86/interrupts.hh" 542686Sksewell@umich.edu#include "arch/x86/intmessage.hh" 552686Sksewell@umich.edu#include "cpu/base.hh" 562686Sksewell@umich.edu#include "debug/LocalApic.hh" 572686Sksewell@umich.edu#include "dev/x86/i82094aa.hh" 582686Sksewell@umich.edu#include "dev/x86/pc.hh" 592686Sksewell@umich.edu#include "dev/x86/south_bridge.hh" 602686Sksewell@umich.edu#include "mem/packet_access.hh" 612686Sksewell@umich.edu#include "sim/system.hh" 622686Sksewell@umich.edu#include "sim/full_system.hh" 632038SN/A 642038SN/Aint 652038SN/AdivideFromConf(uint32_t conf) 662038SN/A{ 672686Sksewell@umich.edu // This figures out what division we want from the division configuration 682038SN/A // register in the local APIC. The encoding is a little odd but it can 692686Sksewell@umich.edu // be deciphered fairly easily. 702686Sksewell@umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 712686Sksewell@umich.edu shift = (shift + 1) % 8; 722686Sksewell@umich.edu return 1 << shift; 732686Sksewell@umich.edu} 742686Sksewell@umich.edu 752686Sksewell@umich.edunamespace X86ISA 762686Sksewell@umich.edu{ 772686Sksewell@umich.edu 782686Sksewell@umich.eduApicRegIndex 792686Sksewell@umich.edudecodeAddr(Addr paddr) 802686Sksewell@umich.edu{ 812686Sksewell@umich.edu ApicRegIndex regNum; 822686Sksewell@umich.edu paddr &= ~mask(3); 832686Sksewell@umich.edu switch (paddr) 842686Sksewell@umich.edu { 852686Sksewell@umich.edu case 0x20: 862038SN/A regNum = APIC_ID; 872038SN/A break; 882038SN/A case 0x30: 899554Sandreas.hansson@arm.com regNum = APIC_VERSION; 909554Sandreas.hansson@arm.com break; 919554Sandreas.hansson@arm.com case 0x80: 929554Sandreas.hansson@arm.com regNum = APIC_TASK_PRIORITY; 939554Sandreas.hansson@arm.com break; 942686Sksewell@umich.edu case 0x90: 954661Sksewell@umich.edu regNum = APIC_ARBITRATION_PRIORITY; 964661Sksewell@umich.edu break; 974661Sksewell@umich.edu case 0xA0: 984661Sksewell@umich.edu regNum = APIC_PROCESSOR_PRIORITY; 995222Sksewell@umich.edu break; 1005222Sksewell@umich.edu case 0xB0: 1015222Sksewell@umich.edu regNum = APIC_EOI; 1025222Sksewell@umich.edu break; 1034661Sksewell@umich.edu case 0xD0: 1042038SN/A regNum = APIC_LOGICAL_DESTINATION; 1052686Sksewell@umich.edu break; 1062686Sksewell@umich.edu case 0xE0: 1072686Sksewell@umich.edu regNum = APIC_DESTINATION_FORMAT; 1082686Sksewell@umich.edu break; 1092686Sksewell@umich.edu case 0xF0: 1102686Sksewell@umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1112686Sksewell@umich.edu break; 1126314Sgblack@eecs.umich.edu case 0x100: 1132686Sksewell@umich.edu case 0x108: 1142686Sksewell@umich.edu case 0x110: 1156314Sgblack@eecs.umich.edu case 0x118: 1162686Sksewell@umich.edu case 0x120: 1176314Sgblack@eecs.umich.edu case 0x128: 1186314Sgblack@eecs.umich.edu case 0x130: 1196314Sgblack@eecs.umich.edu case 0x138: 1202686Sksewell@umich.edu case 0x140: 1212686Sksewell@umich.edu case 0x148: 1222686Sksewell@umich.edu case 0x150: 1232686Sksewell@umich.edu case 0x158: 1242686Sksewell@umich.edu case 0x160: 1252686Sksewell@umich.edu case 0x168: 1262686Sksewell@umich.edu case 0x170: 1272686Sksewell@umich.edu case 0x178: 1282686Sksewell@umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1292687Sksewell@umich.edu break; 1302686Sksewell@umich.edu case 0x180: 1312686Sksewell@umich.edu case 0x188: 1322686Sksewell@umich.edu case 0x190: 1332686Sksewell@umich.edu case 0x198: 1346314Sgblack@eecs.umich.edu case 0x1A0: 1352686Sksewell@umich.edu case 0x1A8: 1366314Sgblack@eecs.umich.edu case 0x1B0: 1376314Sgblack@eecs.umich.edu case 0x1B8: 1382686Sksewell@umich.edu case 0x1C0: 1392686Sksewell@umich.edu case 0x1C8: 1406314Sgblack@eecs.umich.edu case 0x1D0: 1412686Sksewell@umich.edu case 0x1D8: 1422686Sksewell@umich.edu case 0x1E0: 1436383Sgblack@eecs.umich.edu case 0x1E8: 1446383Sgblack@eecs.umich.edu case 0x1F0: 1452686Sksewell@umich.edu case 0x1F8: 1464675Sksewell@umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1474675Sksewell@umich.edu break; 1482686Sksewell@umich.edu case 0x200: 1496383Sgblack@eecs.umich.edu case 0x208: 1502686Sksewell@umich.edu case 0x210: 1512686Sksewell@umich.edu case 0x218: 1522686Sksewell@umich.edu case 0x220: 1532686Sksewell@umich.edu case 0x228: 1542686Sksewell@umich.edu case 0x230: 1552686Sksewell@umich.edu case 0x238: 1562686Sksewell@umich.edu case 0x240: 1572686Sksewell@umich.edu case 0x248: 1582686Sksewell@umich.edu case 0x250: 1592687Sksewell@umich.edu case 0x258: 1602686Sksewell@umich.edu case 0x260: 1612686Sksewell@umich.edu case 0x268: 1626383Sgblack@eecs.umich.edu case 0x270: 1632686Sksewell@umich.edu case 0x278: 1644661Sksewell@umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1652686Sksewell@umich.edu break; 1662686Sksewell@umich.edu case 0x280: 1672686Sksewell@umich.edu regNum = APIC_ERROR_STATUS; 1686383Sgblack@eecs.umich.edu break; 1692686Sksewell@umich.edu case 0x300: 1702686Sksewell@umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1712686Sksewell@umich.edu break; 1722686Sksewell@umich.edu case 0x310: 1732686Sksewell@umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1742686Sksewell@umich.edu break; 1752686Sksewell@umich.edu case 0x320: 1762686Sksewell@umich.edu regNum = APIC_LVT_TIMER; 1772686Sksewell@umich.edu break; 1782686Sksewell@umich.edu case 0x330: 1795222Sksewell@umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1802686Sksewell@umich.edu break; 1812686Sksewell@umich.edu case 0x340: 1828738Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1838564Sgblack@eecs.umich.edu break; 1842686Sksewell@umich.edu case 0x350: 1852686Sksewell@umich.edu regNum = APIC_LVT_LINT0; 1862686Sksewell@umich.edu break; 1872686Sksewell@umich.edu case 0x360: 1882686Sksewell@umich.edu regNum = APIC_LVT_LINT1; 1892686Sksewell@umich.edu break; 1902686Sksewell@umich.edu case 0x370: 1912686Sksewell@umich.edu regNum = APIC_LVT_ERROR; 1922686Sksewell@umich.edu break; 1932686Sksewell@umich.edu case 0x380: 1942686Sksewell@umich.edu regNum = APIC_INITIAL_COUNT; 1952686Sksewell@umich.edu break; 1962686Sksewell@umich.edu case 0x390: 1972686Sksewell@umich.edu regNum = APIC_CURRENT_COUNT; 1988564Sgblack@eecs.umich.edu break; 1998738Sgblack@eecs.umich.edu case 0x3E0: 2008564Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2018564Sgblack@eecs.umich.edu break; 2028564Sgblack@eecs.umich.edu default: 2038564Sgblack@eecs.umich.edu // A reserved register field. 2042686Sksewell@umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2052686Sksewell@umich.edu break; 2062686Sksewell@umich.edu } 2072686Sksewell@umich.edu return regNum; 2082686Sksewell@umich.edu} 2092686Sksewell@umich.edu} 2102686Sksewell@umich.edu 2112686Sksewell@umich.eduTick 2122686Sksewell@umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2132135SN/A{ 2143951Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2152038SN/A //Make sure we're at least only accessing one register. 2162038SN/A if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2172135SN/A panic("Accessed more than one register at a time in the APIC!\n"); 2182686Sksewell@umich.edu ApicRegIndex reg = decodeAddr(offset); 2192084SN/A uint32_t val = htog(readReg(reg)); 2202084SN/A DPRINTF(LocalApic, 2212686Sksewell@umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2222686Sksewell@umich.edu reg, offset, val); 2232607SN/A pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2242686Sksewell@umich.edu pkt->makeAtomicResponse(); 2258588Sgblack@eecs.umich.edu return pioDelay; 2262686Sksewell@umich.edu} 2278588Sgblack@eecs.umich.edu 2282686Sksewell@umich.eduTick 2292686Sksewell@umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2302686Sksewell@umich.edu{ 2318588Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2328588Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2332686Sksewell@umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2348588Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2352686Sksewell@umich.edu ApicRegIndex reg = decodeAddr(offset); 2362686Sksewell@umich.edu uint32_t val = regs[reg]; 2372686Sksewell@umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2388588Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2392686Sksewell@umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2402686Sksewell@umich.edu reg, offset, gtoh(val)); 2412686Sksewell@umich.edu setReg(reg, gtoh(val)); 2422686Sksewell@umich.edu pkt->makeAtomicResponse(); 2432686Sksewell@umich.edu return pioDelay; 2442686Sksewell@umich.edu} 2452686Sksewell@umich.eduvoid 2462686Sksewell@umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2472686Sksewell@umich.edu uint8_t deliveryMode, bool level) 2482686Sksewell@umich.edu{ 2492686Sksewell@umich.edu /* 2502686Sksewell@umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2512686Sksewell@umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2522686Sksewell@umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2533951Sgblack@eecs.umich.edu */ 2542686Sksewell@umich.edu if (deliveryMode == DeliveryMode::Fixed || 2552686Sksewell@umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2562686Sksewell@umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2572686Sksewell@umich.edu DeliveryMode::names[deliveryMode]); 2582607SN/A // Queue up the interrupt in the IRR. 2592607SN/A if (vector > IRRV) 2602607SN/A IRRV = vector; 2612686Sksewell@umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2622686Sksewell@umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2632686Sksewell@umich.edu if (level) { 2642686Sksewell@umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2658588Sgblack@eecs.umich.edu } else { 2662686Sksewell@umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2672686Sksewell@umich.edu } 2688588Sgblack@eecs.umich.edu } 2692686Sksewell@umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2702686Sksewell@umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2718588Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2722686Sksewell@umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2732686Sksewell@umich.edu pendingUnmaskableInt = pendingSmi = true; 2748588Sgblack@eecs.umich.edu smiVector = vector; 2752686Sksewell@umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2762686Sksewell@umich.edu pendingUnmaskableInt = pendingNmi = true; 2772686Sksewell@umich.edu nmiVector = vector; 2782686Sksewell@umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2792686Sksewell@umich.edu pendingExtInt = true; 2802686Sksewell@umich.edu extIntVector = vector; 2812686Sksewell@umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2828588Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2832686Sksewell@umich.edu initVector = vector; 2848588Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2852686Sksewell@umich.edu !pendingStartup && !startedUp) { 2868588Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2872686Sksewell@umich.edu startupVector = vector; 2888588Sgblack@eecs.umich.edu } 2892686Sksewell@umich.edu } 2902686Sksewell@umich.edu if (FullSystem) 2912686Sksewell@umich.edu cpu->wakeup(); 2922686Sksewell@umich.edu} 2932686Sksewell@umich.edu 2942686Sksewell@umich.edu 2952686Sksewell@umich.eduvoid 2962686Sksewell@umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2972686Sksewell@umich.edu{ 2982686Sksewell@umich.edu assert(newCPU); 2992686Sksewell@umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 3002686Sksewell@umich.edu panic("Local APICs can't be moved between CPUs" 3012686Sksewell@umich.edu " with different IDs.\n"); 3022686Sksewell@umich.edu } 3032686Sksewell@umich.edu cpu = newCPU; 3043951Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 3052686Sksewell@umich.edu regs[APIC_ID] = (initialApicId << 24); 3062686Sksewell@umich.edu pioAddr = x86LocalAPICAddress(initialApicId, 0); 3072686Sksewell@umich.edu} 3082686Sksewell@umich.edu 3092686Sksewell@umich.edu 3102686Sksewell@umich.eduvoid 3112686Sksewell@umich.eduX86ISA::Interrupts::init() 3123951Sgblack@eecs.umich.edu{ 3132607SN/A // 3142607SN/A // The local apic must register its address ranges on both its pio port 3152607SN/A // via the basicpiodevice(piodevice) init() function and its int port 3162607SN/A // that it inherited from IntDev. Note IntDev is not a SimObject itself. 3172607SN/A // 3182607SN/A BasicPioDevice::init(); 3192573SN/A IntDev::init(); 3202135SN/A 3213951Sgblack@eecs.umich.edu // the slave port has a range so inform the connected master 3222084SN/A intSlavePort.sendRangeChange(); 3232084SN/A} 3242135SN/A 3252135SN/A 3262038SN/ATick 3272607SN/AX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3282686Sksewell@umich.edu{ 3292686Sksewell@umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3302686Sksewell@umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3312686Sksewell@umich.edu switch(offset) 3322686Sksewell@umich.edu { 3332686Sksewell@umich.edu case 0: 3342686Sksewell@umich.edu { 3352686Sksewell@umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3368588Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3372686Sksewell@umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3382686Sksewell@umich.edu message.vector); 3392686Sksewell@umich.edu 3408588Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3412686Sksewell@umich.edu message.deliveryMode, message.trigger); 3422686Sksewell@umich.edu } 3432686Sksewell@umich.edu break; 3442686Sksewell@umich.edu default: 3452686Sksewell@umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3468588Sgblack@eecs.umich.edu offset); 3472686Sksewell@umich.edu break; 3482686Sksewell@umich.edu } 3492686Sksewell@umich.edu pkt->makeAtomicResponse(); 3502686Sksewell@umich.edu return pioDelay; 3512686Sksewell@umich.edu} 3522686Sksewell@umich.edu 3532686Sksewell@umich.edu 3542686Sksewell@umich.eduTick 3552686Sksewell@umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3562686Sksewell@umich.edu{ 3572686Sksewell@umich.edu assert(!pkt->isError()); 3588588Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3592686Sksewell@umich.edu if (--pendingIPIs == 0) { 3602686Sksewell@umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3612686Sksewell@umich.edu // Record that the ICR is now idle. 3622686Sksewell@umich.edu low.deliveryStatus = 0; 3632686Sksewell@umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3642686Sksewell@umich.edu } 3652686Sksewell@umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3662686Sksewell@umich.edu return 0; 3672686Sksewell@umich.edu} 3682686Sksewell@umich.edu 3693951Sgblack@eecs.umich.edu 3702686Sksewell@umich.eduAddrRangeList 3712686Sksewell@umich.eduX86ISA::Interrupts::getIntAddrRange() const 3722686Sksewell@umich.edu{ 3732686Sksewell@umich.edu AddrRangeList ranges; 3742607SN/A ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3752608SN/A x86InterruptAddress(initialApicId, 0) + 376 PhysAddrAPICRangeSize)); 377 return ranges; 378} 379 380 381uint32_t 382X86ISA::Interrupts::readReg(ApicRegIndex reg) 383{ 384 if (reg >= APIC_TRIGGER_MODE(0) && 385 reg <= APIC_TRIGGER_MODE(15)) { 386 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 387 } 388 switch (reg) { 389 case APIC_ARBITRATION_PRIORITY: 390 panic("Local APIC Arbitration Priority register unimplemented.\n"); 391 break; 392 case APIC_PROCESSOR_PRIORITY: 393 panic("Local APIC Processor Priority register unimplemented.\n"); 394 break; 395 case APIC_ERROR_STATUS: 396 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 397 break; 398 case APIC_CURRENT_COUNT: 399 { 400 if (apicTimerEvent.scheduled()) { 401 // Compute how many m5 ticks happen per count. 402 uint64_t ticksPerCount = clockPeriod() * 403 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 404 // Compute how many m5 ticks are left. 405 uint64_t val = apicTimerEvent.when() - curTick(); 406 // Turn that into a count. 407 val = (val + ticksPerCount - 1) / ticksPerCount; 408 return val; 409 } else { 410 return 0; 411 } 412 } 413 default: 414 break; 415 } 416 return regs[reg]; 417} 418 419void 420X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 421{ 422 uint32_t newVal = val; 423 if (reg >= APIC_IN_SERVICE(0) && 424 reg <= APIC_IN_SERVICE(15)) { 425 panic("Local APIC In-Service registers are unimplemented.\n"); 426 } 427 if (reg >= APIC_TRIGGER_MODE(0) && 428 reg <= APIC_TRIGGER_MODE(15)) { 429 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 430 } 431 if (reg >= APIC_INTERRUPT_REQUEST(0) && 432 reg <= APIC_INTERRUPT_REQUEST(15)) { 433 panic("Local APIC Interrupt Request registers " 434 "are unimplemented.\n"); 435 } 436 switch (reg) { 437 case APIC_ID: 438 newVal = val & 0xFF; 439 break; 440 case APIC_VERSION: 441 // The Local APIC Version register is read only. 442 return; 443 case APIC_TASK_PRIORITY: 444 newVal = val & 0xFF; 445 break; 446 case APIC_ARBITRATION_PRIORITY: 447 panic("Local APIC Arbitration Priority register unimplemented.\n"); 448 break; 449 case APIC_PROCESSOR_PRIORITY: 450 panic("Local APIC Processor Priority register unimplemented.\n"); 451 break; 452 case APIC_EOI: 453 // Remove the interrupt that just completed from the local apic state. 454 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 455 updateISRV(); 456 return; 457 case APIC_LOGICAL_DESTINATION: 458 newVal = val & 0xFF000000; 459 break; 460 case APIC_DESTINATION_FORMAT: 461 newVal = val | 0x0FFFFFFF; 462 break; 463 case APIC_SPURIOUS_INTERRUPT_VECTOR: 464 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 465 regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 466 if (val & (1 << 9)) 467 warn("Focus processor checking not implemented.\n"); 468 break; 469 case APIC_ERROR_STATUS: 470 { 471 if (regs[APIC_INTERNAL_STATE] & 0x1) { 472 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 473 newVal = 0; 474 } else { 475 regs[APIC_INTERNAL_STATE] |= ULL(0x1); 476 return; 477 } 478 479 } 480 break; 481 case APIC_INTERRUPT_COMMAND_LOW: 482 { 483 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 484 // Check if we're already sending an IPI. 485 if (low.deliveryStatus) { 486 newVal = low; 487 break; 488 } 489 low = val; 490 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 491 // Record that an IPI is being sent. 492 low.deliveryStatus = 1; 493 TriggerIntMessage message = 0; 494 message.destination = high.destination; 495 message.vector = low.vector; 496 message.deliveryMode = low.deliveryMode; 497 message.destMode = low.destMode; 498 message.level = low.level; 499 message.trigger = low.trigger; 500 bool timing(sys->isTimingMode()); 501 // Be careful no updates of the delivery status bit get lost. 502 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 503 ApicList apics; 504 int numContexts = sys->numContexts(); 505 switch (low.destShorthand) { 506 case 0: 507 if (message.deliveryMode == DeliveryMode::LowestPriority) { 508 panic("Lowest priority delivery mode " 509 "IPIs aren't implemented.\n"); 510 } 511 if (message.destMode == 1) { 512 int dest = message.destination; 513 hack_once("Assuming logical destinations are 1 << id.\n"); 514 for (int i = 0; i < numContexts; i++) { 515 if (dest & 0x1) 516 apics.push_back(i); 517 dest = dest >> 1; 518 } 519 } else { 520 if (message.destination == 0xFF) { 521 for (int i = 0; i < numContexts; i++) { 522 if (i == initialApicId) { 523 requestInterrupt(message.vector, 524 message.deliveryMode, message.trigger); 525 } else { 526 apics.push_back(i); 527 } 528 } 529 } else { 530 if (message.destination == initialApicId) { 531 requestInterrupt(message.vector, 532 message.deliveryMode, message.trigger); 533 } else { 534 apics.push_back(message.destination); 535 } 536 } 537 } 538 break; 539 case 1: 540 newVal = val; 541 requestInterrupt(message.vector, 542 message.deliveryMode, message.trigger); 543 break; 544 case 2: 545 requestInterrupt(message.vector, 546 message.deliveryMode, message.trigger); 547 // Fall through 548 case 3: 549 { 550 for (int i = 0; i < numContexts; i++) { 551 if (i != initialApicId) { 552 apics.push_back(i); 553 } 554 } 555 } 556 break; 557 } 558 pendingIPIs += apics.size(); 559 intMasterPort.sendMessage(apics, message, timing); 560 newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 561 } 562 break; 563 case APIC_LVT_TIMER: 564 case APIC_LVT_THERMAL_SENSOR: 565 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 566 case APIC_LVT_LINT0: 567 case APIC_LVT_LINT1: 568 case APIC_LVT_ERROR: 569 { 570 uint64_t readOnlyMask = (1 << 12) | (1 << 14); 571 newVal = (val & ~readOnlyMask) | 572 (regs[reg] & readOnlyMask); 573 } 574 break; 575 case APIC_INITIAL_COUNT: 576 { 577 newVal = bits(val, 31, 0); 578 // Compute how many timer ticks we're being programmed for. 579 uint64_t newCount = newVal * 580 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 581 // Schedule on the edge of the next tick plus the new count. 582 Tick offset = curTick() % clockPeriod(); 583 if (offset) { 584 reschedule(apicTimerEvent, 585 curTick() + (newCount + 1) * 586 clockPeriod() - offset, true); 587 } else { 588 if (newCount) 589 reschedule(apicTimerEvent, 590 curTick() + newCount * 591 clockPeriod(), true); 592 } 593 } 594 break; 595 case APIC_CURRENT_COUNT: 596 //Local APIC Current Count register is read only. 597 return; 598 case APIC_DIVIDE_CONFIGURATION: 599 newVal = val & 0xB; 600 break; 601 default: 602 break; 603 } 604 regs[reg] = newVal; 605 return; 606} 607 608 609X86ISA::Interrupts::Interrupts(Params * p) : 610 BasicPioDevice(p), IntDev(this, p->int_latency), 611 apicTimerEvent(this), 612 pendingSmi(false), smiVector(0), 613 pendingNmi(false), nmiVector(0), 614 pendingExtInt(false), extIntVector(0), 615 pendingInit(false), initVector(0), 616 pendingStartup(false), startupVector(0), 617 startedUp(false), pendingUnmaskableInt(false), 618 pendingIPIs(0), cpu(NULL), 619 intSlavePort(name() + ".int_slave", this, this) 620{ 621 pioSize = PageBytes; 622 memset(regs, 0, sizeof(regs)); 623 //Set the local apic DFR to the flat model. 624 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 625 ISRV = 0; 626 IRRV = 0; 627} 628 629 630bool 631X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 632{ 633 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 634 if (pendingUnmaskableInt) { 635 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 636 return true; 637 } 638 if (rflags.intf) { 639 if (pendingExtInt) { 640 DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 641 return true; 642 } 643 if (IRRV > ISRV && bits(IRRV, 7, 4) > 644 bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 645 DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 646 return true; 647 } 648 } 649 return false; 650} 651 652Fault 653X86ISA::Interrupts::getInterrupt(ThreadContext *tc) 654{ 655 assert(checkInterrupts(tc)); 656 // These are all probably fairly uncommon, so we'll make them easier to 657 // check for. 658 if (pendingUnmaskableInt) { 659 if (pendingSmi) { 660 DPRINTF(LocalApic, "Generated SMI fault object.\n"); 661 return new SystemManagementInterrupt(); 662 } else if (pendingNmi) { 663 DPRINTF(LocalApic, "Generated NMI fault object.\n"); 664 return new NonMaskableInterrupt(nmiVector); 665 } else if (pendingInit) { 666 DPRINTF(LocalApic, "Generated INIT fault object.\n"); 667 return new InitInterrupt(initVector); 668 } else if (pendingStartup) { 669 DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 670 return new StartupInterrupt(startupVector); 671 } else { 672 panic("pendingUnmaskableInt set, but no unmaskable " 673 "ints were pending.\n"); 674 return NoFault; 675 } 676 } else if (pendingExtInt) { 677 DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 678 return new ExternalInterrupt(extIntVector); 679 } else { 680 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 681 // The only thing left are fixed and lowest priority interrupts. 682 return new ExternalInterrupt(IRRV); 683 } 684} 685 686void 687X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 688{ 689 assert(checkInterrupts(tc)); 690 if (pendingUnmaskableInt) { 691 if (pendingSmi) { 692 DPRINTF(LocalApic, "SMI sent to core.\n"); 693 pendingSmi = false; 694 } else if (pendingNmi) { 695 DPRINTF(LocalApic, "NMI sent to core.\n"); 696 pendingNmi = false; 697 } else if (pendingInit) { 698 DPRINTF(LocalApic, "Init sent to core.\n"); 699 pendingInit = false; 700 startedUp = false; 701 } else if (pendingStartup) { 702 DPRINTF(LocalApic, "SIPI sent to core.\n"); 703 pendingStartup = false; 704 startedUp = true; 705 } 706 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 707 pendingUnmaskableInt = false; 708 } else if (pendingExtInt) { 709 pendingExtInt = false; 710 } else { 711 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 712 // Mark the interrupt as "in service". 713 ISRV = IRRV; 714 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 715 // Clear it out of the IRR. 716 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 717 updateIRRV(); 718 } 719} 720 721void 722X86ISA::Interrupts::serialize(std::ostream &os) 723{ 724 SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 725 SERIALIZE_SCALAR(pendingSmi); 726 SERIALIZE_SCALAR(smiVector); 727 SERIALIZE_SCALAR(pendingNmi); 728 SERIALIZE_SCALAR(nmiVector); 729 SERIALIZE_SCALAR(pendingExtInt); 730 SERIALIZE_SCALAR(extIntVector); 731 SERIALIZE_SCALAR(pendingInit); 732 SERIALIZE_SCALAR(initVector); 733 SERIALIZE_SCALAR(pendingStartup); 734 SERIALIZE_SCALAR(startupVector); 735 SERIALIZE_SCALAR(startedUp); 736 SERIALIZE_SCALAR(pendingUnmaskableInt); 737 SERIALIZE_SCALAR(pendingIPIs); 738 SERIALIZE_SCALAR(IRRV); 739 SERIALIZE_SCALAR(ISRV); 740 bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 741 SERIALIZE_SCALAR(apicTimerEventScheduled); 742 Tick apicTimerEventTick = apicTimerEvent.when(); 743 SERIALIZE_SCALAR(apicTimerEventTick); 744} 745 746void 747X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 748{ 749 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 750 UNSERIALIZE_SCALAR(pendingSmi); 751 UNSERIALIZE_SCALAR(smiVector); 752 UNSERIALIZE_SCALAR(pendingNmi); 753 UNSERIALIZE_SCALAR(nmiVector); 754 UNSERIALIZE_SCALAR(pendingExtInt); 755 UNSERIALIZE_SCALAR(extIntVector); 756 UNSERIALIZE_SCALAR(pendingInit); 757 UNSERIALIZE_SCALAR(initVector); 758 UNSERIALIZE_SCALAR(pendingStartup); 759 UNSERIALIZE_SCALAR(startupVector); 760 UNSERIALIZE_SCALAR(startedUp); 761 UNSERIALIZE_SCALAR(pendingUnmaskableInt); 762 UNSERIALIZE_SCALAR(pendingIPIs); 763 UNSERIALIZE_SCALAR(IRRV); 764 UNSERIALIZE_SCALAR(ISRV); 765 bool apicTimerEventScheduled; 766 UNSERIALIZE_SCALAR(apicTimerEventScheduled); 767 if (apicTimerEventScheduled) { 768 Tick apicTimerEventTick; 769 UNSERIALIZE_SCALAR(apicTimerEventTick); 770 if (apicTimerEvent.scheduled()) { 771 reschedule(apicTimerEvent, apicTimerEventTick, true); 772 } else { 773 schedule(apicTimerEvent, apicTimerEventTick); 774 } 775 } 776} 777 778X86ISA::Interrupts * 779X86LocalApicParams::create() 780{ 781 return new X86ISA::Interrupts(this); 782} 783