interrupts.cc revision 9805 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder.  You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/regs/apic.hh"
53#include "arch/x86/interrupts.hh"
54#include "arch/x86/intmessage.hh"
55#include "cpu/base.hh"
56#include "debug/LocalApic.hh"
57#include "dev/x86/i82094aa.hh"
58#include "dev/x86/pc.hh"
59#include "dev/x86/south_bridge.hh"
60#include "mem/packet_access.hh"
61#include "sim/system.hh"
62#include "sim/full_system.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    pkt->makeAtomicResponse();
225    return pioDelay;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231    Addr offset = pkt->getAddr() - pioAddr;
232    //Make sure we're at least only accessing one register.
233    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234        panic("Accessed more than one register at a time in the APIC!\n");
235    ApicRegIndex reg = decodeAddr(offset);
236    uint32_t val = regs[reg];
237    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238    DPRINTF(LocalApic,
239            "Writing Local APIC register %d at offset %#x as %#x.\n",
240            reg, offset, gtoh(val));
241    setReg(reg, gtoh(val));
242    pkt->makeAtomicResponse();
243    return pioDelay;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247        uint8_t deliveryMode, bool level)
248{
249    /*
250     * Fixed and lowest-priority delivery mode interrupts are handled
251     * using the IRR/ISR registers, checking against the TPR, etc.
252     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
253     */
254    if (deliveryMode == DeliveryMode::Fixed ||
255            deliveryMode == DeliveryMode::LowestPriority) {
256        DPRINTF(LocalApic, "Interrupt is an %s.\n",
257                DeliveryMode::names[deliveryMode]);
258        // Queue up the interrupt in the IRR.
259        if (vector > IRRV)
260            IRRV = vector;
261        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
262            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
263            if (level) {
264                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            } else {
266                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
267            }
268        }
269    } else if (!DeliveryMode::isReserved(deliveryMode)) {
270        DPRINTF(LocalApic, "Interrupt is an %s.\n",
271                DeliveryMode::names[deliveryMode]);
272        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
273            pendingUnmaskableInt = pendingSmi = true;
274            smiVector = vector;
275        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
276            pendingUnmaskableInt = pendingNmi = true;
277            nmiVector = vector;
278        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
279            pendingExtInt = true;
280            extIntVector = vector;
281        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
282            pendingUnmaskableInt = pendingInit = true;
283            initVector = vector;
284        } else if (deliveryMode == DeliveryMode::SIPI &&
285                !pendingStartup && !startedUp) {
286            pendingUnmaskableInt = pendingStartup = true;
287            startupVector = vector;
288        }
289    }
290    if (FullSystem)
291        cpu->wakeup();
292}
293
294
295void
296X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
297{
298    assert(newCPU);
299    if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
300        panic("Local APICs can't be moved between CPUs"
301                " with different IDs.\n");
302    }
303    cpu = newCPU;
304    initialApicId = cpu->cpuId();
305    regs[APIC_ID] = (initialApicId << 24);
306    pioAddr = x86LocalAPICAddress(initialApicId, 0);
307}
308
309
310void
311X86ISA::Interrupts::init()
312{
313    //
314    // The local apic must register its address ranges on both its pio port
315    // via the basicpiodevice(piodevice) init() function and its int port
316    // that it inherited from IntDev.  Note IntDev is not a SimObject itself.
317    //
318    BasicPioDevice::init();
319    IntDev::init();
320
321    // the slave port has a range so inform the connected master
322    intSlavePort.sendRangeChange();
323}
324
325
326Tick
327X86ISA::Interrupts::recvMessage(PacketPtr pkt)
328{
329    Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
330    assert(pkt->cmd == MemCmd::MessageReq);
331    switch(offset)
332    {
333      case 0:
334        {
335            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
336            DPRINTF(LocalApic,
337                    "Got Trigger Interrupt message with vector %#x.\n",
338                    message.vector);
339
340            requestInterrupt(message.vector,
341                    message.deliveryMode, message.trigger);
342        }
343        break;
344      default:
345        panic("Local apic got unknown interrupt message at offset %#x.\n",
346                offset);
347        break;
348    }
349    pkt->makeAtomicResponse();
350    return pioDelay;
351}
352
353
354Tick
355X86ISA::Interrupts::recvResponse(PacketPtr pkt)
356{
357    assert(!pkt->isError());
358    assert(pkt->cmd == MemCmd::MessageResp);
359    if (--pendingIPIs == 0) {
360        InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
361        // Record that the ICR is now idle.
362        low.deliveryStatus = 0;
363        regs[APIC_INTERRUPT_COMMAND_LOW] = low;
364    }
365    DPRINTF(LocalApic, "ICR is now idle.\n");
366    return 0;
367}
368
369
370AddrRangeList
371X86ISA::Interrupts::getIntAddrRange() const
372{
373    AddrRangeList ranges;
374    ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
375                             x86InterruptAddress(initialApicId, 0) +
376                             PhysAddrAPICRangeSize));
377    return ranges;
378}
379
380
381uint32_t
382X86ISA::Interrupts::readReg(ApicRegIndex reg)
383{
384    if (reg >= APIC_TRIGGER_MODE(0) &&
385            reg <= APIC_TRIGGER_MODE(15)) {
386        panic("Local APIC Trigger Mode registers are unimplemented.\n");
387    }
388    switch (reg) {
389      case APIC_ARBITRATION_PRIORITY:
390        panic("Local APIC Arbitration Priority register unimplemented.\n");
391        break;
392      case APIC_PROCESSOR_PRIORITY:
393        panic("Local APIC Processor Priority register unimplemented.\n");
394        break;
395      case APIC_ERROR_STATUS:
396        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
397        break;
398      case APIC_CURRENT_COUNT:
399        {
400            if (apicTimerEvent.scheduled()) {
401                // Compute how many m5 ticks happen per count.
402                uint64_t ticksPerCount = clockPeriod() *
403                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
404                // Compute how many m5 ticks are left.
405                uint64_t val = apicTimerEvent.when() - curTick();
406                // Turn that into a count.
407                val = (val + ticksPerCount - 1) / ticksPerCount;
408                return val;
409            } else {
410                return 0;
411            }
412        }
413      default:
414        break;
415    }
416    return regs[reg];
417}
418
419void
420X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
421{
422    uint32_t newVal = val;
423    if (reg >= APIC_IN_SERVICE(0) &&
424            reg <= APIC_IN_SERVICE(15)) {
425        panic("Local APIC In-Service registers are unimplemented.\n");
426    }
427    if (reg >= APIC_TRIGGER_MODE(0) &&
428            reg <= APIC_TRIGGER_MODE(15)) {
429        panic("Local APIC Trigger Mode registers are unimplemented.\n");
430    }
431    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
432            reg <= APIC_INTERRUPT_REQUEST(15)) {
433        panic("Local APIC Interrupt Request registers "
434                "are unimplemented.\n");
435    }
436    switch (reg) {
437      case APIC_ID:
438        newVal = val & 0xFF;
439        break;
440      case APIC_VERSION:
441        // The Local APIC Version register is read only.
442        return;
443      case APIC_TASK_PRIORITY:
444        newVal = val & 0xFF;
445        break;
446      case APIC_ARBITRATION_PRIORITY:
447        panic("Local APIC Arbitration Priority register unimplemented.\n");
448        break;
449      case APIC_PROCESSOR_PRIORITY:
450        panic("Local APIC Processor Priority register unimplemented.\n");
451        break;
452      case APIC_EOI:
453        // Remove the interrupt that just completed from the local apic state.
454        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
455        updateISRV();
456        return;
457      case APIC_LOGICAL_DESTINATION:
458        newVal = val & 0xFF000000;
459        break;
460      case APIC_DESTINATION_FORMAT:
461        newVal = val | 0x0FFFFFFF;
462        break;
463      case APIC_SPURIOUS_INTERRUPT_VECTOR:
464        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
465        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
466        if (val & (1 << 9))
467            warn("Focus processor checking not implemented.\n");
468        break;
469      case APIC_ERROR_STATUS:
470        {
471            if (regs[APIC_INTERNAL_STATE] & 0x1) {
472                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
473                newVal = 0;
474            } else {
475                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
476                return;
477            }
478
479        }
480        break;
481      case APIC_INTERRUPT_COMMAND_LOW:
482        {
483            InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
484            // Check if we're already sending an IPI.
485            if (low.deliveryStatus) {
486                newVal = low;
487                break;
488            }
489            low = val;
490            InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
491            // Record that an IPI is being sent.
492            low.deliveryStatus = 1;
493            TriggerIntMessage message = 0;
494            message.destination = high.destination;
495            message.vector = low.vector;
496            message.deliveryMode = low.deliveryMode;
497            message.destMode = low.destMode;
498            message.level = low.level;
499            message.trigger = low.trigger;
500            bool timing(sys->isTimingMode());
501            // Be careful no updates of the delivery status bit get lost.
502            regs[APIC_INTERRUPT_COMMAND_LOW] = low;
503            ApicList apics;
504            int numContexts = sys->numContexts();
505            switch (low.destShorthand) {
506              case 0:
507                if (message.deliveryMode == DeliveryMode::LowestPriority) {
508                    panic("Lowest priority delivery mode "
509                            "IPIs aren't implemented.\n");
510                }
511                if (message.destMode == 1) {
512                    int dest = message.destination;
513                    hack_once("Assuming logical destinations are 1 << id.\n");
514                    for (int i = 0; i < numContexts; i++) {
515                        if (dest & 0x1)
516                            apics.push_back(i);
517                        dest = dest >> 1;
518                    }
519                } else {
520                    if (message.destination == 0xFF) {
521                        for (int i = 0; i < numContexts; i++) {
522                            if (i == initialApicId) {
523                                requestInterrupt(message.vector,
524                                        message.deliveryMode, message.trigger);
525                            } else {
526                                apics.push_back(i);
527                            }
528                        }
529                    } else {
530                        if (message.destination == initialApicId) {
531                            requestInterrupt(message.vector,
532                                    message.deliveryMode, message.trigger);
533                        } else {
534                            apics.push_back(message.destination);
535                        }
536                    }
537                }
538                break;
539              case 1:
540                newVal = val;
541                requestInterrupt(message.vector,
542                        message.deliveryMode, message.trigger);
543                break;
544              case 2:
545                requestInterrupt(message.vector,
546                        message.deliveryMode, message.trigger);
547                // Fall through
548              case 3:
549                {
550                    for (int i = 0; i < numContexts; i++) {
551                        if (i != initialApicId) {
552                            apics.push_back(i);
553                        }
554                    }
555                }
556                break;
557            }
558            pendingIPIs += apics.size();
559            intMasterPort.sendMessage(apics, message, timing);
560            newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
561        }
562        break;
563      case APIC_LVT_TIMER:
564      case APIC_LVT_THERMAL_SENSOR:
565      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
566      case APIC_LVT_LINT0:
567      case APIC_LVT_LINT1:
568      case APIC_LVT_ERROR:
569        {
570            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
571            newVal = (val & ~readOnlyMask) |
572                     (regs[reg] & readOnlyMask);
573        }
574        break;
575      case APIC_INITIAL_COUNT:
576        {
577            newVal = bits(val, 31, 0);
578            // Compute how many timer ticks we're being programmed for.
579            uint64_t newCount = newVal *
580                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
581            // Schedule on the edge of the next tick plus the new count.
582            Tick offset = curTick() % clockPeriod();
583            if (offset) {
584                reschedule(apicTimerEvent,
585                           curTick() + (newCount + 1) *
586                           clockPeriod() - offset, true);
587            } else {
588                if (newCount)
589                    reschedule(apicTimerEvent,
590                               curTick() + newCount *
591                               clockPeriod(), true);
592            }
593        }
594        break;
595      case APIC_CURRENT_COUNT:
596        //Local APIC Current Count register is read only.
597        return;
598      case APIC_DIVIDE_CONFIGURATION:
599        newVal = val & 0xB;
600        break;
601      default:
602        break;
603    }
604    regs[reg] = newVal;
605    return;
606}
607
608
609X86ISA::Interrupts::Interrupts(Params * p) :
610    BasicPioDevice(p), IntDev(this, p->int_latency),
611    apicTimerEvent(this),
612    pendingSmi(false), smiVector(0),
613    pendingNmi(false), nmiVector(0),
614    pendingExtInt(false), extIntVector(0),
615    pendingInit(false), initVector(0),
616    pendingStartup(false), startupVector(0),
617    startedUp(false), pendingUnmaskableInt(false),
618    pendingIPIs(0), cpu(NULL),
619    intSlavePort(name() + ".int_slave", this, this)
620{
621    pioSize = PageBytes;
622    memset(regs, 0, sizeof(regs));
623    //Set the local apic DFR to the flat model.
624    regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
625    ISRV = 0;
626    IRRV = 0;
627}
628
629
630bool
631X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
632{
633    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
634    if (pendingUnmaskableInt) {
635        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
636        return true;
637    }
638    if (rflags.intf) {
639        if (pendingExtInt) {
640            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
641            return true;
642        }
643        if (IRRV > ISRV && bits(IRRV, 7, 4) >
644               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
645            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
646            return true;
647        }
648    }
649    return false;
650}
651
652Fault
653X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
654{
655    assert(checkInterrupts(tc));
656    // These are all probably fairly uncommon, so we'll make them easier to
657    // check for.
658    if (pendingUnmaskableInt) {
659        if (pendingSmi) {
660            DPRINTF(LocalApic, "Generated SMI fault object.\n");
661            return new SystemManagementInterrupt();
662        } else if (pendingNmi) {
663            DPRINTF(LocalApic, "Generated NMI fault object.\n");
664            return new NonMaskableInterrupt(nmiVector);
665        } else if (pendingInit) {
666            DPRINTF(LocalApic, "Generated INIT fault object.\n");
667            return new InitInterrupt(initVector);
668        } else if (pendingStartup) {
669            DPRINTF(LocalApic, "Generating SIPI fault object.\n");
670            return new StartupInterrupt(startupVector);
671        } else {
672            panic("pendingUnmaskableInt set, but no unmaskable "
673                    "ints were pending.\n");
674            return NoFault;
675        }
676    } else if (pendingExtInt) {
677        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
678        return new ExternalInterrupt(extIntVector);
679    } else {
680        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
681        // The only thing left are fixed and lowest priority interrupts.
682        return new ExternalInterrupt(IRRV);
683    }
684}
685
686void
687X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
688{
689    assert(checkInterrupts(tc));
690    if (pendingUnmaskableInt) {
691        if (pendingSmi) {
692            DPRINTF(LocalApic, "SMI sent to core.\n");
693            pendingSmi = false;
694        } else if (pendingNmi) {
695            DPRINTF(LocalApic, "NMI sent to core.\n");
696            pendingNmi = false;
697        } else if (pendingInit) {
698            DPRINTF(LocalApic, "Init sent to core.\n");
699            pendingInit = false;
700            startedUp = false;
701        } else if (pendingStartup) {
702            DPRINTF(LocalApic, "SIPI sent to core.\n");
703            pendingStartup = false;
704            startedUp = true;
705        }
706        if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
707            pendingUnmaskableInt = false;
708    } else if (pendingExtInt) {
709        pendingExtInt = false;
710    } else {
711        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
712        // Mark the interrupt as "in service".
713        ISRV = IRRV;
714        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
715        // Clear it out of the IRR.
716        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
717        updateIRRV();
718    }
719}
720
721void
722X86ISA::Interrupts::serialize(std::ostream &os)
723{
724    SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
725    SERIALIZE_SCALAR(pendingSmi);
726    SERIALIZE_SCALAR(smiVector);
727    SERIALIZE_SCALAR(pendingNmi);
728    SERIALIZE_SCALAR(nmiVector);
729    SERIALIZE_SCALAR(pendingExtInt);
730    SERIALIZE_SCALAR(extIntVector);
731    SERIALIZE_SCALAR(pendingInit);
732    SERIALIZE_SCALAR(initVector);
733    SERIALIZE_SCALAR(pendingStartup);
734    SERIALIZE_SCALAR(startupVector);
735    SERIALIZE_SCALAR(startedUp);
736    SERIALIZE_SCALAR(pendingUnmaskableInt);
737    SERIALIZE_SCALAR(pendingIPIs);
738    SERIALIZE_SCALAR(IRRV);
739    SERIALIZE_SCALAR(ISRV);
740    bool apicTimerEventScheduled = apicTimerEvent.scheduled();
741    SERIALIZE_SCALAR(apicTimerEventScheduled);
742    Tick apicTimerEventTick = apicTimerEvent.when();
743    SERIALIZE_SCALAR(apicTimerEventTick);
744}
745
746void
747X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
748{
749    UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
750    UNSERIALIZE_SCALAR(pendingSmi);
751    UNSERIALIZE_SCALAR(smiVector);
752    UNSERIALIZE_SCALAR(pendingNmi);
753    UNSERIALIZE_SCALAR(nmiVector);
754    UNSERIALIZE_SCALAR(pendingExtInt);
755    UNSERIALIZE_SCALAR(extIntVector);
756    UNSERIALIZE_SCALAR(pendingInit);
757    UNSERIALIZE_SCALAR(initVector);
758    UNSERIALIZE_SCALAR(pendingStartup);
759    UNSERIALIZE_SCALAR(startupVector);
760    UNSERIALIZE_SCALAR(startedUp);
761    UNSERIALIZE_SCALAR(pendingUnmaskableInt);
762    UNSERIALIZE_SCALAR(pendingIPIs);
763    UNSERIALIZE_SCALAR(IRRV);
764    UNSERIALIZE_SCALAR(ISRV);
765    bool apicTimerEventScheduled;
766    UNSERIALIZE_SCALAR(apicTimerEventScheduled);
767    if (apicTimerEventScheduled) {
768        Tick apicTimerEventTick;
769        UNSERIALIZE_SCALAR(apicTimerEventTick);
770        if (apicTimerEvent.scheduled()) {
771            reschedule(apicTimerEvent, apicTimerEventTick, true);
772        } else {
773            schedule(apicTimerEvent, apicTimerEventTick);
774        }
775    }
776}
777
778X86ISA::Interrupts *
779X86LocalApicParams::create()
780{
781    return new X86ISA::Interrupts(this);
782}
783