registers.hh revision 9918:2c7219e2d999 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/generated/max_inst_regs.hh"
47#include "arch/arm/intregs.hh"
48#include "arch/arm/miscregs.hh"
49
50namespace ArmISA {
51
52
53// For a predicated instruction, we need all the
54// destination registers to also be sources
55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
56    ArmISAInst::MaxInstSrcRegs;
57using ArmISAInst::MaxInstDestRegs;
58using ArmISAInst::MaxMiscDestRegs;
59
60typedef uint16_t  RegIndex;
61
62typedef uint64_t IntReg;
63
64// floating point register file entry type
65typedef uint32_t FloatRegBits;
66typedef float FloatReg;
67
68// cop-0/cop-1 system control register
69typedef uint64_t MiscReg;
70
71// Constants Related to the number of registers
72const int NumIntArchRegs = NUM_ARCH_INTREGS;
73// The number of single precision floating point registers
74const int NumFloatArchRegs = 64;
75const int NumFloatSpecialRegs = 8;
76
77const int NumIntRegs = NUM_INTREGS;
78const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
79const int NumMiscRegs = NUM_MISCREGS;
80
81const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
82
83// semantically meaningful register indices
84const int ReturnValueReg = 0;
85const int ReturnValueReg1 = 1;
86const int ReturnValueReg2 = 2;
87const int NumArgumentRegs = 4;
88const int ArgumentReg0 = 0;
89const int ArgumentReg1 = 1;
90const int ArgumentReg2 = 2;
91const int ArgumentReg3 = 3;
92const int FramePointerReg = 11;
93const int StackPointerReg = INTREG_SP;
94const int ReturnAddressReg = INTREG_LR;
95const int PCReg = INTREG_PC;
96
97const int ZeroReg = INTREG_ZERO;
98
99const int SyscallNumReg = ReturnValueReg;
100const int SyscallPseudoReturnReg = ReturnValueReg;
101const int SyscallSuccessReg = ReturnValueReg;
102
103// These help enumerate all the registers for dependence tracking.
104const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1);
105const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
106const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
107
108typedef union {
109    IntReg   intreg;
110    FloatReg fpreg;
111    MiscReg  ctrlreg;
112} AnyReg;
113
114} // namespace ArmISA
115
116#endif
117