registers.hh revision 7848 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#ifndef __ARCH_ARM_REGISTERS_HH__
44#define __ARCH_ARM_REGISTERS_HH__
45
46#include "arch/arm/max_inst_regs.hh"
47#include "arch/arm/intregs.hh"
48#include "arch/arm/miscregs.hh"
49
50namespace ArmISA {
51
52
53// For a predicated instruction, we need all the
54// destination registers to also be sources
55const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
56    ArmISAInst::MaxInstSrcRegs;
57using ArmISAInst::MaxInstDestRegs;
58
59typedef uint16_t  RegIndex;
60
61typedef uint64_t IntReg;
62
63// floating point register file entry type
64typedef uint32_t FloatRegBits;
65typedef float FloatReg;
66
67// cop-0/cop-1 system control register
68typedef uint64_t MiscReg;
69
70// Constants Related to the number of registers
71const int NumIntArchRegs = NUM_ARCH_INTREGS;
72// The number of single precision floating point registers
73const int NumFloatArchRegs = 64;
74const int NumFloatSpecialRegs = 8;
75
76const int NumIntRegs = NUM_INTREGS;
77const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
78const int NumMiscRegs = NUM_MISCREGS;
79
80const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
81
82// semantically meaningful register indices
83const int ReturnValueReg = 0;
84const int ReturnValueReg1 = 1;
85const int ReturnValueReg2 = 2;
86const int NumArgumentRegs = 4;
87const int ArgumentReg0 = 0;
88const int ArgumentReg1 = 1;
89const int ArgumentReg2 = 2;
90const int ArgumentReg3 = 3;
91const int FramePointerReg = 11;
92const int StackPointerReg = INTREG_SP;
93const int ReturnAddressReg = INTREG_LR;
94const int PCReg = INTREG_PC;
95
96const int ZeroReg = INTREG_ZERO;
97
98const int SyscallNumReg = ReturnValueReg;
99const int SyscallPseudoReturnReg = ReturnValueReg;
100const int SyscallSuccessReg = ReturnValueReg;
101
102// These help enumerate all the registers for dependence tracking.
103const int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1);
104const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
105const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
106
107typedef union {
108    IntReg   intreg;
109    FloatReg fpreg;
110    MiscReg  ctrlreg;
111} AnyReg;
112
113} // namespace ArmISA
114
115#endif
116