registers.hh revision 7310 
1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Stephen Hines
29 */
30
31#ifndef __ARCH_ARM_REGISTERS_HH__
32#define __ARCH_ARM_REGISTERS_HH__
33
34#include "arch/arm/max_inst_regs.hh"
35#include "arch/arm/intregs.hh"
36#include "arch/arm/miscregs.hh"
37
38namespace ArmISA {
39
40using ArmISAInst::MaxInstSrcRegs;
41using ArmISAInst::MaxInstDestRegs;
42
43typedef uint16_t  RegIndex;
44
45typedef uint64_t IntReg;
46
47// floating point register file entry type
48typedef uint32_t FloatRegBits;
49typedef float FloatReg;
50
51// cop-0/cop-1 system control register
52typedef uint64_t MiscReg;
53
54// Constants Related to the number of registers
55const int NumIntArchRegs = NUM_ARCH_INTREGS;
56// The number of single precision floating point registers
57const int NumFloatArchRegs = 64;
58const int NumFloatSpecialRegs = 5;
59
60const int NumIntRegs = NUM_INTREGS;
61const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
62
63const int NumMiscRegs = NUM_MISCREGS;
64
65
66// semantically meaningful register indices
67const int ReturnValueReg = 0;
68const int ReturnValueReg1 = 1;
69const int ReturnValueReg2 = 2;
70const int ArgumentReg0 = 0;
71const int ArgumentReg1 = 1;
72const int ArgumentReg2 = 2;
73const int ArgumentReg3 = 3;
74const int FramePointerReg = 11;
75const int StackPointerReg = INTREG_SP;
76const int ReturnAddressReg = INTREG_LR;
77const int PCReg = INTREG_PC;
78
79const int ZeroReg = INTREG_ZERO;
80
81const int SyscallNumReg = ReturnValueReg;
82const int SyscallPseudoReturnReg = ReturnValueReg;
83const int SyscallSuccessReg = ReturnValueReg;
84
85// These help enumerate all the registers for dependence tracking.
86const int FP_Base_DepTag = NumIntRegs;
87const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
88
89typedef union {
90    IntReg   intreg;
91    FloatReg fpreg;
92    MiscReg  ctrlreg;
93} AnyReg;
94
95enum FPControlRegNums {
96   FIR = NumFloatArchRegs,
97   FCCR,
98   FEXR,
99   FENR,
100   FCSR
101};
102
103enum FCSRBits {
104    Inexact = 1,
105    Underflow,
106    Overflow,
107    DivideByZero,
108    Invalid,
109    Unimplemented
110};
111
112enum FCSRFields {
113    Flag_Field = 1,
114    Enable_Field = 6,
115    Cause_Field = 11
116};
117
118} // namespace ArmISA
119
120#endif
121