registers.hh revision 6329:5d8b91875859
1/* 2 * Copyright (c) 2007-2008 The Florida State University 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Stephen Hines 29 */ 30 31#ifndef __ARCH_ARM_REGISTERS_HH__ 32#define __ARCH_ARM_REGISTERS_HH__ 33 34#include "arch/arm/max_inst_regs.hh" 35#include "arch/arm/miscregs.hh" 36 37namespace ArmISA { 38 39using ArmISAInst::MaxInstSrcRegs; 40using ArmISAInst::MaxInstDestRegs; 41 42typedef uint8_t RegIndex; 43 44typedef uint64_t IntReg; 45 46// floating point register file entry type 47typedef uint32_t FloatRegBits; 48typedef float FloatReg; 49 50// cop-0/cop-1 system control register 51typedef uint64_t MiscReg; 52 53// Constants Related to the number of registers 54const int NumIntArchRegs = 16; 55const int NumIntSpecialRegs = 19; 56const int NumFloatArchRegs = 16; 57const int NumFloatSpecialRegs = 5; 58const int NumInternalProcRegs = 0; 59 60const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 61const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 62 63const int NumMiscRegs = NUM_MISCREGS; 64 65 66// semantically meaningful register indices 67const int ReturnValueReg = 0; 68const int ReturnValueReg1 = 1; 69const int ReturnValueReg2 = 2; 70const int ArgumentReg0 = 0; 71const int ArgumentReg1 = 1; 72const int ArgumentReg2 = 2; 73const int ArgumentReg3 = 3; 74const int FramePointerReg = 11; 75const int StackPointerReg = 13; 76const int ReturnAddressReg = 14; 77const int PCReg = 15; 78 79const int ZeroReg = NumIntArchRegs; 80const int AddrReg = ZeroReg + 1; // Used to generate address for uops 81 82const int SyscallNumReg = ReturnValueReg; 83const int SyscallPseudoReturnReg = ReturnValueReg; 84const int SyscallSuccessReg = ReturnValueReg; 85 86// These help enumerate all the registers for dependence tracking. 87const int FP_Base_DepTag = NumIntRegs; 88const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 89 90typedef union { 91 IntReg intreg; 92 FloatReg fpreg; 93 MiscReg ctrlreg; 94} AnyReg; 95 96enum FPControlRegNums { 97 FIR = NumFloatArchRegs, 98 FCCR, 99 FEXR, 100 FENR, 101 FCSR 102}; 103 104enum FCSRBits { 105 Inexact = 1, 106 Underflow, 107 Overflow, 108 DivideByZero, 109 Invalid, 110 Unimplemented 111}; 112 113enum FCSRFields { 114 Flag_Field = 1, 115 Enable_Field = 6, 116 Cause_Field = 11 117}; 118 119enum MiscIntRegNums { 120 zero_reg = NumIntArchRegs, 121 addr_reg, 122 123 rhi, 124 rlo, 125 126 r8_fiq, /* FIQ mode register bank */ 127 r9_fiq, 128 r10_fiq, 129 r11_fiq, 130 r12_fiq, 131 132 r13_fiq, /* FIQ mode SP and LR */ 133 r14_fiq, 134 135 r13_irq, /* IRQ mode SP and LR */ 136 r14_irq, 137 138 r13_svc, /* SVC mode SP and LR */ 139 r14_svc, 140 141 r13_undef, /* UNDEF mode SP and LR */ 142 r14_undef, 143 144 r13_abt, /* ABT mode SP and LR */ 145 r14_abt 146}; 147 148} // namespace ArmISA 149 150#endif 151