registers.hh revision 12104:edd63f9c6184
1/* 2 * Copyright (c) 2010-2011, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/generated/max_inst_regs.hh" 47#include "arch/arm/intregs.hh" 48#include "arch/arm/ccregs.hh" 49#include "arch/arm/miscregs.hh" 50 51namespace ArmISA { 52 53 54// For a predicated instruction, we need all the 55// destination registers to also be sources 56const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 57 ArmISAInst::MaxInstSrcRegs; 58using ArmISAInst::MaxInstDestRegs; 59using ArmISAInst::MaxMiscDestRegs; 60 61typedef uint64_t IntReg; 62 63// floating point register file entry type 64typedef uint32_t FloatRegBits; 65typedef float FloatReg; 66 67// cop-0/cop-1 system control register 68typedef uint64_t MiscReg; 69 70// condition code register; must be at least 32 bits for FpCondCodes 71typedef uint64_t CCReg; 72 73// Constants Related to the number of registers 74const int NumIntArchRegs = NUM_ARCH_INTREGS; 75// The number of single precision floating point registers 76const int NumFloatV7ArchRegs = 64; 77const int NumFloatV8ArchRegs = 128; 78const int NumFloatSpecialRegs = 32; 79 80const int NumIntRegs = NUM_INTREGS; 81const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 82const int NumCCRegs = NUM_CCREGS; 83const int NumMiscRegs = NUM_MISCREGS; 84 85#define ISA_HAS_CC_REGS 86 87const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 88 89// semantically meaningful register indices 90const int ReturnValueReg = 0; 91const int ReturnValueReg1 = 1; 92const int ReturnValueReg2 = 2; 93const int NumArgumentRegs = 4; 94const int NumArgumentRegs64 = 8; 95const int ArgumentReg0 = 0; 96const int ArgumentReg1 = 1; 97const int ArgumentReg2 = 2; 98const int ArgumentReg3 = 3; 99const int FramePointerReg = 11; 100const int StackPointerReg = INTREG_SP; 101const int ReturnAddressReg = INTREG_LR; 102const int PCReg = INTREG_PC; 103 104const int ZeroReg = INTREG_ZERO; 105 106const int SyscallNumReg = ReturnValueReg; 107const int SyscallPseudoReturnReg = ReturnValueReg; 108const int SyscallSuccessReg = ReturnValueReg; 109 110typedef union { 111 IntReg intreg; 112 FloatReg fpreg; 113 CCReg ccreg; 114 MiscReg ctrlreg; 115} AnyReg; 116 117} // namespace ArmISA 118 119#endif 120