registers.hh revision 10338:8bee5f4edb92
1/* 2 * Copyright (c) 2010-2011, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#ifndef __ARCH_ARM_REGISTERS_HH__ 44#define __ARCH_ARM_REGISTERS_HH__ 45 46#include "arch/arm/generated/max_inst_regs.hh" 47#include "arch/arm/intregs.hh" 48#include "arch/arm/ccregs.hh" 49#include "arch/arm/miscregs.hh" 50 51namespace ArmISA { 52 53 54// For a predicated instruction, we need all the 55// destination registers to also be sources 56const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 57 ArmISAInst::MaxInstSrcRegs; 58using ArmISAInst::MaxInstDestRegs; 59using ArmISAInst::MaxMiscDestRegs; 60 61typedef uint16_t RegIndex; 62 63typedef uint64_t IntReg; 64 65// floating point register file entry type 66typedef uint32_t FloatRegBits; 67typedef float FloatReg; 68 69// cop-0/cop-1 system control register 70typedef uint64_t MiscReg; 71 72// condition code register; must be at least 32 bits for FpCondCodes 73typedef uint64_t CCReg; 74 75// Constants Related to the number of registers 76const int NumIntArchRegs = NUM_ARCH_INTREGS; 77// The number of single precision floating point registers 78const int NumFloatV7ArchRegs = 64; 79const int NumFloatV8ArchRegs = 128; 80const int NumFloatSpecialRegs = 32; 81 82const int NumIntRegs = NUM_INTREGS; 83const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 84const int NumCCRegs = NUM_CCREGS; 85const int NumMiscRegs = NUM_MISCREGS; 86 87#define ISA_HAS_CC_REGS 88 89const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 90 91// semantically meaningful register indices 92const int ReturnValueReg = 0; 93const int ReturnValueReg1 = 1; 94const int ReturnValueReg2 = 2; 95const int NumArgumentRegs = 4; 96const int NumArgumentRegs64 = 8; 97const int ArgumentReg0 = 0; 98const int ArgumentReg1 = 1; 99const int ArgumentReg2 = 2; 100const int ArgumentReg3 = 3; 101const int FramePointerReg = 11; 102const int StackPointerReg = INTREG_SP; 103const int ReturnAddressReg = INTREG_LR; 104const int PCReg = INTREG_PC; 105 106const int ZeroReg = INTREG_ZERO; 107 108const int SyscallNumReg = ReturnValueReg; 109const int SyscallPseudoReturnReg = ReturnValueReg; 110const int SyscallSuccessReg = ReturnValueReg; 111 112// These help enumerate all the registers for dependence tracking. 113const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 114const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 115const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; 116const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 117 118typedef union { 119 IntReg intreg; 120 FloatReg fpreg; 121 CCReg ccreg; 122 MiscReg ctrlreg; 123} AnyReg; 124 125} // namespace ArmISA 126 127#endif 128