registers.hh revision 9921
16019SN/A/* 27649Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37649Sminkyu.jeong@arm.com * All rights reserved 47649Sminkyu.jeong@arm.com * 57649Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67649Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77649Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87649Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97649Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107649Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117649Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127649Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137649Sminkyu.jeong@arm.com * 146019SN/A * Copyright (c) 2007-2008 The Florida State University 156019SN/A * All rights reserved. 166019SN/A * 176019SN/A * Redistribution and use in source and binary forms, with or without 186019SN/A * modification, are permitted provided that the following conditions are 196019SN/A * met: redistributions of source code must retain the above copyright 206019SN/A * notice, this list of conditions and the following disclaimer; 216019SN/A * redistributions in binary form must reproduce the above copyright 226019SN/A * notice, this list of conditions and the following disclaimer in the 236019SN/A * documentation and/or other materials provided with the distribution; 246019SN/A * neither the name of the copyright holders nor the names of its 256019SN/A * contributors may be used to endorse or promote products derived from 266019SN/A * this software without specific prior written permission. 276019SN/A * 286019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019SN/A * 406019SN/A * Authors: Stephen Hines 416019SN/A */ 426019SN/A 436329Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_REGISTERS_HH__ 446329Sgblack@eecs.umich.edu#define __ARCH_ARM_REGISTERS_HH__ 456019SN/A 468961Sgblack@eecs.umich.edu#include "arch/arm/generated/max_inst_regs.hh" 478229Snate@binkert.org#include "arch/arm/intregs.hh" 486329Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 496328SN/A 506329Sgblack@eecs.umich.edunamespace ArmISA { 516328SN/A 527848SAli.Saidi@ARM.com 537848SAli.Saidi@ARM.com// For a predicated instruction, we need all the 547848SAli.Saidi@ARM.com// destination registers to also be sources 557848SAli.Saidi@ARM.comconst int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 567848SAli.Saidi@ARM.com ArmISAInst::MaxInstSrcRegs; 576329Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstDestRegs; 589046SAli.Saidi@ARM.comusing ArmISAInst::MaxMiscDestRegs; 596328SN/A 607310Sgblack@eecs.umich.edutypedef uint16_t RegIndex; 616328SN/A 626329Sgblack@eecs.umich.edutypedef uint64_t IntReg; 636328SN/A 646329Sgblack@eecs.umich.edu// floating point register file entry type 656329Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 666329Sgblack@eecs.umich.edutypedef float FloatReg; 676328SN/A 686329Sgblack@eecs.umich.edu// cop-0/cop-1 system control register 696329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 706328SN/A 719920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 729920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 739920Syasuko.eckert@amd.com 746329Sgblack@eecs.umich.edu// Constants Related to the number of registers 756717Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_ARCH_INTREGS; 767177Sgblack@eecs.umich.edu// The number of single precision floating point registers 777177Sgblack@eecs.umich.educonst int NumFloatArchRegs = 64; 787592SAli.Saidi@ARM.comconst int NumFloatSpecialRegs = 8; 796328SN/A 806717Sgblack@eecs.umich.educonst int NumIntRegs = NUM_INTREGS; 816329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 829920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 836329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 846328SN/A 857649Sminkyu.jeong@arm.comconst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 866328SN/A 876329Sgblack@eecs.umich.edu// semantically meaningful register indices 886329Sgblack@eecs.umich.educonst int ReturnValueReg = 0; 896329Sgblack@eecs.umich.educonst int ReturnValueReg1 = 1; 906329Sgblack@eecs.umich.educonst int ReturnValueReg2 = 2; 917650SAli.Saidi@ARM.comconst int NumArgumentRegs = 4; 926329Sgblack@eecs.umich.educonst int ArgumentReg0 = 0; 936329Sgblack@eecs.umich.educonst int ArgumentReg1 = 1; 946329Sgblack@eecs.umich.educonst int ArgumentReg2 = 2; 956329Sgblack@eecs.umich.educonst int ArgumentReg3 = 3; 966329Sgblack@eecs.umich.educonst int FramePointerReg = 11; 976717Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_SP; 986717Sgblack@eecs.umich.educonst int ReturnAddressReg = INTREG_LR; 996717Sgblack@eecs.umich.educonst int PCReg = INTREG_PC; 1006328SN/A 1016717Sgblack@eecs.umich.educonst int ZeroReg = INTREG_ZERO; 1026328SN/A 1036329Sgblack@eecs.umich.educonst int SyscallNumReg = ReturnValueReg; 1046329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = ReturnValueReg; 1056329Sgblack@eecs.umich.educonst int SyscallSuccessReg = ReturnValueReg; 1066328SN/A 1076329Sgblack@eecs.umich.edu// These help enumerate all the registers for dependence tracking. 1089918Ssteve.reinhardt@amd.comconst int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); 1099920Syasuko.eckert@amd.comconst int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 1109920Syasuko.eckert@amd.comconst int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 1119918Ssteve.reinhardt@amd.comconst int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 1126329Sgblack@eecs.umich.edu 1136329Sgblack@eecs.umich.edutypedef union { 1146329Sgblack@eecs.umich.edu IntReg intreg; 1156329Sgblack@eecs.umich.edu FloatReg fpreg; 1166329Sgblack@eecs.umich.edu MiscReg ctrlreg; 1176329Sgblack@eecs.umich.edu} AnyReg; 1186329Sgblack@eecs.umich.edu 1196328SN/A} // namespace ArmISA 1206019SN/A 1216019SN/A#endif 122