registers.hh revision 8961
17202Sgblack@eecs.umich.edu/* 27202Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37202Sgblack@eecs.umich.edu * All rights reserved 47202Sgblack@eecs.umich.edu * 57202Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67202Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77202Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87202Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97202Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107202Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117202Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127202Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137202Sgblack@eecs.umich.edu * 147202Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157202Sgblack@eecs.umich.edu * All rights reserved. 167202Sgblack@eecs.umich.edu * 177202Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187202Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197202Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207202Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217202Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227202Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237202Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247202Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257202Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267202Sgblack@eecs.umich.edu * this software without specific prior written permission. 277202Sgblack@eecs.umich.edu * 287202Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297202Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307202Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317202Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327202Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337202Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347202Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357202Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367202Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377202Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387202Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397202Sgblack@eecs.umich.edu * 407202Sgblack@eecs.umich.edu * Authors: Stephen Hines 417202Sgblack@eecs.umich.edu */ 427202Sgblack@eecs.umich.edu 437202Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_REGISTERS_HH__ 447202Sgblack@eecs.umich.edu#define __ARCH_ARM_REGISTERS_HH__ 457202Sgblack@eecs.umich.edu 467202Sgblack@eecs.umich.edu#include "arch/arm/generated/max_inst_regs.hh" 477202Sgblack@eecs.umich.edu#include "arch/arm/intregs.hh" 487202Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 497202Sgblack@eecs.umich.edu 507202Sgblack@eecs.umich.edunamespace ArmISA { 517202Sgblack@eecs.umich.edu 527202Sgblack@eecs.umich.edu 537202Sgblack@eecs.umich.edu// For a predicated instruction, we need all the 547202Sgblack@eecs.umich.edu// destination registers to also be sources 557202Sgblack@eecs.umich.educonst int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 567202Sgblack@eecs.umich.edu ArmISAInst::MaxInstSrcRegs; 577202Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstDestRegs; 587202Sgblack@eecs.umich.edu 597202Sgblack@eecs.umich.edutypedef uint16_t RegIndex; 607202Sgblack@eecs.umich.edu 617202Sgblack@eecs.umich.edutypedef uint64_t IntReg; 627202Sgblack@eecs.umich.edu 637202Sgblack@eecs.umich.edu// floating point register file entry type 647202Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 657202Sgblack@eecs.umich.edutypedef float FloatReg; 667202Sgblack@eecs.umich.edu 677202Sgblack@eecs.umich.edu// cop-0/cop-1 system control register 687202Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 697202Sgblack@eecs.umich.edu 707202Sgblack@eecs.umich.edu// Constants Related to the number of registers 717202Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_ARCH_INTREGS; 727202Sgblack@eecs.umich.edu// The number of single precision floating point registers 737202Sgblack@eecs.umich.educonst int NumFloatArchRegs = 64; 747202Sgblack@eecs.umich.educonst int NumFloatSpecialRegs = 8; 757202Sgblack@eecs.umich.edu 767202Sgblack@eecs.umich.educonst int NumIntRegs = NUM_INTREGS; 777202Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 787202Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 797202Sgblack@eecs.umich.edu 807202Sgblack@eecs.umich.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 817202Sgblack@eecs.umich.edu 827202Sgblack@eecs.umich.edu// semantically meaningful register indices 837202Sgblack@eecs.umich.educonst int ReturnValueReg = 0; 847202Sgblack@eecs.umich.educonst int ReturnValueReg1 = 1; 857202Sgblack@eecs.umich.educonst int ReturnValueReg2 = 2; 867202Sgblack@eecs.umich.educonst int NumArgumentRegs = 4; 877202Sgblack@eecs.umich.educonst int ArgumentReg0 = 0; 887202Sgblack@eecs.umich.educonst int ArgumentReg1 = 1; 897202Sgblack@eecs.umich.educonst int ArgumentReg2 = 2; 907202Sgblack@eecs.umich.educonst int ArgumentReg3 = 3; 917202Sgblack@eecs.umich.educonst int FramePointerReg = 11; 927202Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_SP; 937202Sgblack@eecs.umich.educonst int ReturnAddressReg = INTREG_LR; 947202Sgblack@eecs.umich.educonst int PCReg = INTREG_PC; 957202Sgblack@eecs.umich.edu 967202Sgblack@eecs.umich.educonst int ZeroReg = INTREG_ZERO; 977202Sgblack@eecs.umich.edu 987202Sgblack@eecs.umich.educonst int SyscallNumReg = ReturnValueReg; 997202Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = ReturnValueReg; 1007202Sgblack@eecs.umich.educonst int SyscallSuccessReg = ReturnValueReg; 1017208Sgblack@eecs.umich.edu 1027208Sgblack@eecs.umich.edu// These help enumerate all the registers for dependence tracking. 1037208Sgblack@eecs.umich.educonst int FP_Base_DepTag = NumIntRegs * (MODE_MAXMODE + 1); 1047208Sgblack@eecs.umich.educonst int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 1057208Sgblack@eecs.umich.educonst int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs; 1067208Sgblack@eecs.umich.edu 1077208Sgblack@eecs.umich.edutypedef union { 1087208Sgblack@eecs.umich.edu IntReg intreg; 1097208Sgblack@eecs.umich.edu FloatReg fpreg; 1107208Sgblack@eecs.umich.edu MiscReg ctrlreg; 1117208Sgblack@eecs.umich.edu} AnyReg; 1127208Sgblack@eecs.umich.edu 1137208Sgblack@eecs.umich.edu} // namespace ArmISA 1147208Sgblack@eecs.umich.edu 1157208Sgblack@eecs.umich.edu#endif 1167208Sgblack@eecs.umich.edu