registers.hh revision 6328
16791SN/A/* 26791SN/A * Copyright (c) 2007-2008 The Florida State University 36791SN/A * All rights reserved. 46791SN/A * 56791SN/A * Redistribution and use in source and binary forms, with or without 66791SN/A * modification, are permitted provided that the following conditions are 76791SN/A * met: redistributions of source code must retain the above copyright 86791SN/A * notice, this list of conditions and the following disclaimer; 96791SN/A * redistributions in binary form must reproduce the above copyright 106791SN/A * notice, this list of conditions and the following disclaimer in the 116791SN/A * documentation and/or other materials provided with the distribution; 126791SN/A * neither the name of the copyright holders nor the names of its 136791SN/A * contributors may be used to endorse or promote products derived from 146791SN/A * this software without specific prior written permission. 156791SN/A * 166791SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176791SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186791SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196791SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206791SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216791SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226791SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236791SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246791SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256791SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266791SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276791SN/A * 286791SN/A * Authors: Stephen Hines 2910441Snilay@cs.wisc.edu */ 3010441Snilay@cs.wisc.edu 316791SN/A#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__ 327055SN/A#define __ARCH_ARM_REGFILE_REGFILE_HH__ 3311168Sandreas.hansson@arm.com 347055SN/A#include "arch/arm/types.hh" 357039SN/A#include "arch/arm/misc_regfile.hh" 367039SN/A#include "sim/faults.hh" 3710301Snilay@cs.wisc.edu 387039SN/Aclass Checkpoint; 396791SN/Aclass EventManager; 407039SN/Aclass ThreadContext; 417039SN/A 427039SN/Anamespace ArmISA 438607SN/A{ 447055SN/A enum FPControlRegNums { 456791SN/A FIR = NumFloatArchRegs, 467039SN/A FCCR, 477039SN/A FEXR, 487039SN/A FENR, 496797SN/A FCSR 506791SN/A }; 517039SN/A 527039SN/A enum FCSRBits { 537039SN/A Inexact = 1, 547039SN/A Underflow, 557039SN/A Overflow, 566791SN/A DivideByZero, 577039SN/A Invalid, 587039SN/A Unimplemented 597054SN/A }; 607039SN/A 6111025Snilay@cs.wisc.edu enum FCSRFields { 627039SN/A Flag_Field = 1, 6311025Snilay@cs.wisc.edu Enable_Field = 6, 6411025Snilay@cs.wisc.edu Cause_Field = 11 6511025Snilay@cs.wisc.edu }; 6611025Snilay@cs.wisc.edu 6711025Snilay@cs.wisc.edu enum MiscIntRegNums { 6811025Snilay@cs.wisc.edu zero_reg = NumIntArchRegs, 6911025Snilay@cs.wisc.edu addr_reg, 7011025Snilay@cs.wisc.edu 716791SN/A rhi, 727055SN/A rlo, 736791SN/A 747039SN/A r8_fiq, /* FIQ mode register bank */ 757039SN/A r9_fiq, 767039SN/A r10_fiq, 777039SN/A r11_fiq, 786791SN/A r12_fiq, 797039SN/A 8011168Sandreas.hansson@arm.com r13_fiq, /* FIQ mode SP and LR */ 817455SN/A r14_fiq, 826791SN/A 836791SN/A r13_irq, /* IRQ mode SP and LR */ 847055SN/A r14_irq, 857055SN/A 866791SN/A r13_svc, /* SVC mode SP and LR */ 877039SN/A r14_svc, 887055SN/A 897039SN/A r13_undef, /* UNDEF mode SP and LR */ 906791SN/A r14_undef, 916791SN/A 927055SN/A r13_abt, /* ABT mode SP and LR */ 937055SN/A r14_abt 946797SN/A }; 957039SN/A 967055SN/A void copyRegs(ThreadContext *src, ThreadContext *dest); 977039SN/A 986797SN/A void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 996797SN/A 10010441Snilay@cs.wisc.edu} // namespace ArmISA 101 102#endif 103