registers.hh revision 13759
12623SN/A/* 22623SN/A * Copyright (c) 2010-2011, 2014, 2016-2017 ARM Limited 32623SN/A * All rights reserved 42623SN/A * 52623SN/A * The license below extends only to copyright in the software and shall 62623SN/A * not be construed as granting a license to any other intellectual 72623SN/A * property including but not limited to intellectual property relating 82623SN/A * to a hardware implementation of the functionality of the software 92623SN/A * licensed hereunder. You may use the software subject to the license 102623SN/A * terms below provided that you ensure that this notice is replicated 112623SN/A * unmodified and in its entirety in all distributions of the software, 122623SN/A * modified or unmodified, in source code or in binary form. 132623SN/A * 142623SN/A * Copyright (c) 2007-2008 The Florida State University 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323806Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344040Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373348Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383348Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394762Snate@binkert.org * 402901Ssaidi@eecs.umich.edu * Authors: Stephen Hines 412623SN/A */ 422623SN/A 432623SN/A#ifndef __ARCH_ARM_REGISTERS_HH__ 442623SN/A#define __ARCH_ARM_REGISTERS_HH__ 452623SN/A 462623SN/A#include "arch/arm/ccregs.hh" 472623SN/A#include "arch/arm/generated/max_inst_regs.hh" 482623SN/A#include "arch/arm/intregs.hh" 492623SN/A#include "arch/arm/miscregs.hh" 502623SN/A#include "arch/arm/types.hh" 512623SN/A#include "arch/generic/vec_pred_reg.hh" 522623SN/A#include "arch/generic/vec_reg.hh" 532623SN/A 542623SN/Anamespace ArmISA { 552623SN/A 562623SN/A 572623SN/A// For a predicated instruction, we need all the 582623SN/A// destination registers to also be sources 592623SN/Aconst int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 604873Sstever@eecs.umich.edu ArmISAInst::MaxInstSrcRegs; 612623SN/Ausing ArmISAInst::MaxInstDestRegs; 622623SN/Ausing ArmISAInst::MaxMiscDestRegs; 632856Srdreslin@umich.edu 642856Srdreslin@umich.edu// Number of VecElem per Vector Register, computed based on the vector length 652856Srdreslin@umich.educonstexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords; 662856Srdreslin@umich.edu 672856Srdreslin@umich.eduusing VecElem = uint32_t; 682856Srdreslin@umich.eduusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 692856Srdreslin@umich.eduusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 704968Sacolyte@umich.eduusing VecRegContainer = VecReg::Container; 714968Sacolyte@umich.edu 724968Sacolyte@umich.eduusing VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, 734968Sacolyte@umich.edu VecPredRegHasPackedRepr, false>; 742856Srdreslin@umich.eduusing ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg, 752856Srdreslin@umich.edu VecPredRegHasPackedRepr, true>; 762856Srdreslin@umich.eduusing VecPredRegContainer = VecPredReg::Container; 772623SN/A 782623SN/A// Constants Related to the number of registers 792623SN/Aconst int NumIntArchRegs = NUM_ARCH_INTREGS; 802623SN/A// The number of single precision floating point registers 812623SN/Aconst int NumFloatV7ArchRegs = 64; 822623SN/Aconst int NumFloatV8ArchRegs = 128; 832680Sktlim@umich.educonst int NumFloatSpecialRegs = 32; 842680Sktlim@umich.educonst int NumVecV7ArchRegs = 64; 852623SN/Aconst int NumVecV8ArchRegs = 32; 862623SN/Aconst int NumVecSpecialRegs = 8; 872680Sktlim@umich.edu 882623SN/Aconst int NumIntRegs = NUM_INTREGS; 892623SN/Aconst int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 904968Sacolyte@umich.educonst int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; 914968Sacolyte@umich.educonst int NumVecPredRegs = 17; // P0-P15, FFR 924968Sacolyte@umich.educonst int PREDREG_FFR = 16; 934968Sacolyte@umich.educonst int NumCCRegs = NUM_CCREGS; 944968Sacolyte@umich.educonst int NumMiscRegs = NUM_MISCREGS; 954968Sacolyte@umich.edu 962623SN/A#define ISA_HAS_CC_REGS 972623SN/A 982623SN/Aconst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + 993349Sbinkertn@umich.edu NumVecPredRegs + NumMiscRegs; 1002623SN/A 1013184Srdreslin@umich.edu// semantically meaningful register indices 1022623SN/Aconst int ReturnValueReg = 0; 1032623SN/Aconst int ReturnValueReg1 = 1; 1042623SN/Aconst int ReturnValueReg2 = 2; 1052623SN/Aconst int NumArgumentRegs = 4; 1063349Sbinkertn@umich.educonst int NumArgumentRegs64 = 8; 1072623SN/Aconst int ArgumentReg0 = 0; 1083310Srdreslin@umich.educonst int ArgumentReg1 = 1; 1093649Srdreslin@umich.educonst int ArgumentReg2 = 2; 1102623SN/Aconst int ArgumentReg3 = 3; 1112623SN/Aconst int FramePointerReg = 11; 1122623SN/Aconst int StackPointerReg = INTREG_SP; 1133349Sbinkertn@umich.educonst int ReturnAddressReg = INTREG_LR; 1142623SN/Aconst int PCReg = INTREG_PC; 1153184Srdreslin@umich.edu 1163184Srdreslin@umich.educonst int ZeroReg = INTREG_ZERO; 1172623SN/A 1182623SN/Aconst int SyscallNumReg = ReturnValueReg; 1192623SN/Aconst int SyscallPseudoReturnReg = ReturnValueReg; 1202623SN/Aconst int SyscallSuccessReg = ReturnValueReg; 1212623SN/A 1223647Srdreslin@umich.edu} // namespace ArmISA 1233647Srdreslin@umich.edu 1243647Srdreslin@umich.edu#endif 1253647Srdreslin@umich.edu