registers.hh revision 13610
16019SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2011, 2014, 2016 ARM Limited 37649Sminkyu.jeong@arm.com * All rights reserved 47649Sminkyu.jeong@arm.com * 57649Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67649Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77649Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87649Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97649Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107649Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117649Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127649Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137649Sminkyu.jeong@arm.com * 146019SN/A * Copyright (c) 2007-2008 The Florida State University 156019SN/A * All rights reserved. 166019SN/A * 176019SN/A * Redistribution and use in source and binary forms, with or without 186019SN/A * modification, are permitted provided that the following conditions are 196019SN/A * met: redistributions of source code must retain the above copyright 206019SN/A * notice, this list of conditions and the following disclaimer; 216019SN/A * redistributions in binary form must reproduce the above copyright 226019SN/A * notice, this list of conditions and the following disclaimer in the 236019SN/A * documentation and/or other materials provided with the distribution; 246019SN/A * neither the name of the copyright holders nor the names of its 256019SN/A * contributors may be used to endorse or promote products derived from 266019SN/A * this software without specific prior written permission. 276019SN/A * 286019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019SN/A * 406019SN/A * Authors: Stephen Hines 416019SN/A */ 426019SN/A 436329Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_REGISTERS_HH__ 446329Sgblack@eecs.umich.edu#define __ARCH_ARM_REGISTERS_HH__ 456019SN/A 4612109SRekai.GonzalezAlberquilla@arm.com#include "arch/arm/ccregs.hh" 478961Sgblack@eecs.umich.edu#include "arch/arm/generated/max_inst_regs.hh" 488229Snate@binkert.org#include "arch/arm/intregs.hh" 496329Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5013610Sgiacomo.gabrielli@arm.com#include "arch/arm/types.hh" 5113610Sgiacomo.gabrielli@arm.com#include "arch/generic/vec_pred_reg.hh" 5212109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 536328SN/A 546329Sgblack@eecs.umich.edunamespace ArmISA { 556328SN/A 567848SAli.Saidi@ARM.com 577848SAli.Saidi@ARM.com// For a predicated instruction, we need all the 587848SAli.Saidi@ARM.com// destination registers to also be sources 597848SAli.Saidi@ARM.comconst int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + 607848SAli.Saidi@ARM.com ArmISAInst::MaxInstSrcRegs; 616329Sgblack@eecs.umich.eduusing ArmISAInst::MaxInstDestRegs; 629046SAli.Saidi@ARM.comusing ArmISAInst::MaxMiscDestRegs; 636328SN/A 6412109SRekai.GonzalezAlberquilla@arm.com// Number of VecElem per Vector Register, computed based on the vector length 6512109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 4; 6612109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t; 6712109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 6812109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 6912109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container; 7012109SRekai.GonzalezAlberquilla@arm.com 7113610Sgiacomo.gabrielli@arm.comconstexpr size_t VecRegSizeBytes = NumVecElemPerVecReg * sizeof(VecElem); 7213610Sgiacomo.gabrielli@arm.com 7313610Sgiacomo.gabrielli@arm.com// Dummy typedefs 7413610Sgiacomo.gabrielli@arm.comusing VecPredReg = ::DummyVecPredReg; 7513610Sgiacomo.gabrielli@arm.comusing ConstVecPredReg = ::DummyConstVecPredReg; 7613610Sgiacomo.gabrielli@arm.comusing VecPredRegContainer = ::DummyVecPredRegContainer; 7713610Sgiacomo.gabrielli@arm.comconstexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 7813610Sgiacomo.gabrielli@arm.comconstexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 7913610Sgiacomo.gabrielli@arm.com 8010338SCurtis.Dunham@arm.com// condition code register; must be at least 32 bits for FpCondCodes 8110338SCurtis.Dunham@arm.comtypedef uint64_t CCReg; 829920Syasuko.eckert@amd.com 836329Sgblack@eecs.umich.edu// Constants Related to the number of registers 846717Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_ARCH_INTREGS; 857177Sgblack@eecs.umich.edu// The number of single precision floating point registers 8610037SARM gem5 Developersconst int NumFloatV7ArchRegs = 64; 8710037SARM gem5 Developersconst int NumFloatV8ArchRegs = 128; 8810037SARM gem5 Developersconst int NumFloatSpecialRegs = 32; 8912109SRekai.GonzalezAlberquilla@arm.comconst int NumVecV7ArchRegs = 64; 9012109SRekai.GonzalezAlberquilla@arm.comconst int NumVecV8ArchRegs = 32; 9112109SRekai.GonzalezAlberquilla@arm.comconst int NumVecSpecialRegs = 8; 926328SN/A 936717Sgblack@eecs.umich.educonst int NumIntRegs = NUM_INTREGS; 9410037SARM gem5 Developersconst int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; 9512109SRekai.GonzalezAlberquilla@arm.comconst int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; 9613610Sgiacomo.gabrielli@arm.comconst int NumVecPredRegs = 1; 9710338SCurtis.Dunham@arm.comconst int NumCCRegs = NUM_CCREGS; 986329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 996328SN/A 10010338SCurtis.Dunham@arm.com#define ISA_HAS_CC_REGS 10110338SCurtis.Dunham@arm.com 10213610Sgiacomo.gabrielli@arm.comconst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + 10313610Sgiacomo.gabrielli@arm.com NumVecPredRegs + NumMiscRegs; 1046328SN/A 1056329Sgblack@eecs.umich.edu// semantically meaningful register indices 1066329Sgblack@eecs.umich.educonst int ReturnValueReg = 0; 1076329Sgblack@eecs.umich.educonst int ReturnValueReg1 = 1; 1086329Sgblack@eecs.umich.educonst int ReturnValueReg2 = 2; 1097650SAli.Saidi@ARM.comconst int NumArgumentRegs = 4; 11010037SARM gem5 Developersconst int NumArgumentRegs64 = 8; 1116329Sgblack@eecs.umich.educonst int ArgumentReg0 = 0; 1126329Sgblack@eecs.umich.educonst int ArgumentReg1 = 1; 1136329Sgblack@eecs.umich.educonst int ArgumentReg2 = 2; 1146329Sgblack@eecs.umich.educonst int ArgumentReg3 = 3; 1156329Sgblack@eecs.umich.educonst int FramePointerReg = 11; 1166717Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_SP; 1176717Sgblack@eecs.umich.educonst int ReturnAddressReg = INTREG_LR; 1186717Sgblack@eecs.umich.educonst int PCReg = INTREG_PC; 1196328SN/A 1206717Sgblack@eecs.umich.educonst int ZeroReg = INTREG_ZERO; 1216328SN/A 1226329Sgblack@eecs.umich.educonst int SyscallNumReg = ReturnValueReg; 1236329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = ReturnValueReg; 1246329Sgblack@eecs.umich.educonst int SyscallSuccessReg = ReturnValueReg; 1256328SN/A 1266328SN/A} // namespace ArmISA 1276019SN/A 1286019SN/A#endif 129