miscregs_types.hh revision 13118
19397Sandreas.hansson@arm.com/* 29397Sandreas.hansson@arm.com * Copyright (c) 2010-2018 ARM Limited 39397Sandreas.hansson@arm.com * All rights reserved 49397Sandreas.hansson@arm.com * 59397Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69397Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79397Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89397Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99397Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109397Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119397Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129397Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139397Sandreas.hansson@arm.com * 149397Sandreas.hansson@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 159397Sandreas.hansson@arm.com * All rights reserved. 169397Sandreas.hansson@arm.com * 179397Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 189397Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 199397Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 209397Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 219397Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 229397Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 239397Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 249397Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 259397Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 269397Sandreas.hansson@arm.com * this software without specific prior written permission. 279397Sandreas.hansson@arm.com * 289397Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299397Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309397Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319397Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329397Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339397Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349397Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359397Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369397Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379397Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389397Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399397Sandreas.hansson@arm.com * 409397Sandreas.hansson@arm.com * Authors: Gabe Black 419397Sandreas.hansson@arm.com * Giacomo Gabrielli 429397Sandreas.hansson@arm.com */ 439397Sandreas.hansson@arm.com 449397Sandreas.hansson@arm.com#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__ 459397Sandreas.hansson@arm.com#define __ARCH_ARM_MISCREGS_TYPES_HH__ 469397Sandreas.hansson@arm.com 479397Sandreas.hansson@arm.com#include "base/bitunion.hh" 489397Sandreas.hansson@arm.com 499397Sandreas.hansson@arm.comnamespace ArmISA 509397Sandreas.hansson@arm.com{ 519397Sandreas.hansson@arm.com BitUnion32(CPSR) 529397Sandreas.hansson@arm.com Bitfield<31, 30> nz; 539397Sandreas.hansson@arm.com Bitfield<29> c; 549397Sandreas.hansson@arm.com Bitfield<28> v; 559397Sandreas.hansson@arm.com Bitfield<27> q; 569397Sandreas.hansson@arm.com Bitfield<26, 25> it1; 579397Sandreas.hansson@arm.com Bitfield<24> j; 589397Sandreas.hansson@arm.com Bitfield<23, 22> res0_23_22; 599397Sandreas.hansson@arm.com Bitfield<21> ss; // AArch64 609397Sandreas.hansson@arm.com Bitfield<20> il; // AArch64 619397Sandreas.hansson@arm.com Bitfield<19, 16> ge; 629397Sandreas.hansson@arm.com Bitfield<15, 10> it2; 639397Sandreas.hansson@arm.com Bitfield<9> d; // AArch64 649397Sandreas.hansson@arm.com Bitfield<9> e; 659397Sandreas.hansson@arm.com Bitfield<8> a; 669397Sandreas.hansson@arm.com Bitfield<7> i; 679397Sandreas.hansson@arm.com Bitfield<6> f; 689397Sandreas.hansson@arm.com Bitfield<8, 6> aif; 699397Sandreas.hansson@arm.com Bitfield<9, 6> daif; // AArch64 709397Sandreas.hansson@arm.com Bitfield<5> t; 719397Sandreas.hansson@arm.com Bitfield<4> width; // AArch64 729397Sandreas.hansson@arm.com Bitfield<3, 2> el; // AArch64 739397Sandreas.hansson@arm.com Bitfield<4, 0> mode; 749397Sandreas.hansson@arm.com Bitfield<0> sp; // AArch64 759397Sandreas.hansson@arm.com EndBitUnion(CPSR) 769397Sandreas.hansson@arm.com 779397Sandreas.hansson@arm.com BitUnion64(AA64DFR0) 789397Sandreas.hansson@arm.com Bitfield<43, 40> tracefilt; 799397Sandreas.hansson@arm.com Bitfield<39, 36> doublelock; 809397Sandreas.hansson@arm.com Bitfield<35, 32> pmsver; 819397Sandreas.hansson@arm.com Bitfield<31, 28> ctx_cmps; 829397Sandreas.hansson@arm.com Bitfield<23, 20> wrps; 839397Sandreas.hansson@arm.com Bitfield<15, 12> brps; 849397Sandreas.hansson@arm.com Bitfield<11, 8> pmuver; 859397Sandreas.hansson@arm.com Bitfield<7, 4> tracever; 869397Sandreas.hansson@arm.com Bitfield<3, 0> debugver; 879397Sandreas.hansson@arm.com EndBitUnion(AA64DFR0) 889397Sandreas.hansson@arm.com 899397Sandreas.hansson@arm.com BitUnion64(AA64ISAR0) 909397Sandreas.hansson@arm.com Bitfield<63, 60> rndr; 919397Sandreas.hansson@arm.com Bitfield<59, 56> tlb; 929397Sandreas.hansson@arm.com Bitfield<55, 52> ts; 939397Sandreas.hansson@arm.com Bitfield<51, 48> fhm; 94 Bitfield<47, 44> dp; 95 Bitfield<43, 40> sm4; 96 Bitfield<39, 36> sm3; 97 Bitfield<35, 32> sha3; 98 Bitfield<31, 28> rdm; 99 Bitfield<23, 20> atomic; 100 Bitfield<19, 16> crc32; 101 Bitfield<15, 12> sha2; 102 Bitfield<11, 8> sha1; 103 Bitfield<3, 0> aes; 104 EndBitUnion(AA64ISAR0) 105 106 BitUnion64(AA64ISAR1) 107 Bitfield<43, 40> specres; 108 Bitfield<39, 36> sb; 109 Bitfield<35, 32> frintts; 110 Bitfield<31, 28> gpi; 111 Bitfield<27, 24> gpa; 112 Bitfield<23, 20> lrcpc; 113 Bitfield<19, 16> fcma; 114 Bitfield<15, 12> jscvt; 115 Bitfield<11, 8> api; 116 Bitfield<7, 4> apa; 117 Bitfield<3, 0> dpb; 118 EndBitUnion(AA64ISAR1) 119 120 BitUnion64(AA64MMFR0) 121 Bitfield<47, 44> exs; 122 Bitfield<43, 40> tgran4_2; 123 Bitfield<39, 36> tgran64_2; 124 Bitfield<35, 32> tgran16_2; 125 Bitfield<31, 28> tgran4; 126 Bitfield<27, 24> tgran64; 127 Bitfield<23, 20> tgran16; 128 Bitfield<19, 16> bigendEL0; 129 Bitfield<15, 12> snsmem; 130 Bitfield<11, 8> bigend; 131 Bitfield<7, 4> asidbits; 132 Bitfield<3, 0> parange; 133 EndBitUnion(AA64MMFR0) 134 135 BitUnion64(AA64MMFR1) 136 Bitfield<31, 28> xnx; 137 Bitfield<27, 24> specsei; 138 Bitfield<23, 20> pan; 139 Bitfield<19, 16> lo; 140 Bitfield<15, 12> hpds; 141 Bitfield<11, 8> vh; 142 Bitfield<7, 4> vmidbits; 143 Bitfield<3, 0> hafdbs; 144 EndBitUnion(AA64MMFR1) 145 146 BitUnion64(AA64MMFR2) 147 Bitfield<63, 60> e0pd; 148 Bitfield<59, 56> evt; 149 Bitfield<55, 52> bbm; 150 Bitfield<51, 48> ttl; 151 Bitfield<43, 40> fwb; 152 Bitfield<39, 36> ids; 153 Bitfield<35, 32> at; 154 Bitfield<31, 28> st; 155 Bitfield<27, 24> nv; 156 Bitfield<23, 20> ccidx; 157 Bitfield<19, 16> varange; 158 Bitfield<15, 12> iesb; 159 Bitfield<11, 8> lsm; 160 Bitfield<7, 4> uao; 161 Bitfield<3, 0> cnp; 162 EndBitUnion(AA64MMFR2) 163 164 BitUnion64(AA64PFR0) 165 Bitfield<63, 60> csv3; 166 Bitfield<59, 56> csv2; 167 Bitfield<51, 48> dit; 168 Bitfield<47, 44> amu; 169 Bitfield<43, 40> mpam; 170 Bitfield<39, 36> sel2; 171 Bitfield<35, 32> sve; 172 Bitfield<31, 28> ras; 173 Bitfield<27, 24> gic; 174 Bitfield<23, 20> advsimd; 175 Bitfield<19, 16> fp; 176 Bitfield<15, 12> el3; 177 Bitfield<11, 8> el2; 178 Bitfield<7, 4> el1; 179 Bitfield<3, 0> el0; 180 EndBitUnion(AA64PFR0) 181 182 BitUnion32(HDCR) 183 Bitfield<11> tdra; 184 Bitfield<10> tdosa; 185 Bitfield<9> tda; 186 Bitfield<8> tde; 187 Bitfield<7> hpme; 188 Bitfield<6> tpm; 189 Bitfield<5> tpmcr; 190 Bitfield<4, 0> hpmn; 191 EndBitUnion(HDCR) 192 193 BitUnion32(HCPTR) 194 Bitfield<31> tcpac; 195 Bitfield<20> tta; 196 Bitfield<15> tase; 197 Bitfield<13> tcp13; 198 Bitfield<12> tcp12; 199 Bitfield<11> tcp11; 200 Bitfield<10> tcp10; 201 Bitfield<10> tfp; // AArch64 202 Bitfield<9> tcp9; 203 Bitfield<8> tcp8; 204 Bitfield<7> tcp7; 205 Bitfield<6> tcp6; 206 Bitfield<5> tcp5; 207 Bitfield<4> tcp4; 208 Bitfield<3> tcp3; 209 Bitfield<2> tcp2; 210 Bitfield<1> tcp1; 211 Bitfield<0> tcp0; 212 EndBitUnion(HCPTR) 213 214 BitUnion32(HSTR) 215 Bitfield<17> tjdbx; 216 Bitfield<16> ttee; 217 Bitfield<15> t15; 218 Bitfield<13> t13; 219 Bitfield<12> t12; 220 Bitfield<11> t11; 221 Bitfield<10> t10; 222 Bitfield<9> t9; 223 Bitfield<8> t8; 224 Bitfield<7> t7; 225 Bitfield<6> t6; 226 Bitfield<5> t5; 227 Bitfield<4> t4; 228 Bitfield<3> t3; 229 Bitfield<2> t2; 230 Bitfield<1> t1; 231 Bitfield<0> t0; 232 EndBitUnion(HSTR) 233 234 BitUnion64(HCR) 235 Bitfield<34> e2h; // AArch64 236 Bitfield<33> id; // AArch64 237 Bitfield<32> cd; // AArch64 238 Bitfield<31> rw; // AArch64 239 Bitfield<30> trvm; // AArch64 240 Bitfield<29> hcd; // AArch64 241 Bitfield<28> tdz; // AArch64 242 243 Bitfield<27> tge; 244 Bitfield<26> tvm; 245 Bitfield<25> ttlb; 246 Bitfield<24> tpu; 247 Bitfield<23> tpc; 248 Bitfield<22> tsw; 249 Bitfield<21> tac; 250 Bitfield<21> tacr; // AArch64 251 Bitfield<20> tidcp; 252 Bitfield<19> tsc; 253 Bitfield<18> tid3; 254 Bitfield<17> tid2; 255 Bitfield<16> tid1; 256 Bitfield<15> tid0; 257 Bitfield<14> twe; 258 Bitfield<13> twi; 259 Bitfield<12> dc; 260 Bitfield<11, 10> bsu; 261 Bitfield<9> fb; 262 Bitfield<8> va; 263 Bitfield<8> vse; // AArch64 264 Bitfield<7> vi; 265 Bitfield<6> vf; 266 Bitfield<5> amo; 267 Bitfield<4> imo; 268 Bitfield<3> fmo; 269 Bitfield<2> ptw; 270 Bitfield<1> swio; 271 Bitfield<0> vm; 272 EndBitUnion(HCR) 273 274 BitUnion32(NSACR) 275 Bitfield<20> nstrcdis; 276 Bitfield<19> rfr; 277 Bitfield<15> nsasedis; 278 Bitfield<14> nsd32dis; 279 Bitfield<13> cp13; 280 Bitfield<12> cp12; 281 Bitfield<11> cp11; 282 Bitfield<10> cp10; 283 Bitfield<9> cp9; 284 Bitfield<8> cp8; 285 Bitfield<7> cp7; 286 Bitfield<6> cp6; 287 Bitfield<5> cp5; 288 Bitfield<4> cp4; 289 Bitfield<3> cp3; 290 Bitfield<2> cp2; 291 Bitfield<1> cp1; 292 Bitfield<0> cp0; 293 EndBitUnion(NSACR) 294 295 BitUnion32(SCR) 296 Bitfield<13> twe; 297 Bitfield<12> twi; 298 Bitfield<11> st; // AArch64 299 Bitfield<10> rw; // AArch64 300 Bitfield<9> sif; 301 Bitfield<8> hce; 302 Bitfield<7> scd; 303 Bitfield<7> smd; // AArch64 304 Bitfield<6> nEt; 305 Bitfield<5> aw; 306 Bitfield<4> fw; 307 Bitfield<3> ea; 308 Bitfield<2> fiq; 309 Bitfield<1> irq; 310 Bitfield<0> ns; 311 EndBitUnion(SCR) 312 313 BitUnion32(SCTLR) 314 Bitfield<30> te; // Thumb Exception Enable (AArch32 only) 315 Bitfield<29> afe; // Access flag enable (AArch32 only) 316 Bitfield<28> tre; // TEX remap enable (AArch32 only) 317 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only) 318 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC, 319 // DC CVAC and IC IVAU instructions 320 // (AArch64 SCTLR_EL1 only) 321 Bitfield<25> ee; // Exception Endianness 322 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only) 323 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 324 // (AArch64 SCTLR_EL1 only) 325 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) 326 Bitfield<22> u; // Alignment (dropped in ARMv7) 327 Bitfield<21> fi; // Fast interrupts configuration enable 328 // (ARMv7 only) 329 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN 330 // (AArch32 only) 331 Bitfield<19> dz; // Divide by Zero fault enable 332 // (dropped in ARMv7) 333 Bitfield<19> wxn; // Write permission implies XN 334 Bitfield<18> ntwe; // Not trap WFE 335 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 336 Bitfield<18> rao2; // Read as one 337 Bitfield<16> ntwi; // Not trap WFI 338 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 339 Bitfield<16> rao3; // Read as one 340 Bitfield<15> uct; // Enable EL0 access to CTR_EL0 341 // (AArch64 SCTLR_EL1 only) 342 Bitfield<14> rr; // Round Robin select (ARMv7 only) 343 Bitfield<14> dze; // Enable EL0 access to DC ZVA 344 // (AArch64 SCTLR_EL1 only) 345 Bitfield<13> v; // Vectors bit (AArch32 only) 346 Bitfield<12> i; // Instruction cache enable 347 Bitfield<11> z; // Branch prediction enable (ARMv7 only) 348 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only) 349 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7) 350 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only) 351 Bitfield<8> sed; // SETEND disable 352 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 353 Bitfield<7> b; // Endianness support (dropped in ARMv7) 354 Bitfield<7> itd; // IT disable 355 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 356 Bitfield<6, 3> rao4; // Read as one 357 Bitfield<6> thee; // ThumbEE enable 358 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 359 Bitfield<5> cp15ben; // CP15 barrier enable 360 // (AArch32 and AArch64 SCTLR_EL1 only) 361 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0 362 // (AArch64 SCTLR_EL1 only) 363 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only) 364 Bitfield<2> c; // Cache enable 365 Bitfield<1> a; // Alignment check enable 366 Bitfield<0> m; // MMU enable 367 EndBitUnion(SCTLR) 368 369 BitUnion32(CPACR) 370 Bitfield<1, 0> cp0; 371 Bitfield<3, 2> cp1; 372 Bitfield<5, 4> cp2; 373 Bitfield<7, 6> cp3; 374 Bitfield<9, 8> cp4; 375 Bitfield<11, 10> cp5; 376 Bitfield<13, 12> cp6; 377 Bitfield<15, 14> cp7; 378 Bitfield<17, 16> cp8; 379 Bitfield<19, 18> cp9; 380 Bitfield<21, 20> cp10; 381 Bitfield<21, 20> fpen; // AArch64 382 Bitfield<23, 22> cp11; 383 Bitfield<25, 24> cp12; 384 Bitfield<27, 26> cp13; 385 Bitfield<29, 28> rsvd; 386 Bitfield<28> tta; // AArch64 387 Bitfield<30> d32dis; 388 Bitfield<31> asedis; 389 EndBitUnion(CPACR) 390 391 BitUnion32(FSR) 392 Bitfield<3, 0> fsLow; 393 Bitfield<5, 0> status; // LPAE 394 Bitfield<7, 4> domain; 395 Bitfield<9> lpae; 396 Bitfield<10> fsHigh; 397 Bitfield<11> wnr; 398 Bitfield<12> ext; 399 Bitfield<13> cm; // LPAE 400 EndBitUnion(FSR) 401 402 BitUnion32(FPSCR) 403 Bitfield<0> ioc; 404 Bitfield<1> dzc; 405 Bitfield<2> ofc; 406 Bitfield<3> ufc; 407 Bitfield<4> ixc; 408 Bitfield<7> idc; 409 Bitfield<8> ioe; 410 Bitfield<9> dze; 411 Bitfield<10> ofe; 412 Bitfield<11> ufe; 413 Bitfield<12> ixe; 414 Bitfield<15> ide; 415 Bitfield<18, 16> len; 416 Bitfield<19> fz16; 417 Bitfield<21, 20> stride; 418 Bitfield<23, 22> rMode; 419 Bitfield<24> fz; 420 Bitfield<25> dn; 421 Bitfield<26> ahp; 422 Bitfield<27> qc; 423 Bitfield<28> v; 424 Bitfield<29> c; 425 Bitfield<30> z; 426 Bitfield<31> n; 427 EndBitUnion(FPSCR) 428 429 BitUnion32(FPEXC) 430 Bitfield<31> ex; 431 Bitfield<30> en; 432 Bitfield<29, 0> subArchDefined; 433 EndBitUnion(FPEXC) 434 435 BitUnion32(MVFR0) 436 Bitfield<3, 0> advSimdRegisters; 437 Bitfield<7, 4> singlePrecision; 438 Bitfield<11, 8> doublePrecision; 439 Bitfield<15, 12> vfpExceptionTrapping; 440 Bitfield<19, 16> divide; 441 Bitfield<23, 20> squareRoot; 442 Bitfield<27, 24> shortVectors; 443 Bitfield<31, 28> roundingModes; 444 EndBitUnion(MVFR0) 445 446 BitUnion32(MVFR1) 447 Bitfield<3, 0> flushToZero; 448 Bitfield<7, 4> defaultNaN; 449 Bitfield<11, 8> advSimdLoadStore; 450 Bitfield<15, 12> advSimdInteger; 451 Bitfield<19, 16> advSimdSinglePrecision; 452 Bitfield<23, 20> advSimdHalfPrecision; 453 Bitfield<27, 24> vfpHalfPrecision; 454 Bitfield<31, 28> raz; 455 EndBitUnion(MVFR1) 456 457 BitUnion64(TTBCR) 458 // Short-descriptor translation table format 459 Bitfield<2, 0> n; 460 Bitfield<4> pd0; 461 Bitfield<5> pd1; 462 // Long-descriptor translation table format 463 Bitfield<2, 0> t0sz; 464 Bitfield<7> epd0; 465 Bitfield<9, 8> irgn0; 466 Bitfield<11, 10> orgn0; 467 Bitfield<13, 12> sh0; 468 Bitfield<14> tg0; 469 Bitfield<18, 16> t1sz; 470 Bitfield<22> a1; 471 Bitfield<23> epd1; 472 Bitfield<25, 24> irgn1; 473 Bitfield<27, 26> orgn1; 474 Bitfield<29, 28> sh1; 475 Bitfield<30> tg1; 476 Bitfield<34, 32> ips; 477 Bitfield<36> as; 478 Bitfield<37> tbi0; 479 Bitfield<38> tbi1; 480 // Common 481 Bitfield<31> eae; 482 // TCR_EL2/3 (AArch64) 483 Bitfield<18, 16> ps; 484 Bitfield<20> tbi; 485 EndBitUnion(TTBCR) 486 487 // Fields of TCR_EL{1,2,3} (mostly overlapping) 488 // TCR_EL1 is natively 64 bits, the others are 32 bits 489 BitUnion64(TCR) 490 Bitfield<5, 0> t0sz; 491 Bitfield<7> epd0; // EL1 492 Bitfield<9, 8> irgn0; 493 Bitfield<11, 10> orgn0; 494 Bitfield<13, 12> sh0; 495 Bitfield<15, 14> tg0; 496 Bitfield<18, 16> ps; 497 Bitfield<20> tbi; // EL2/EL3 498 Bitfield<21, 16> t1sz; // EL1 499 Bitfield<22> a1; // EL1 500 Bitfield<23> epd1; // EL1 501 Bitfield<25, 24> irgn1; // EL1 502 Bitfield<27, 26> orgn1; // EL1 503 Bitfield<29, 28> sh1; // EL1 504 Bitfield<31, 30> tg1; // EL1 505 Bitfield<34, 32> ips; // EL1 506 Bitfield<36> as; // EL1 507 Bitfield<37> tbi0; // EL1 508 Bitfield<38> tbi1; // EL1 509 EndBitUnion(TCR) 510 511 BitUnion32(HTCR) 512 Bitfield<2, 0> t0sz; 513 Bitfield<9, 8> irgn0; 514 Bitfield<11, 10> orgn0; 515 Bitfield<13, 12> sh0; 516 EndBitUnion(HTCR) 517 518 BitUnion32(VTCR_t) 519 Bitfield<3, 0> t0sz; 520 Bitfield<4> s; 521 Bitfield<5, 0> t0sz64; 522 Bitfield<7, 6> sl0; 523 Bitfield<9, 8> irgn0; 524 Bitfield<11, 10> orgn0; 525 Bitfield<13, 12> sh0; 526 Bitfield<15, 14> tg0; 527 Bitfield<18, 16> ps; // Only defined for VTCR_EL2 528 EndBitUnion(VTCR_t) 529 530 BitUnion32(PRRR) 531 Bitfield<1,0> tr0; 532 Bitfield<3,2> tr1; 533 Bitfield<5,4> tr2; 534 Bitfield<7,6> tr3; 535 Bitfield<9,8> tr4; 536 Bitfield<11,10> tr5; 537 Bitfield<13,12> tr6; 538 Bitfield<15,14> tr7; 539 Bitfield<16> ds0; 540 Bitfield<17> ds1; 541 Bitfield<18> ns0; 542 Bitfield<19> ns1; 543 Bitfield<24> nos0; 544 Bitfield<25> nos1; 545 Bitfield<26> nos2; 546 Bitfield<27> nos3; 547 Bitfield<28> nos4; 548 Bitfield<29> nos5; 549 Bitfield<30> nos6; 550 Bitfield<31> nos7; 551 EndBitUnion(PRRR) 552 553 BitUnion32(NMRR) 554 Bitfield<1,0> ir0; 555 Bitfield<3,2> ir1; 556 Bitfield<5,4> ir2; 557 Bitfield<7,6> ir3; 558 Bitfield<9,8> ir4; 559 Bitfield<11,10> ir5; 560 Bitfield<13,12> ir6; 561 Bitfield<15,14> ir7; 562 Bitfield<17,16> or0; 563 Bitfield<19,18> or1; 564 Bitfield<21,20> or2; 565 Bitfield<23,22> or3; 566 Bitfield<25,24> or4; 567 Bitfield<27,26> or5; 568 Bitfield<29,28> or6; 569 Bitfield<31,30> or7; 570 EndBitUnion(NMRR) 571 572 BitUnion32(CONTEXTIDR) 573 Bitfield<7,0> asid; 574 Bitfield<31,8> procid; 575 EndBitUnion(CONTEXTIDR) 576 577 BitUnion32(L2CTLR) 578 Bitfield<2,0> sataRAMLatency; 579 Bitfield<4,3> reserved_4_3; 580 Bitfield<5> dataRAMSetup; 581 Bitfield<8,6> tagRAMLatency; 582 Bitfield<9> tagRAMSetup; 583 Bitfield<11,10> dataRAMSlice; 584 Bitfield<12> tagRAMSlice; 585 Bitfield<20,13> reserved_20_13; 586 Bitfield<21> eccandParityEnable; 587 Bitfield<22> reserved_22; 588 Bitfield<23> interptCtrlPresent; 589 Bitfield<25,24> numCPUs; 590 Bitfield<30,26> reserved_30_26; 591 Bitfield<31> l2rstDISABLE_monitor; 592 EndBitUnion(L2CTLR) 593 594 BitUnion32(CTR) 595 Bitfield<3,0> iCacheLineSize; 596 Bitfield<13,4> raz_13_4; 597 Bitfield<15,14> l1IndexPolicy; 598 Bitfield<19,16> dCacheLineSize; 599 Bitfield<23,20> erg; 600 Bitfield<27,24> cwg; 601 Bitfield<28> raz_28; 602 Bitfield<31,29> format; 603 EndBitUnion(CTR) 604 605 BitUnion32(PMSELR) 606 Bitfield<4, 0> sel; 607 EndBitUnion(PMSELR) 608 609 BitUnion64(PAR) 610 // 64-bit format 611 Bitfield<63, 56> attr; 612 Bitfield<39, 12> pa; 613 Bitfield<11> lpae; 614 Bitfield<9> ns; 615 Bitfield<8, 7> sh; 616 Bitfield<0> f; 617 EndBitUnion(PAR) 618 619 BitUnion32(ESR) 620 Bitfield<31, 26> ec; 621 Bitfield<25> il; 622 Bitfield<15, 0> imm16; 623 EndBitUnion(ESR) 624 625 BitUnion32(CPTR) 626 Bitfield<31> tcpac; 627 Bitfield<20> tta; 628 Bitfield<13, 12> res1_13_12_el2; 629 Bitfield<10> tfp; 630 Bitfield<9, 0> res1_9_0_el2; 631 EndBitUnion(CPTR) 632 633} 634 635#endif // __ARCH_ARM_MISCREGS_TYPES_HH__ 636