misc.isa revision 7261
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40def template MrsDeclare {{ 41class %(class_name)s : public %(base_class)s 42{ 43 protected: 44 public: 45 // Constructor 46 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 47 %(BasicExecDeclare)s 48}; 49}}; 50 51def template MrsConstructor {{ 52 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 53 IntRegIndex _dest) 54 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 55 { 56 %(constructor)s; 57 } 58}}; 59 60def template MsrRegDeclare {{ 61class %(class_name)s : public %(base_class)s 62{ 63 protected: 64 public: 65 // Constructor 66 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 67 %(BasicExecDeclare)s 68}; 69}}; 70 71def template MsrRegConstructor {{ 72 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 73 IntRegIndex _op1, 74 uint8_t mask) 75 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 76 { 77 %(constructor)s; 78 } 79}}; 80 81def template MsrImmDeclare {{ 82class %(class_name)s : public %(base_class)s 83{ 84 protected: 85 public: 86 // Constructor 87 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 88 %(BasicExecDeclare)s 89}; 90}}; 91 92def template MsrImmConstructor {{ 93 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 94 uint32_t imm, 95 uint8_t mask) 96 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 97 { 98 %(constructor)s; 99 } 100}}; 101 102def template RegRegOpDeclare {{ 103class %(class_name)s : public %(base_class)s 104{ 105 protected: 106 public: 107 // Constructor 108 %(class_name)s(ExtMachInst machInst, 109 IntRegIndex _dest, IntRegIndex _op1); 110 %(BasicExecDeclare)s 111}; 112}}; 113 114def template RegRegOpConstructor {{ 115 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 116 IntRegIndex _dest, IntRegIndex _op1) 117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 118 { 119 %(constructor)s; 120 } 121}}; 122 123def template RegRegRegImmOpDeclare {{ 124class %(class_name)s : public %(base_class)s 125{ 126 protected: 127 public: 128 // Constructor 129 %(class_name)s(ExtMachInst machInst, 130 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 131 uint32_t _imm); 132 %(BasicExecDeclare)s 133}; 134}}; 135 136def template RegRegRegImmOpConstructor {{ 137 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 138 IntRegIndex _dest, 139 IntRegIndex _op1, 140 IntRegIndex _op2, 141 uint32_t _imm) 142 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 143 _dest, _op1, _op2, _imm) 144 { 145 %(constructor)s; 146 } 147}}; 148 149def template RegRegRegRegOpDeclare {{ 150class %(class_name)s : public %(base_class)s 151{ 152 protected: 153 public: 154 // Constructor 155 %(class_name)s(ExtMachInst machInst, 156 IntRegIndex _dest, IntRegIndex _op1, 157 IntRegIndex _op2, IntRegIndex _op3); 158 %(BasicExecDeclare)s 159}; 160}}; 161 162def template RegRegRegRegOpConstructor {{ 163 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 164 IntRegIndex _dest, 165 IntRegIndex _op1, 166 IntRegIndex _op2, 167 IntRegIndex _op3) 168 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 169 _dest, _op1, _op2, _op3) 170 { 171 %(constructor)s; 172 } 173}}; 174 175def template RegRegRegOpDeclare {{ 176class %(class_name)s : public %(base_class)s 177{ 178 protected: 179 public: 180 // Constructor 181 %(class_name)s(ExtMachInst machInst, 182 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); 183 %(BasicExecDeclare)s 184}; 185}}; 186 187def template RegRegRegOpConstructor {{ 188 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 189 IntRegIndex _dest, 190 IntRegIndex _op1, 191 IntRegIndex _op2) 192 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 193 _dest, _op1, _op2) 194 { 195 %(constructor)s; 196 } 197}}; 198 199def template RegRegImmImmOpDeclare {{ 200class %(class_name)s : public %(base_class)s 201{ 202 protected: 203 public: 204 // Constructor 205 %(class_name)s(ExtMachInst machInst, 206 IntRegIndex _dest, IntRegIndex _op1, 207 uint32_t _imm1, uint32_t _imm2); 208 %(BasicExecDeclare)s 209}; 210}}; 211 212def template RegRegImmImmOpConstructor {{ 213 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 214 IntRegIndex _dest, 215 IntRegIndex _op1, 216 uint32_t _imm1, 217 uint32_t _imm2) 218 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 219 _dest, _op1, _imm1, _imm2) 220 { 221 %(constructor)s; 222 } 223}}; 224 225def template RegImmRegOpDeclare {{ 226class %(class_name)s : public %(base_class)s 227{ 228 protected: 229 public: 230 // Constructor 231 %(class_name)s(ExtMachInst machInst, 232 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1); 233 %(BasicExecDeclare)s 234}; 235}}; 236 237def template RegImmRegOpConstructor {{ 238 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 239 IntRegIndex _dest, 240 uint32_t _imm, 241 IntRegIndex _op1) 242 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 243 _dest, _imm, _op1) 244 { 245 %(constructor)s; 246 } 247}}; 248 249def template RegImmRegShiftOpDeclare {{ 250class %(class_name)s : public %(base_class)s 251{ 252 protected: 253 public: 254 // Constructor 255 %(class_name)s(ExtMachInst machInst, 256 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1, 257 int32_t _shiftAmt, ArmShiftType _shiftType); 258 %(BasicExecDeclare)s 259}; 260}}; 261 262def template RegImmRegShiftOpConstructor {{ 263 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 264 IntRegIndex _dest, 265 uint32_t _imm, 266 IntRegIndex _op1, 267 int32_t _shiftAmt, 268 ArmShiftType _shiftType) 269 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 270 _dest, _imm, _op1, _shiftAmt, _shiftType) 271 { 272 %(constructor)s; 273 } 274}}; 275