xref: /gem5/src/arch/arm/isa/templates/misc.isa

// -*- mode:c++ -*-

// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

def template MrsDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
        %(BasicExecDeclare)s
};
}};

def template MrsConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
    {
        %(constructor)s;
    }
}};

def template MsrRegDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
        %(BasicExecDeclare)s
};
}};

def template MsrRegConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _op1,
                                          uint8_t mask)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
    {
        %(constructor)s;
    }
}};

def template MsrImmDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
        %(BasicExecDeclare)s
};
}};

def template MsrImmConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          uint32_t imm,
                                          uint8_t mask)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
    {
        %(constructor)s;
    }
}};

def template ImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, uint64_t _imm);
        %(BasicExecDeclare)s
};
}};

def template ImmOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
    {
        %(constructor)s;
    }
}};

def template RegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
        %(BasicExecDeclare)s
};
}};

def template RegImmOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
            IntRegIndex _dest, uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
    {
        %(constructor)s;
    }
}};

def template RegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1);
        %(BasicExecDeclare)s
};
}};

def template RegRegOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest, IntRegIndex _op1)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
    {
        %(constructor)s;
    }
}};

def template RegRegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
                       uint64_t _imm);
        %(BasicExecDeclare)s
};
}};

def template RegRegRegImmOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _imm)
    {
        %(constructor)s;
    }
}};

def template RegRegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       IntRegIndex _op2, IntRegIndex _op3);
        %(BasicExecDeclare)s
};
}};

def template RegRegRegRegOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2,
                                          IntRegIndex _op3)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2, _op3)
    {
        %(constructor)s;
    }
}};

def template RegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
        %(BasicExecDeclare)s
};
}};

def template RegRegRegOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          IntRegIndex _op2)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _op2)
    {
        %(constructor)s;
    }
}};

def template RegRegImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm);
        %(BasicExecDeclare)s
};
}};

def template RegRegImmOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          uint64_t _imm)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm)
    {
        %(constructor)s;
    }
}};

def template RegRegImmImmOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, IntRegIndex _op1,
                       uint64_t _imm1, uint64_t _imm2);
        %(BasicExecDeclare)s
};
}};

def template RegRegImmImmOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          IntRegIndex _op1,
                                          uint64_t _imm1,
                                          uint64_t _imm2)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _op1, _imm1, _imm2)
    {
        %(constructor)s;
    }
}};

def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
        %(BasicExecDeclare)s
};
}};

def template RegImmRegOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          uint64_t _imm,
                                          IntRegIndex _op1)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _imm, _op1)
    {
        %(constructor)s;
    }
}};

def template RegImmRegShiftOpDeclare {{
class %(class_name)s : public %(base_class)s
{
  protected:
    public:
        // Constructor
        %(class_name)s(ExtMachInst machInst,
                       IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
                       int32_t _shiftAmt, ArmShiftType _shiftType);
        %(BasicExecDeclare)s
};
}};

def template RegImmRegShiftOpConstructor {{
    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
                                          IntRegIndex _dest,
                                          uint64_t _imm,
                                          IntRegIndex _op1,
                                          int32_t _shiftAmt,
                                          ArmShiftType _shiftType)
        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
                         _dest, _imm, _op1, _shiftAmt, _shiftType)
    {
        %(constructor)s;
    }
}};

def template ClrexDeclare {{
    /**
     * Static instruction class for "%(mnemonic)s".
     */
    class %(class_name)s : public %(base_class)s
    {
      public:

        /// Constructor.
        %(class_name)s(ExtMachInst machInst);

        %(BasicExecDeclare)s

        %(InitiateAccDeclare)s

        %(CompleteAccDeclare)s
    };
}};

def template ClrexInitiateAcc {{
    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;
        %(op_decl)s;
        %(op_rd)s;

        if (%(predicate_test)s)
        {
            if (fault == NoFault) {
                unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
                fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
            }
        } else {
            xc->setPredicate(false);
            if (fault == NoFault && machInst.itstateMask != 0) {
                xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
            }
        }

        return fault;
    }
}};

def template ClrexCompleteAcc {{
    Fault %(class_name)s::completeAcc(PacketPtr pkt,
                                      %(CPU_exec_context)s *xc,
                                      Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(op_decl)s;
        %(op_rd)s;


        if (fault == NoFault && machInst.itstateMask != 0) {
            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
        }

        return fault;
    }
}};