misc.isa revision 7233
16019SN/A// -*- mode:c++ -*- 27649Sminkyu.jeong@arm.com 37649Sminkyu.jeong@arm.com// Copyright (c) 2010 ARM Limited 47649Sminkyu.jeong@arm.com// All rights reserved 57649Sminkyu.jeong@arm.com// 67649Sminkyu.jeong@arm.com// The license below extends only to copyright in the software and shall 77649Sminkyu.jeong@arm.com// not be construed as granting a license to any other intellectual 87649Sminkyu.jeong@arm.com// property including but not limited to intellectual property relating 97649Sminkyu.jeong@arm.com// to a hardware implementation of the functionality of the software 107649Sminkyu.jeong@arm.com// licensed hereunder. You may use the software subject to the license 117649Sminkyu.jeong@arm.com// terms below provided that you ensure that this notice is replicated 127649Sminkyu.jeong@arm.com// unmodified and in its entirety in all distributions of the software, 137649Sminkyu.jeong@arm.com// modified or unmodified, in source code or in binary form. 146019SN/A// 156019SN/A// Redistribution and use in source and binary forms, with or without 166019SN/A// modification, are permitted provided that the following conditions are 176019SN/A// met: redistributions of source code must retain the above copyright 186019SN/A// notice, this list of conditions and the following disclaimer; 196019SN/A// redistributions in binary form must reproduce the above copyright 206019SN/A// notice, this list of conditions and the following disclaimer in the 216019SN/A// documentation and/or other materials provided with the distribution; 226019SN/A// neither the name of the copyright holders nor the names of its 236019SN/A// contributors may be used to endorse or promote products derived from 246019SN/A// this software without specific prior written permission. 256019SN/A// 266019SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 276019SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 286019SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 296019SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 306019SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 316019SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 326019SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 336019SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 346019SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 356019SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 366019SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 376019SN/A// 386019SN/A// Authors: Gabe Black 396019SN/A 406019SN/Adef template MrsDeclare {{ 416019SN/Aclass %(class_name)s : public %(base_class)s 426019SN/A{ 436329Sgblack@eecs.umich.edu protected: 446329Sgblack@eecs.umich.edu public: 456019SN/A // Constructor 468961Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 478229Snate@binkert.org %(BasicExecDeclare)s 486329Sgblack@eecs.umich.edu}; 496328SN/A}}; 506329Sgblack@eecs.umich.edu 516328SN/Adef template MrsConstructor {{ 527848SAli.Saidi@ARM.com inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 537848SAli.Saidi@ARM.com IntRegIndex _dest) 547848SAli.Saidi@ARM.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 557848SAli.Saidi@ARM.com { 567848SAli.Saidi@ARM.com %(constructor)s; 576329Sgblack@eecs.umich.edu } 586328SN/A}}; 597310Sgblack@eecs.umich.edu 606328SN/Adef template MsrRegDeclare {{ 616329Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 626328SN/A{ 636329Sgblack@eecs.umich.edu protected: 646329Sgblack@eecs.umich.edu public: 656329Sgblack@eecs.umich.edu // Constructor 666328SN/A %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 676329Sgblack@eecs.umich.edu %(BasicExecDeclare)s 686329Sgblack@eecs.umich.edu}; 696328SN/A}}; 706329Sgblack@eecs.umich.edu 716717Sgblack@eecs.umich.edudef template MsrRegConstructor {{ 727177Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 737177Sgblack@eecs.umich.edu IntRegIndex _op1, 747592SAli.Saidi@ARM.com uint8_t mask) 756328SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 766717Sgblack@eecs.umich.edu { 776329Sgblack@eecs.umich.edu %(constructor)s; 786329Sgblack@eecs.umich.edu } 796328SN/A}}; 807649Sminkyu.jeong@arm.com 816328SN/Adef template MsrImmDeclare {{ 826329Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 836329Sgblack@eecs.umich.edu{ 846329Sgblack@eecs.umich.edu protected: 856329Sgblack@eecs.umich.edu public: 867650SAli.Saidi@ARM.com // Constructor 876329Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 886329Sgblack@eecs.umich.edu %(BasicExecDeclare)s 896329Sgblack@eecs.umich.edu}; 906329Sgblack@eecs.umich.edu}}; 916329Sgblack@eecs.umich.edu 926717Sgblack@eecs.umich.edudef template MsrImmConstructor {{ 936717Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 946717Sgblack@eecs.umich.edu uint32_t imm, 956328SN/A uint8_t mask) 966717Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 976328SN/A { 986329Sgblack@eecs.umich.edu %(constructor)s; 996329Sgblack@eecs.umich.edu } 1006329Sgblack@eecs.umich.edu}}; 1016328SN/A 1026329Sgblack@eecs.umich.edudef template RevOpDeclare {{ 1037498Sgblack@eecs.umich.educlass %(class_name)s : public %(base_class)s 1046329Sgblack@eecs.umich.edu{ 1057649Sminkyu.jeong@arm.com protected: 1066329Sgblack@eecs.umich.edu public: 1076329Sgblack@eecs.umich.edu // Constructor 1086329Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 1096329Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1); 1106329Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1116329Sgblack@eecs.umich.edu}; 1126329Sgblack@eecs.umich.edu}}; 1136328SN/A 1146019SN/Adef template RevOpConstructor {{ 1156019SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 116 IntRegIndex _dest, IntRegIndex _op1) 117 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 118 { 119 %(constructor)s; 120 } 121}}; 122 123def template RegRegRegImmOpDeclare {{ 124class %(class_name)s : public %(base_class)s 125{ 126 protected: 127 public: 128 // Constructor 129 %(class_name)s(ExtMachInst machInst, 130 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 131 uint32_t _imm); 132 %(BasicExecDeclare)s 133}; 134}}; 135 136def template RegRegRegImmOpConstructor {{ 137 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 138 IntRegIndex _dest, 139 IntRegIndex _op1, 140 IntRegIndex _op2, 141 uint32_t _imm) 142 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 143 _dest, _op1, _op2, _imm) 144 { 145 %(constructor)s; 146 } 147}}; 148 149def template RegImmRegOpDeclare {{ 150class %(class_name)s : public %(base_class)s 151{ 152 protected: 153 public: 154 // Constructor 155 %(class_name)s(ExtMachInst machInst, 156 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1); 157 %(BasicExecDeclare)s 158}; 159}}; 160 161def template RegImmRegOpConstructor {{ 162 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 163 IntRegIndex _dest, 164 uint32_t _imm, 165 IntRegIndex _op1) 166 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 167 _dest, _imm, _op1) 168 { 169 %(constructor)s; 170 } 171}}; 172 173def template RegImmRegShiftOpDeclare {{ 174class %(class_name)s : public %(base_class)s 175{ 176 protected: 177 public: 178 // Constructor 179 %(class_name)s(ExtMachInst machInst, 180 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1, 181 int32_t _shiftAmt, ArmShiftType _shiftType); 182 %(BasicExecDeclare)s 183}; 184}}; 185 186def template RegImmRegShiftOpConstructor {{ 187 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, 188 IntRegIndex _dest, 189 uint32_t _imm, 190 IntRegIndex _op1, 191 int32_t _shiftAmt, 192 ArmShiftType _shiftType) 193 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 194 _dest, _imm, _op1, _shiftAmt, _shiftType) 195 { 196 %(constructor)s; 197 } 198}}; 199