misc.isa revision 10420
12SN/A// -*- mode:c++ -*- 29952Sdam.sunwoo@arm.com 39952Sdam.sunwoo@arm.com// Copyright (c) 2010-2013 ARM Limited 49952Sdam.sunwoo@arm.com// All rights reserved 59952Sdam.sunwoo@arm.com// 69952Sdam.sunwoo@arm.com// The license below extends only to copyright in the software and shall 79952Sdam.sunwoo@arm.com// not be construed as granting a license to any other intellectual 89952Sdam.sunwoo@arm.com// property including but not limited to intellectual property relating 99952Sdam.sunwoo@arm.com// to a hardware implementation of the functionality of the software 109952Sdam.sunwoo@arm.com// licensed hereunder. You may use the software subject to the license 119952Sdam.sunwoo@arm.com// terms below provided that you ensure that this notice is replicated 129952Sdam.sunwoo@arm.com// unmodified and in its entirety in all distributions of the software, 139952Sdam.sunwoo@arm.com// modified or unmodified, in source code or in binary form. 141762SN/A// 159983Sstever@gmail.com// Redistribution and use in source and binary forms, with or without 169983Sstever@gmail.com// modification, are permitted provided that the following conditions are 172SN/A// met: redistributions of source code must retain the above copyright 182SN/A// notice, this list of conditions and the following disclaimer; 192SN/A// redistributions in binary form must reproduce the above copyright 202SN/A// notice, this list of conditions and the following disclaimer in the 212SN/A// documentation and/or other materials provided with the distribution; 222SN/A// neither the name of the copyright holders nor the names of its 232SN/A// contributors may be used to endorse or promote products derived from 242SN/A// this software without specific prior written permission. 252SN/A// 262SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372SN/A// 382SN/A// Authors: Gabe Black 392SN/A 402SN/Adef template MrsDeclare {{ 412665Ssaidi@eecs.umich.educlass %(class_name)s : public %(base_class)s 422665Ssaidi@eecs.umich.edu{ 432SN/A protected: 442SN/A public: 451798SN/A // Constructor 461798SN/A %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); 472SN/A %(BasicExecDeclare)s 489983Sstever@gmail.com}; 499952Sdam.sunwoo@arm.com}}; 502SN/A 512SN/Adef template MrsConstructor {{ 522SN/A %(class_name)s::%(class_name)s(ExtMachInst machInst, 532SN/A IntRegIndex _dest) 549983Sstever@gmail.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) 552SN/A { 565606Snate@binkert.org %(constructor)s; 572SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 582SN/A for (int x = 0; x < _numDestRegs; x++) { 592SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 603144Shsul@eecs.umich.edu } 612SN/A } 622SN/A } 639952Sdam.sunwoo@arm.com}}; 649983Sstever@gmail.com 659983Sstever@gmail.comdef template MrsBankedRegDeclare {{ 6611070Sandreas.sandberg@arm.comclass %(class_name)s : public %(base_class)s 672SN/A{ 689983Sstever@gmail.com protected: 699983Sstever@gmail.com uint8_t byteMask; 709983Sstever@gmail.com bool r; 719983Sstever@gmail.com 729983Sstever@gmail.com public: 739983Sstever@gmail.com // Constructor 749983Sstever@gmail.com %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, 759983Sstever@gmail.com uint8_t _sysM, bool _r); 769983Sstever@gmail.com %(BasicExecDeclare)s 779983Sstever@gmail.com}; 789983Sstever@gmail.com}}; 799983Sstever@gmail.com 809983Sstever@gmail.comdef template MrsBankedRegConstructor {{ 819983Sstever@gmail.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 829983Sstever@gmail.com IntRegIndex _dest, 839983Sstever@gmail.com uint8_t _sysM, 849983Sstever@gmail.com bool _r) 859983Sstever@gmail.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest), 8611070Sandreas.sandberg@arm.com byteMask(_sysM), r(_r) 879983Sstever@gmail.com { 889983Sstever@gmail.com %(constructor)s; 899983Sstever@gmail.com if (!(condCode == COND_AL || condCode == COND_UC)) { 902SN/A for (int x = 0; x < _numDestRegs; x++) { 915543Ssaidi@eecs.umich.edu _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 922SN/A } 935336Shines@cs.fsu.edu } 949952Sdam.sunwoo@arm.com } 9510905Sandreas.sandberg@arm.com}}; 9610905Sandreas.sandberg@arm.com 9710905Sandreas.sandberg@arm.comdef template MsrBankedRegDeclare {{ 989952Sdam.sunwoo@arm.comclass %(class_name)s : public %(base_class)s 992SN/A{ 1002SN/A protected: 1017821Ssteve.reinhardt@amd.com bool r; 1022797Sktlim@umich.edu 1032797Sktlim@umich.edu public: 1042839Sktlim@umich.edu // Constructor 1052797Sktlim@umich.edu %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 1065606Snate@binkert.org uint8_t _sysM, bool _r); 1072797Sktlim@umich.edu %(BasicExecDeclare)s 1085606Snate@binkert.org}; 1095606Snate@binkert.org}}; 1102797Sktlim@umich.edu 1112797Sktlim@umich.edudef template MsrBankedRegConstructor {{ 1122797Sktlim@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst, 1132797Sktlim@umich.edu IntRegIndex _op1, 1149983Sstever@gmail.com uint8_t _sysM, 1152797Sktlim@umich.edu bool _r) 1162797Sktlim@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM), 1172SN/A r(_r) 1182SN/A { 1192SN/A %(constructor)s; 1202SN/A if (!(condCode == COND_AL || condCode == COND_UC)) { 1212SN/A for (int x = 0; x < _numDestRegs; x++) { 1222SN/A _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 1232SN/A } 1242SN/A } 1255543Ssaidi@eecs.umich.edu } 1265543Ssaidi@eecs.umich.edu}}; 1272SN/A 1282SN/Adef template MsrRegDeclare {{ 1295606Snate@binkert.orgclass %(class_name)s : public %(base_class)s 1302SN/A{ 1315543Ssaidi@eecs.umich.edu protected: 1322SN/A public: 1335336Shines@cs.fsu.edu // Constructor 1342SN/A %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); 1352SN/A %(BasicExecDeclare)s 1362SN/A}; 1371798SN/A}}; 138 139def template MsrRegConstructor {{ 140 %(class_name)s::%(class_name)s(ExtMachInst machInst, 141 IntRegIndex _op1, 142 uint8_t mask) 143 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) 144 { 145 %(constructor)s; 146 if (!(condCode == COND_AL || condCode == COND_UC)) { 147 for (int x = 0; x < _numDestRegs; x++) { 148 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 149 } 150 } 151 } 152}}; 153 154def template MsrImmDeclare {{ 155class %(class_name)s : public %(base_class)s 156{ 157 protected: 158 public: 159 // Constructor 160 %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); 161 %(BasicExecDeclare)s 162}; 163}}; 164 165def template MsrImmConstructor {{ 166 %(class_name)s::%(class_name)s(ExtMachInst machInst, 167 uint32_t imm, 168 uint8_t mask) 169 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) 170 { 171 %(constructor)s; 172 if (!(condCode == COND_AL || condCode == COND_UC)) { 173 for (int x = 0; x < _numDestRegs; x++) { 174 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 175 } 176 } 177 } 178}}; 179 180def template MrrcOpDeclare {{ 181class %(class_name)s : public %(base_class)s 182{ 183 protected: 184 public: 185 // Constructor 186 %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, 187 IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); 188 %(BasicExecDeclare)s 189}; 190}}; 191 192def template MrrcOpConstructor {{ 193 %(class_name)s::%(class_name)s(ExtMachInst machInst, 194 MiscRegIndex op1, 195 IntRegIndex dest, 196 IntRegIndex dest2, 197 uint32_t imm) 198 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest, 199 dest2, imm) 200 { 201 %(constructor)s; 202 if (!(condCode == COND_AL || condCode == COND_UC)) { 203 for (int x = 0; x < _numDestRegs; x++) { 204 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 205 } 206 } 207 } 208}}; 209 210def template McrrOpDeclare {{ 211class %(class_name)s : public %(base_class)s 212{ 213 protected: 214 public: 215 // Constructor 216 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, 217 MiscRegIndex _dest, uint32_t imm); 218 %(BasicExecDeclare)s 219}; 220}}; 221 222def template McrrOpConstructor {{ 223 %(class_name)s::%(class_name)s(ExtMachInst machInst, 224 IntRegIndex op1, 225 IntRegIndex op2, 226 MiscRegIndex dest, 227 uint32_t imm) 228 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2, 229 dest, imm) 230 { 231 %(constructor)s; 232 if (!(condCode == COND_AL || condCode == COND_UC)) { 233 for (int x = 0; x < _numDestRegs; x++) { 234 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 235 } 236 } 237 } 238}}; 239 240def template ImmOpDeclare {{ 241class %(class_name)s : public %(base_class)s 242{ 243 protected: 244 public: 245 // Constructor 246 %(class_name)s(ExtMachInst machInst, uint64_t _imm); 247 %(BasicExecDeclare)s 248}; 249}}; 250 251def template ImmOpConstructor {{ 252 %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) 253 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 254 { 255 %(constructor)s; 256 if (!(condCode == COND_AL || condCode == COND_UC)) { 257 for (int x = 0; x < _numDestRegs; x++) { 258 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 259 } 260 } 261 } 262}}; 263 264def template RegImmOpDeclare {{ 265class %(class_name)s : public %(base_class)s 266{ 267 protected: 268 public: 269 // Constructor 270 %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); 271 %(BasicExecDeclare)s 272}; 273}}; 274 275def template RegImmOpConstructor {{ 276 %(class_name)s::%(class_name)s(ExtMachInst machInst, 277 IntRegIndex _dest, uint64_t _imm) 278 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) 279 { 280 %(constructor)s; 281 if (!(condCode == COND_AL || condCode == COND_UC)) { 282 for (int x = 0; x < _numDestRegs; x++) { 283 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 284 } 285 } 286 } 287}}; 288 289def template RegRegOpDeclare {{ 290class %(class_name)s : public %(base_class)s 291{ 292 protected: 293 public: 294 // Constructor 295 %(class_name)s(ExtMachInst machInst, 296 IntRegIndex _dest, IntRegIndex _op1); 297 %(BasicExecDeclare)s 298}; 299}}; 300 301def template RegRegOpConstructor {{ 302 %(class_name)s::%(class_name)s(ExtMachInst machInst, 303 IntRegIndex _dest, IntRegIndex _op1) 304 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) 305 { 306 %(constructor)s; 307 if (!(condCode == COND_AL || condCode == COND_UC)) { 308 for (int x = 0; x < _numDestRegs; x++) { 309 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 310 } 311 } 312 } 313}}; 314 315def template RegRegRegImmOpDeclare {{ 316class %(class_name)s : public %(base_class)s 317{ 318 protected: 319 public: 320 // Constructor 321 %(class_name)s(ExtMachInst machInst, 322 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 323 uint64_t _imm); 324 %(BasicExecDeclare)s 325}; 326}}; 327 328def template RegRegRegImmOpConstructor {{ 329 %(class_name)s::%(class_name)s(ExtMachInst machInst, 330 IntRegIndex _dest, 331 IntRegIndex _op1, 332 IntRegIndex _op2, 333 uint64_t _imm) 334 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 335 _dest, _op1, _op2, _imm) 336 { 337 %(constructor)s; 338 if (!(condCode == COND_AL || condCode == COND_UC)) { 339 for (int x = 0; x < _numDestRegs; x++) { 340 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 341 } 342 } 343 } 344}}; 345 346def template RegRegRegRegOpDeclare {{ 347class %(class_name)s : public %(base_class)s 348{ 349 protected: 350 public: 351 // Constructor 352 %(class_name)s(ExtMachInst machInst, 353 IntRegIndex _dest, IntRegIndex _op1, 354 IntRegIndex _op2, IntRegIndex _op3); 355 %(BasicExecDeclare)s 356}; 357}}; 358 359def template RegRegRegRegOpConstructor {{ 360 %(class_name)s::%(class_name)s(ExtMachInst machInst, 361 IntRegIndex _dest, 362 IntRegIndex _op1, 363 IntRegIndex _op2, 364 IntRegIndex _op3) 365 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 366 _dest, _op1, _op2, _op3) 367 { 368 %(constructor)s; 369 if (!(condCode == COND_AL || condCode == COND_UC)) { 370 for (int x = 0; x < _numDestRegs; x++) { 371 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 372 } 373 } 374 } 375}}; 376 377def template RegRegRegOpDeclare {{ 378class %(class_name)s : public %(base_class)s 379{ 380 protected: 381 public: 382 // Constructor 383 %(class_name)s(ExtMachInst machInst, 384 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); 385 %(BasicExecDeclare)s 386}; 387}}; 388 389def template RegRegRegOpConstructor {{ 390 %(class_name)s::%(class_name)s(ExtMachInst machInst, 391 IntRegIndex _dest, 392 IntRegIndex _op1, 393 IntRegIndex _op2) 394 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 395 _dest, _op1, _op2) 396 { 397 %(constructor)s; 398 if (!(condCode == COND_AL || condCode == COND_UC)) { 399 for (int x = 0; x < _numDestRegs; x++) { 400 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 401 } 402 } 403 } 404}}; 405 406def template RegRegImmOpDeclare {{ 407class %(class_name)s : public %(base_class)s 408{ 409 protected: 410 public: 411 // Constructor 412 %(class_name)s(ExtMachInst machInst, 413 IntRegIndex _dest, IntRegIndex _op1, 414 uint64_t _imm); 415 %(BasicExecDeclare)s 416}; 417}}; 418 419def template RegRegImmOpConstructor {{ 420 %(class_name)s::%(class_name)s(ExtMachInst machInst, 421 IntRegIndex _dest, 422 IntRegIndex _op1, 423 uint64_t _imm) 424 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 425 _dest, _op1, _imm) 426 { 427 %(constructor)s; 428 if (!(condCode == COND_AL || condCode == COND_UC)) { 429 for (int x = 0; x < _numDestRegs; x++) { 430 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 431 } 432 } 433 } 434}}; 435 436def template MiscRegRegImmOpDeclare {{ 437class %(class_name)s : public %(base_class)s 438{ 439 protected: 440 public: 441 // Constructor 442 %(class_name)s(ExtMachInst machInst, 443 MiscRegIndex _dest, IntRegIndex _op1, 444 uint64_t _imm); 445 %(BasicExecDeclare)s 446}; 447}}; 448 449def template MiscRegRegImmOpConstructor {{ 450 %(class_name)s::%(class_name)s(ExtMachInst machInst, 451 MiscRegIndex _dest, 452 IntRegIndex _op1, 453 uint64_t _imm) 454 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 455 _dest, _op1, _imm) 456 { 457 %(constructor)s; 458 if (!(condCode == COND_AL || condCode == COND_UC)) { 459 for (int x = 0; x < _numDestRegs; x++) { 460 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 461 } 462 } 463 } 464}}; 465 466def template RegMiscRegImmOpDeclare {{ 467class %(class_name)s : public %(base_class)s 468{ 469 protected: 470 public: 471 // Constructor 472 %(class_name)s(ExtMachInst machInst, 473 IntRegIndex _dest, MiscRegIndex _op1, 474 uint64_t _imm); 475 %(BasicExecDeclare)s 476}; 477}}; 478 479def template RegMiscRegImmOpConstructor {{ 480 %(class_name)s::%(class_name)s(ExtMachInst machInst, 481 IntRegIndex _dest, 482 MiscRegIndex _op1, 483 uint64_t _imm) 484 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 485 _dest, _op1, _imm) 486 { 487 %(constructor)s; 488 if (!(condCode == COND_AL || condCode == COND_UC)) { 489 for (int x = 0; x < _numDestRegs; x++) { 490 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 491 } 492 } 493 } 494}}; 495 496def template RegImmImmOpDeclare {{ 497class %(class_name)s : public %(base_class)s 498{ 499 protected: 500 public: 501 // Constructor 502 %(class_name)s(ExtMachInst machInst, 503 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); 504 %(BasicExecDeclare)s 505}; 506}}; 507 508def template RegImmImmOpConstructor {{ 509 %(class_name)s::%(class_name)s(ExtMachInst machInst, 510 IntRegIndex _dest, 511 uint64_t _imm1, 512 uint64_t _imm2) 513 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 514 _dest, _imm1, _imm2) 515 { 516 %(constructor)s; 517 if (!(condCode == COND_AL || condCode == COND_UC)) { 518 for (int x = 0; x < _numDestRegs; x++) { 519 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 520 } 521 } 522 } 523}}; 524 525def template RegRegImmImmOpDeclare {{ 526class %(class_name)s : public %(base_class)s 527{ 528 protected: 529 public: 530 // Constructor 531 %(class_name)s(ExtMachInst machInst, 532 IntRegIndex _dest, IntRegIndex _op1, 533 uint64_t _imm1, uint64_t _imm2); 534 %(BasicExecDeclare)s 535}; 536}}; 537 538def template RegRegImmImmOpConstructor {{ 539 %(class_name)s::%(class_name)s(ExtMachInst machInst, 540 IntRegIndex _dest, 541 IntRegIndex _op1, 542 uint64_t _imm1, 543 uint64_t _imm2) 544 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 545 _dest, _op1, _imm1, _imm2) 546 { 547 %(constructor)s; 548 if (!(condCode == COND_AL || condCode == COND_UC)) { 549 for (int x = 0; x < _numDestRegs; x++) { 550 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 551 } 552 } 553 } 554}}; 555 556def template RegImmRegOpDeclare {{ 557class %(class_name)s : public %(base_class)s 558{ 559 protected: 560 public: 561 // Constructor 562 %(class_name)s(ExtMachInst machInst, 563 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); 564 %(BasicExecDeclare)s 565}; 566}}; 567 568def template RegImmRegOpConstructor {{ 569 %(class_name)s::%(class_name)s(ExtMachInst machInst, 570 IntRegIndex _dest, 571 uint64_t _imm, 572 IntRegIndex _op1) 573 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 574 _dest, _imm, _op1) 575 { 576 %(constructor)s; 577 if (!(condCode == COND_AL || condCode == COND_UC)) { 578 for (int x = 0; x < _numDestRegs; x++) { 579 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 580 } 581 } 582 } 583}}; 584 585def template RegImmRegShiftOpDeclare {{ 586class %(class_name)s : public %(base_class)s 587{ 588 protected: 589 public: 590 // Constructor 591 %(class_name)s(ExtMachInst machInst, 592 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, 593 int32_t _shiftAmt, ArmShiftType _shiftType); 594 %(BasicExecDeclare)s 595}; 596}}; 597 598def template RegImmRegShiftOpConstructor {{ 599 %(class_name)s::%(class_name)s(ExtMachInst machInst, 600 IntRegIndex _dest, 601 uint64_t _imm, 602 IntRegIndex _op1, 603 int32_t _shiftAmt, 604 ArmShiftType _shiftType) 605 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 606 _dest, _imm, _op1, _shiftAmt, _shiftType) 607 { 608 %(constructor)s; 609 if (!(condCode == COND_AL || condCode == COND_UC)) { 610 for (int x = 0; x < _numDestRegs; x++) { 611 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 612 } 613 } 614 } 615}}; 616 617