arm.isa revision 7102
14467Sstever@eecs.umich.edu// -*- mode:c++ -*- 23354Srdreslin@umich.edu 33354Srdreslin@umich.edu// Copyright (c) 2010 ARM Limited 43354Srdreslin@umich.edu// All rights reserved 53354Srdreslin@umich.edu// 63354Srdreslin@umich.edu// The license below extends only to copyright in the software and shall 73354Srdreslin@umich.edu// not be construed as granting a license to any other intellectual 83354Srdreslin@umich.edu// property including but not limited to intellectual property relating 93354Srdreslin@umich.edu// to a hardware implementation of the functionality of the software 103354Srdreslin@umich.edu// licensed hereunder. You may use the software subject to the license 113354Srdreslin@umich.edu// terms below provided that you ensure that this notice is replicated 123354Srdreslin@umich.edu// unmodified and in its entirety in all distributions of the software, 133354Srdreslin@umich.edu// modified or unmodified, in source code or in binary form. 143354Srdreslin@umich.edu// 153354Srdreslin@umich.edu// Copyright (c) 2007-2008 The Florida State University 163354Srdreslin@umich.edu// All rights reserved. 173354Srdreslin@umich.edu// 183354Srdreslin@umich.edu// Redistribution and use in source and binary forms, with or without 193354Srdreslin@umich.edu// modification, are permitted provided that the following conditions are 203354Srdreslin@umich.edu// met: redistributions of source code must retain the above copyright 213354Srdreslin@umich.edu// notice, this list of conditions and the following disclaimer; 223354Srdreslin@umich.edu// redistributions in binary form must reproduce the above copyright 233354Srdreslin@umich.edu// notice, this list of conditions and the following disclaimer in the 243354Srdreslin@umich.edu// documentation and/or other materials provided with the distribution; 253354Srdreslin@umich.edu// neither the name of the copyright holders nor the names of its 263354Srdreslin@umich.edu// contributors may be used to endorse or promote products derived from 273354Srdreslin@umich.edu// this software without specific prior written permission. 283354Srdreslin@umich.edu// 296654Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306654Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316654Snate@binkert.org// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323354Srdreslin@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333354Srdreslin@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343354Srdreslin@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353354Srdreslin@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363354Srdreslin@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374626Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384626Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394626Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404626Sstever@eecs.umich.edu// 414893Sstever@eecs.umich.edu// Authors: Stephen Hines 424892Sstever@eecs.umich.edu 434626Sstever@eecs.umich.edu//////////////////////////////////////////////////////////////////// 444626Sstever@eecs.umich.edu// 454626Sstever@eecs.umich.edu// The actual ARM ISA decoder 464626Sstever@eecs.umich.edu// -------------------------- 474892Sstever@eecs.umich.edu// The following instructions are specified in the ARM ISA 484892Sstever@eecs.umich.edu// Specification. Decoding closely follows the style specified 494892Sstever@eecs.umich.edu// in the ARM ISA specification document starting with Table B.1 or 3-1 504892Sstever@eecs.umich.edu// 514892Sstever@eecs.umich.edu// 524892Sstever@eecs.umich.edu 534892Sstever@eecs.umich.edu0: decode ENCODING { 544892Sstever@eecs.umich.eduformat DataOp { 554892Sstever@eecs.umich.edu 0x0: decode SEVEN_AND_FOUR { 564892Sstever@eecs.umich.edu 1: decode MISC_OPCODE { 574892Sstever@eecs.umich.edu 0x9: decode PREPOST { 584892Sstever@eecs.umich.edu 0: decode OPCODE { 594892Sstever@eecs.umich.edu 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 604892Sstever@eecs.umich.edu 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 614892Sstever@eecs.umich.edu 0x2: WarnUnimpl::umall(); 624892Sstever@eecs.umich.edu 0x4: umull({{ 634892Sstever@eecs.umich.edu resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 644892Sstever@eecs.umich.edu Rd = (uint32_t)(resTemp & 0xffffffff); 654892Sstever@eecs.umich.edu Rn = (uint32_t)(resTemp >> 32); 664892Sstever@eecs.umich.edu }}, llbit); 674892Sstever@eecs.umich.edu 0x5: smlal({{ 684892Sstever@eecs.umich.edu resTemp = ((int64_t)Rm) * ((int64_t)Rs); 694890Sstever@eecs.umich.edu resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 704891Sstever@eecs.umich.edu Rd = (uint32_t)(resTemp & 0xffffffff); 714891Sstever@eecs.umich.edu Rn = (uint32_t)(resTemp >> 32); 724890Sstever@eecs.umich.edu }}, llbit); 734626Sstever@eecs.umich.edu 0x6: smull({{ 744626Sstever@eecs.umich.edu resTemp = ((int64_t)(int32_t)Rm)* 754626Sstever@eecs.umich.edu ((int64_t)(int32_t)Rs); 764626Sstever@eecs.umich.edu Rd = (int32_t)(resTemp & 0xffffffff); 774626Sstever@eecs.umich.edu Rn = (int32_t)(resTemp >> 32); 784626Sstever@eecs.umich.edu }}, llbit); 794626Sstever@eecs.umich.edu 0x7: umlal({{ 804626Sstever@eecs.umich.edu resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 813354Srdreslin@umich.edu resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 824628Sstever@eecs.umich.edu Rd = (uint32_t)(resTemp & 0xffffffff); 834628Sstever@eecs.umich.edu Rn = (uint32_t)(resTemp >> 32); 844628Sstever@eecs.umich.edu }}, llbit); 854628Sstever@eecs.umich.edu } 864628Sstever@eecs.umich.edu 1: decode PUBWL { 873354Srdreslin@umich.edu 0x10: WarnUnimpl::swp(); 883354Srdreslin@umich.edu 0x14: WarnUnimpl::swpb(); 893354Srdreslin@umich.edu 0x18: WarnUnimpl::strex(); 903354Srdreslin@umich.edu 0x19: WarnUnimpl::ldrex(); 913354Srdreslin@umich.edu } 923354Srdreslin@umich.edu } 934626Sstever@eecs.umich.edu format AddrMode3 { 944626Sstever@eecs.umich.edu 0xb: strh_ldrh(store, {{ Mem.uh = Rd; }}, 954892Sstever@eecs.umich.edu load, {{ Rd = Mem.uh; }}); 964892Sstever@eecs.umich.edu 0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0); 974892Sstever@eecs.umich.edu Rdo = bits(Mem.ud, 63, 32); }}, 984892Sstever@eecs.umich.edu load, {{ Rd = Mem.sb; }}); 994892Sstever@eecs.umich.edu 0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) | 1004892Sstever@eecs.umich.edu (Rdo.ud << 32); }}, 1013354Srdreslin@umich.edu load, {{ Rd = Mem.sh; }}); 1024890Sstever@eecs.umich.edu } 1034626Sstever@eecs.umich.edu } 1044626Sstever@eecs.umich.edu 0: decode IS_MISC { 1054626Sstever@eecs.umich.edu 0: decode OPCODE { 1063354Srdreslin@umich.edu 0x0: and({{ Rd = resTemp = Rn & op2; }}); 1074890Sstever@eecs.umich.edu 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); 1084890Sstever@eecs.umich.edu 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); 1094890Sstever@eecs.umich.edu 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); 1104890Sstever@eecs.umich.edu 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); 1114890Sstever@eecs.umich.edu 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add); 1124890Sstever@eecs.umich.edu 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub); 1134890Sstever@eecs.umich.edu 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb); 1144890Sstever@eecs.umich.edu 0x8: tst({{ resTemp = Rn & op2; }}); 1154890Sstever@eecs.umich.edu 0x9: teq({{ resTemp = Rn ^ op2; }}); 1164890Sstever@eecs.umich.edu 0xa: cmp({{ resTemp = Rn - op2; }}, sub); 1174890Sstever@eecs.umich.edu 0xb: cmn({{ resTemp = Rn + op2; }}, add); 1187656Ssteve.reinhardt@amd.com 0xc: orr({{ Rd = resTemp = Rn | op2; }}); 1194890Sstever@eecs.umich.edu 0xd: mov({{ Rd = resTemp = op2; }}); 1204893Sstever@eecs.umich.edu 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); 1214893Sstever@eecs.umich.edu 0xf: mvn({{ Rd = resTemp = ~op2; }}); 1224893Sstever@eecs.umich.edu } 1234890Sstever@eecs.umich.edu 1: decode MISC_OPCODE { 1244890Sstever@eecs.umich.edu 0x0: decode OPCODE { 1254890Sstever@eecs.umich.edu 0x8: PredOp::mrs_cpsr({{ 1264890Sstever@eecs.umich.edu Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 1274893Sstever@eecs.umich.edu }}); 1284893Sstever@eecs.umich.edu 0x9: decode USEIMM { 1294893Sstever@eecs.umich.edu // The mask field is the same as the RN index. 1304893Sstever@eecs.umich.edu 0: PredOp::msr_cpsr_reg({{ 1314893Sstever@eecs.umich.edu uint32_t newCpsr = 1327656Ssteve.reinhardt@amd.com cpsrWriteByInstr(Cpsr | CondCodes, 1334890Sstever@eecs.umich.edu Rm, RN, false); 1344890Sstever@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1354890Sstever@eecs.umich.edu CondCodes = CondCodesMask & newCpsr; 1367656Ssteve.reinhardt@amd.com }}); 1374890Sstever@eecs.umich.edu 1: PredImmOp::msr_cpsr_imm({{ 1387656Ssteve.reinhardt@amd.com uint32_t newCpsr = 1397656Ssteve.reinhardt@amd.com cpsrWriteByInstr(Cpsr | CondCodes, 1404890Sstever@eecs.umich.edu rotated_imm, RN, false); 1414467Sstever@eecs.umich.edu Cpsr = ~CondCodesMask & newCpsr; 1423354Srdreslin@umich.edu CondCodes = CondCodesMask & newCpsr; 1434890Sstever@eecs.umich.edu }}); 1444890Sstever@eecs.umich.edu } 1453354Srdreslin@umich.edu 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 1464890Sstever@eecs.umich.edu 0xb: decode USEIMM { 1474890Sstever@eecs.umich.edu // The mask field is the same as the RN index. 1484890Sstever@eecs.umich.edu 0: PredOp::msr_spsr_reg({{ 1494895Sstever@eecs.umich.edu Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 1504890Sstever@eecs.umich.edu }}); 1514890Sstever@eecs.umich.edu 1: PredImmOp::msr_spsr_imm({{ 1524890Sstever@eecs.umich.edu Spsr = spsrWriteByInstr(Spsr, rotated_imm, 1534890Sstever@eecs.umich.edu RN, false); 1544890Sstever@eecs.umich.edu }}); 1554890Sstever@eecs.umich.edu } 1564890Sstever@eecs.umich.edu } 1574890Sstever@eecs.umich.edu 0x1: decode OPCODE { 1584890Sstever@eecs.umich.edu 0x9: BranchExchange::bx({{ }}); 1594890Sstever@eecs.umich.edu 0xb: PredOp::clz({{ 1604890Sstever@eecs.umich.edu Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 1614890Sstever@eecs.umich.edu }}); 1624890Sstever@eecs.umich.edu } 1634890Sstever@eecs.umich.edu 0x2: decode OPCODE { 1644890Sstever@eecs.umich.edu 0x9: WarnUnimpl::bxj(); 1654890Sstever@eecs.umich.edu } 1664890Sstever@eecs.umich.edu 0x3: decode OPCODE { 1674890Sstever@eecs.umich.edu 0x9: BranchExchange::blx({{ }}, Link); 1683354Srdreslin@umich.edu } 1694890Sstever@eecs.umich.edu 0x5: decode OPCODE { 1703354Srdreslin@umich.edu 0x8: WarnUnimpl::qadd(); 1713354Srdreslin@umich.edu 0x9: WarnUnimpl::qsub(); 1723354Srdreslin@umich.edu 0xa: WarnUnimpl::qdadd(); 1733354Srdreslin@umich.edu 0xb: WarnUnimpl::qdsub(); 1743354Srdreslin@umich.edu } 1758801Sgblack@eecs.umich.edu 0x8: decode OPCODE { 1764626Sstever@eecs.umich.edu 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 1774626Sstever@eecs.umich.edu 0x9: WarnUnimpl::smlalbb(); 1784626Sstever@eecs.umich.edu 0xa: WarnUnimpl::smlawb(); 1793354Srdreslin@umich.edu 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none); 1803354Srdreslin@umich.edu } 1814476Sstever@eecs.umich.edu 0xa: decode OPCODE { 1824476Sstever@eecs.umich.edu 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 1834476Sstever@eecs.umich.edu 0x9: smulwb({{ 1843354Srdreslin@umich.edu Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 1857525Ssteve.reinhardt@amd.com }}, none); 1863354Srdreslin@umich.edu 0xa: WarnUnimpl::smlaltb(); 1873354Srdreslin@umich.edu 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none); 1884626Sstever@eecs.umich.edu } 1893354Srdreslin@umich.edu 0xc: decode OPCODE { 1903354Srdreslin@umich.edu 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 191 0x9: WarnUnimpl::smlawt(); 192 0xa: WarnUnimpl::smlalbt(); 193 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none); 194 } 195 0xe: decode OPCODE { 196 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 197 0x9: smulwt({{ 198 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 199 }}, none); 200 0xa: WarnUnimpl::smlaltt(); 201 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none); 202 } 203 } 204 } 205 } 206 0x1: decode IS_MISC { 207 0: decode OPCODE { 208 format DataImmOp { 209 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); 210 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); 211 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); 212 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); 213 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); 214 0x5: adci({{ 215 Rd = resTemp = Rn + rotated_imm + CondCodes<29:>; 216 }}, add); 217 0x6: sbci({{ 218 Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>; 219 }}, sub); 220 0x7: rsci({{ 221 Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>; 222 }}, rsb); 223 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); 224 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); 225 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); 226 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); 227 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); 228 0xd: movi({{ Rd = resTemp = rotated_imm; }}); 229 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); 230 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); 231 } 232 } 233 1: decode OPCODE { 234 // The following two instructions aren't supposed to be defined 235 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 236 0x9: decode RN { 237 0: decode IMM { 238 0: PredImmOp::nop({{ ; }}); 239 1: WarnUnimpl::yield(); 240 2: WarnUnimpl::wfe(); 241 3: WarnUnimpl::wfi(); 242 4: WarnUnimpl::sev(); 243 } 244 default: PredImmOp::msr_i_cpsr({{ 245 uint32_t newCpsr = 246 cpsrWriteByInstr(Cpsr | CondCodes, 247 rotated_imm, RN, false); 248 Cpsr = ~CondCodesMask & newCpsr; 249 CondCodes = CondCodesMask & newCpsr; 250 }}); 251 } 252 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 253 0xb: PredImmOp::msr_i_spsr({{ 254 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 255 }}); 256 } 257 } 258 0x2: AddrMode2::addrMode2(Disp, disp); 259 0x3: decode OPCODE_4 { 260 0: AddrMode2::addrMode2(Shift, Rm_Imm); 261 1: decode MEDIA_OPCODE { 262 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 263 0x8: decode MISC_OPCODE { 264 0x1, 0x9: WarnUnimpl::pkhbt(); 265 0x7: WarnUnimpl::sxtab16(); 266 0xb: WarnUnimpl::sel(); 267 0x5, 0xd: WarnUnimpl::pkhtb(); 268 0x3: WarnUnimpl::sign_zero_extend_add(); 269 } 270 0xa, 0xb: decode SHIFT { 271 0x0, 0x2: WarnUnimpl::ssat(); 272 0x1: WarnUnimpl::ssat16(); 273 } 274 0xe, 0xf: decode SHIFT { 275 0x0, 0x2: WarnUnimpl::usat(); 276 0x1: WarnUnimpl::usat16(); 277 } 278 0x10: decode RN { 279 0xf: decode MISC_OPCODE { 280 0x1: WarnUnimpl::smuad(); 281 0x3: WarnUnimpl::smuadx(); 282 0x5: WarnUnimpl::smusd(); 283 0x7: WarnUnimpl::smusdx(); 284 } 285 default: decode MISC_OPCODE { 286 0x1: WarnUnimpl::smlad(); 287 0x3: WarnUnimpl::smladx(); 288 0x5: WarnUnimpl::smlsd(); 289 0x7: WarnUnimpl::smlsdx(); 290 } 291 } 292 0x14: decode MISC_OPCODE { 293 0x1: WarnUnimpl::smlald(); 294 0x3: WarnUnimpl::smlaldx(); 295 0x5: WarnUnimpl::smlsld(); 296 0x7: WarnUnimpl::smlsldx(); 297 } 298 0x15: decode RN { 299 0xf: decode MISC_OPCODE { 300 0x1: WarnUnimpl::smmul(); 301 0x3: WarnUnimpl::smmulr(); 302 } 303 default: decode MISC_OPCODE { 304 0x1: WarnUnimpl::smmla(); 305 0x3: WarnUnimpl::smmlar(); 306 0xd: WarnUnimpl::smmls(); 307 0xf: WarnUnimpl::smmlsr(); 308 } 309 } 310 0x18: decode RN { 311 0xf: WarnUnimpl::usada8(); 312 default: WarnUnimpl::usad8(); 313 } 314 } 315 } 316 0x4: decode PUSWL { 317 // Right now we only handle cases when S (PSRUSER) is not set 318 default: ArmMacroStore::ldmstm({{ }}); 319 } 320 0x5: decode OPCODE_24 { 321 // Branch (and Link) Instructions 322 0: Branch::b({{ }}); 323 1: Branch::bl({{ }}, Link); 324 } 325 0x6: decode CPNUM { 326 0x1: decode PUNWL { 327 0x02,0x0a: decode OPCODE_15 { 328 0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf; 329 Rn = Rn + disp8; }}, 330 {{ EA = Rn; }}); 331 1: ArmMacroFPAOp::stfd_({{ }}); 332 } 333 0x03,0x0b: decode OPCODE_15 { 334 0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf; 335 Rn = Rn + disp8; }}, 336 {{ EA = Rn; }}); 337 1: ArmMacroFPAOp::ldfd_({{ }}); 338 } 339 0x06,0x0e: decode OPCODE_15 { 340 0: ArmMacroFPAOp::stfe_nw({{ }}); 341 } 342 0x07,0x0f: decode OPCODE_15 { 343 0: ArmMacroFPAOp::ldfe_nw({{ }}); 344 } 345 0x10,0x18: decode OPCODE_15 { 346 0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }}, 347 {{ EA = Rn + disp8; }}); 348 1: ArmMacroFPAOp::stfd_p({{ }}); 349 } 350 0x11,0x19: decode OPCODE_15 { 351 0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }}, 352 {{ EA = Rn + disp8; }}); 353 1: ArmMacroFPAOp::ldfd_p({{ }}); 354 } 355 0x12,0x1a: decode OPCODE_15 { 356 0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf; 357 Rn = Rn + disp8; }}, 358 {{ EA = Rn + disp8; }}); 359 1: ArmMacroFPAOp::stfd_pw({{ }}); 360 } 361 0x13,0x1b: decode OPCODE_15 { 362 0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf; 363 Rn = Rn + disp8; }}, 364 {{ EA = Rn + disp8; }}); 365 1: ArmMacroFPAOp::ldfd_pw({{ }}); 366 } 367 0x14,0x1c: decode OPCODE_15 { 368 0: ArmMacroFPAOp::stfe_pn({{ }}); 369 } 370 0x15,0x1d: decode OPCODE_15 { 371 0: ArmMacroFPAOp::ldfe_pn({{ }}); 372 } 373 0x16,0x1e: decode OPCODE_15 { 374 0: ArmMacroFPAOp::stfe_pnw({{ }}); 375 } 376 0x17,0x1f: decode OPCODE_15 { 377 0: ArmMacroFPAOp::ldfe_pnw({{ }}); 378 } 379 } 380 0x2: decode PUNWL { 381 // could really just decode as a single instruction 382 0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }}); 383 0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }}); 384 0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }}); 385 0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }}); 386 0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }}); 387 0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }}); 388 0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }}); 389 0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }}); 390 } 391 0xb: decode LOADOP { 392 0x0: WarnUnimpl::fstmx(); 393 0x1: WarnUnimpl::fldmx(); 394 } 395 } 396 0x7: decode OPCODE_24 { 397 0: decode OPCODE_4 { 398 0: decode CPNUM { 399 format FloatOp { 400 0x1: decode OPCODE_23_20 { 401 0x0: decode OPCODE_15 { 402 0: adf({{ Fd.sf = Fn.sf + Fm.sf; }}); 403 1: mvf({{ Fd.sf = Fm.sf; }}); 404 } 405 0x1: decode OPCODE_15 { 406 0: muf({{ Fd.sf = Fn.sf * Fm.sf; }}); 407 1: mnf({{ Fd.sf = -Fm.sf; }}); 408 } 409 0x2: decode OPCODE_15 { 410 0: suf({{ Fd.sf = Fn.sf - Fm.sf; }}); 411 1: abs({{ Fd.sf = fabs(Fm.sf); }}); 412 } 413 0x3: decode OPCODE_15 { 414 0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }}); 415 1: rnd({{ Fd.sf = rint(Fm.sf); }}); 416 } 417 0x4: decode OPCODE_15 { 418 0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }}); 419 1: sqt({{ Fd.sf = sqrt(Fm.sf); }}); 420 } 421 0x5: decode OPCODE_15 { 422 0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }}); 423 1: log({{ Fd.sf = log10(Fm.sf); }}); 424 } 425 0x6: decode OPCODE_15 { 426 0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }}); 427 1: lgn({{ Fd.sf = log(Fm.sf); }}); 428 } 429 0x7: decode OPCODE_15 { 430 0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }}); 431 1: exp({{ Fd.sf = exp(Fm.sf); }}); 432 } 433 0x8: decode OPCODE_15 { 434 0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }}); 435 1: sin({{ Fd.sf = sin(Fm.sf); }}); 436 } 437 0x9: decode OPCODE_15 { 438 0: fml({{ Fd.sf = Fn.sf * Fm.sf; }}); 439 1: cos({{ Fd.sf = cos(Fm.sf); }}); 440 } 441 0xa: decode OPCODE_15 { 442 0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }}); 443 1: tan({{ Fd.sf = tan(Fm.sf); }}); 444 } 445 0xb: decode OPCODE_15 { 446 0: frd({{ Fd.sf = Fm.sf / Fn.sf; }}); 447 1: asn({{ Fd.sf = asin(Fm.sf); }}); 448 } 449 0xc: decode OPCODE_15 { 450 0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }}); 451 1: acs({{ Fd.sf = acos(Fm.sf); }}); 452 } 453 0xd: decode OPCODE_15 { 454 1: atn({{ Fd.sf = atan(Fm.sf); }}); 455 } 456 0xe: decode OPCODE_15 { 457 // Unnormalised Round 458 1: FailUnimpl::urd(); 459 } 460 0xf: decode OPCODE_15 { 461 // Normalise 462 1: FailUnimpl::nrm(); 463 } 464 } // OPCODE_23_20 465 } // format FloatOp 466 } // CPNUM 467 1: decode CPNUM { // 27-24=1110,4 ==1 468 1: decode OPCODE_15_12 { 469 format FloatOp { 470 0xf: decode OPCODE_23_21 { 471 format FloatCmp { 472 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 473 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 474 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 475 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 476 } 477 } 478 default: decode OPCODE_23_20 { 479 0x0: decode OPCODE_7 { 480 0: flts({{ Fn.sf = (float) Rd.sw; }}); 481 1: fltd({{ Fn.df = (double) Rd.sw; }}); 482 } 483 0x1: decode OPCODE_7 { 484 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 485 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 486 } 487 0x2: wfs({{ Fpsr = Rd; }}); 488 0x3: rfs({{ Rd = Fpsr; }}); 489 0x4: FailUnimpl::wfc(); 490 0x5: FailUnimpl::rfc(); 491 } 492 } // format FloatOp 493 } 494 0xa: decode MISC_OPCODE { 495 0x1: decode MEDIA_OPCODE { 496 0xf: decode RN { 497 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 498 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 499 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 500 } 501 0xe: decode RN { 502 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 503 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 504 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 505 } 506 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 507 } // MISC_OPCODE (CPNUM 0xA) 508 0xf: decode RN { 509 // Barrriers, Cache Maintence, NOPS 510 7: decode OPCODE_23_21 { 511 0: decode RM { 512 0: decode OPC2 { 513 4: decode OPCODE_20 { 514 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 515 } 516 } 517 1: WarnUnimpl::cp15_cache_maint(); 518 4: WarnUnimpl::cp15_par(); 519 5: decode OPC2 { 520 0,1: WarnUnimpl::cp15_cache_maint2(); 521 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 522 6,7: WarnUnimpl::cp15_bp_maint(); 523 } 524 6: WarnUnimpl::cp15_cache_maint3(); 525 8: WarnUnimpl::cp15_va_to_pa(); 526 10: decode OPC2 { 527 1,2: WarnUnimpl::cp15_cache_maint3(); 528 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 529 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 530 } 531 11: WarnUnimpl::cp15_cache_maint4(); 532 13: decode OPC2 { 533 1: decode OPCODE_20 { 534 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 535 } 536 } 537 14: WarnUnimpl::cp15_cache_maint5(); 538 } // RM 539 } // OPCODE_23_21 CR 540 541 // Thread ID and context ID registers 542 // Thread ID register needs cheaper access than miscreg 543 13: WarnUnimpl::mcr_mrc_cp15_c7(); 544 545 // All the rest 546 default: decode OPCODE_20 { 547 0: PredOp::mcr_cp15({{ 548 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 549 }}); 550 1: PredOp::mrc_cp15({{ 551 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 552 }}); 553 } 554 } // RN 555 } // CPNUM (OP4 == 1) 556 } //OPCODE_4 557 558#if FULL_SYSTEM 559 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 560#else 561 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 562 { 563 if (IMMED_23_0) 564 xc->syscall(IMMED_23_0); 565 else 566 xc->syscall(R7); 567 } 568 }}); 569#endif // FULL_SYSTEM 570 } // OPCODE_24 571 572} 573} 574 575