arch-arm: Add AArch32 HLT Semihosting interface

AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ARM: Add limited CP14 support.

New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.

ARM: Add support for M5 ops in the ARM ISA

ARM: Move some case values out of ##included files.

This will help keep the high level decode together and not have it spread into
the subordinate decode stuff. The ##include lines still need to be on a line
by themselves, though.

ARM: Move some miscellaneous instructions out of the decoder to share with thumb.

ARM: Get rid of some of the old FP implementation.

ARM: Add BKPT instruction

ARM: Implement ARM CPU interrupts

ARM: Move the VFP data operation decode into a function.

ARM: Add some support for wfi/wfe/yield/etc

ARM: BXJ should be BX when there is no J support

ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.

ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.

ARM: Replace the ARM decode of CP15 MCR and MRC instructions.

ARM: Decode miscellaneous arm mode media instructions.

ARM: Decode the clz instruction.

ARM: Decode the usad8 and usada8 instructions.

ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.

ARM: Decode the swp and swpb instructions.

ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.

ARM: Implement SVC (was SWI) outside of the decoder.

ARM: Trigger system calls from the SupervisorCall invoke method.

This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.

ARM: Decode the scalar saturating add/subtract instructions.

ARM: Decode the parallel add and subtract instructions.

ARM: Decode unconditional ARM instructions.

ARM: Define the VFP load/store multiple instructions.

ARM: Hook the new multiply instructions into all the decoders.

ARM: Hook the new branch instructions into the ARM decoder.

ARM: Implement branch instructions external to the decoder.

ARM: Hook the new external data processing instructions to the ARM decoder.

ARM: Reimplement load/store multiple external to the decoder.

ARM: Eliminate decoding for the very deprecated FPA instructions.

ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.

ARM: Define the store instructions from outside the decoder.

ARM: Define the load instructions from outside the decoder.

ARM: Create a "decoder" directory for the files implementing the decoder.