arm.isa revision 7139:20b265c1515f
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2007-2008 The Florida State University 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Stephen Hines 42 43//////////////////////////////////////////////////////////////////// 44// 45// The actual ARM ISA decoder 46// -------------------------- 47// The following instructions are specified in the ARM ISA 48// Specification. Decoding closely follows the style specified 49// in the ARM ISA specification document starting with Table B.1 or 3-1 50// 51// 52 530: decode ENCODING { 54format DataOp { 55 0x0: decode SEVEN_AND_FOUR { 56 1: decode MISC_OPCODE { 57 0x9: decode PREPOST { 58 0: decode OPCODE { 59 0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none); 60 0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none); 61 0x2: WarnUnimpl::umall(); 62 0x4: umull({{ 63 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 64 Rd = (uint32_t)(resTemp & 0xffffffff); 65 Rn = (uint32_t)(resTemp >> 32); 66 }}, llbit); 67 0x5: smlal({{ 68 resTemp = ((int64_t)Rm) * ((int64_t)Rs); 69 resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 70 Rd = (uint32_t)(resTemp & 0xffffffff); 71 Rn = (uint32_t)(resTemp >> 32); 72 }}, llbit); 73 0x6: smull({{ 74 resTemp = ((int64_t)(int32_t)Rm)* 75 ((int64_t)(int32_t)Rs); 76 Rd = (int32_t)(resTemp & 0xffffffff); 77 Rn = (int32_t)(resTemp >> 32); 78 }}, llbit); 79 0x7: umlal({{ 80 resTemp = ((uint64_t)Rm)*((uint64_t)Rs); 81 resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd); 82 Rd = (uint32_t)(resTemp & 0xffffffff); 83 Rn = (uint32_t)(resTemp >> 32); 84 }}, llbit); 85 } 86 1: decode PUBWL { 87 0x10: WarnUnimpl::swp(); 88 0x14: WarnUnimpl::swpb(); 89 0x18: WarnUnimpl::strex(); 90 0x19: WarnUnimpl::ldrex(); 91 } 92 } 93 0xb, 0xd, 0xf: AddrMode3::addrMode3(); 94 } 95 0: decode IS_MISC { 96 0: ArmDataProcReg::armDataProcReg(); 97 1: decode MISC_OPCODE { 98 0x0: decode OPCODE { 99 0x8: PredOp::mrs_cpsr({{ 100 Rd = (Cpsr | CondCodes) & 0xF8FF03DF; 101 }}); 102 0x9: decode USEIMM { 103 // The mask field is the same as the RN index. 104 0: PredOp::msr_cpsr_reg({{ 105 uint32_t newCpsr = 106 cpsrWriteByInstr(Cpsr | CondCodes, 107 Rm, RN, false); 108 Cpsr = ~CondCodesMask & newCpsr; 109 CondCodes = CondCodesMask & newCpsr; 110 }}); 111 1: PredImmOp::msr_cpsr_imm({{ 112 uint32_t newCpsr = 113 cpsrWriteByInstr(Cpsr | CondCodes, 114 rotated_imm, RN, false); 115 Cpsr = ~CondCodesMask & newCpsr; 116 CondCodes = CondCodesMask & newCpsr; 117 }}); 118 } 119 0xa: PredOp::mrs_spsr({{ Rd = Spsr; }}); 120 0xb: decode USEIMM { 121 // The mask field is the same as the RN index. 122 0: PredOp::msr_spsr_reg({{ 123 Spsr = spsrWriteByInstr(Spsr, Rm, RN, false); 124 }}); 125 1: PredImmOp::msr_spsr_imm({{ 126 Spsr = spsrWriteByInstr(Spsr, rotated_imm, 127 RN, false); 128 }}); 129 } 130 } 131 0x1: decode OPCODE { 132 0x9: BranchExchange::bx({{ }}); 133 0xb: PredOp::clz({{ 134 Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); 135 }}); 136 } 137 0x2: decode OPCODE { 138 0x9: WarnUnimpl::bxj(); 139 } 140 0x3: decode OPCODE { 141 0x9: BranchExchange::blx({{ }}, Link); 142 } 143 0x5: decode OPCODE { 144 0x8: WarnUnimpl::qadd(); 145 0x9: WarnUnimpl::qsub(); 146 0xa: WarnUnimpl::qdadd(); 147 0xb: WarnUnimpl::qdsub(); 148 } 149 0x8: decode OPCODE { 150 0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 151 0x9: WarnUnimpl::smlalbb(); 152 0xa: WarnUnimpl::smlawb(); 153 0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none); 154 } 155 0xa: decode OPCODE { 156 0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow); 157 0x9: smulwb({{ 158 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 159 }}, none); 160 0xa: WarnUnimpl::smlaltb(); 161 0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none); 162 } 163 0xc: decode OPCODE { 164 0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 165 0x9: WarnUnimpl::smlawt(); 166 0xa: WarnUnimpl::smlalbt(); 167 0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none); 168 } 169 0xe: decode OPCODE { 170 0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow); 171 0x9: smulwt({{ 172 Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 173 }}, none); 174 0xa: WarnUnimpl::smlaltt(); 175 0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none); 176 } 177 } 178 } 179 } 180 0x1: decode IS_MISC { 181 0: ArmDataProcImm::armDataProcImm(); 182 1: decode OPCODE { 183 // The following two instructions aren't supposed to be defined 184 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); 185 0x9: decode RN { 186 0: decode IMM { 187 0: PredImmOp::nop({{ ; }}); 188 1: WarnUnimpl::yield(); 189 2: WarnUnimpl::wfe(); 190 3: WarnUnimpl::wfi(); 191 4: WarnUnimpl::sev(); 192 } 193 default: PredImmOp::msr_i_cpsr({{ 194 uint32_t newCpsr = 195 cpsrWriteByInstr(Cpsr | CondCodes, 196 rotated_imm, RN, false); 197 Cpsr = ~CondCodesMask & newCpsr; 198 CondCodes = CondCodesMask & newCpsr; 199 }}); 200 } 201 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }}); 202 0xb: PredImmOp::msr_i_spsr({{ 203 Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 204 }}); 205 } 206 } 207 0x2: AddrMode2::addrMode2(True); 208 0x3: decode OPCODE_4 { 209 0: AddrMode2::addrMode2(False); 210 1: decode MEDIA_OPCODE { 211 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions(); 212 0x8: decode MISC_OPCODE { 213 0x1, 0x9: WarnUnimpl::pkhbt(); 214 0x7: WarnUnimpl::sxtab16(); 215 0xb: WarnUnimpl::sel(); 216 0x5, 0xd: WarnUnimpl::pkhtb(); 217 0x3: WarnUnimpl::sign_zero_extend_add(); 218 } 219 0xa, 0xb: decode SHIFT { 220 0x0, 0x2: WarnUnimpl::ssat(); 221 0x1: WarnUnimpl::ssat16(); 222 } 223 0xe, 0xf: decode SHIFT { 224 0x0, 0x2: WarnUnimpl::usat(); 225 0x1: WarnUnimpl::usat16(); 226 } 227 0x10: decode RN { 228 0xf: decode MISC_OPCODE { 229 0x1: WarnUnimpl::smuad(); 230 0x3: WarnUnimpl::smuadx(); 231 0x5: WarnUnimpl::smusd(); 232 0x7: WarnUnimpl::smusdx(); 233 } 234 default: decode MISC_OPCODE { 235 0x1: WarnUnimpl::smlad(); 236 0x3: WarnUnimpl::smladx(); 237 0x5: WarnUnimpl::smlsd(); 238 0x7: WarnUnimpl::smlsdx(); 239 } 240 } 241 0x14: decode MISC_OPCODE { 242 0x1: WarnUnimpl::smlald(); 243 0x3: WarnUnimpl::smlaldx(); 244 0x5: WarnUnimpl::smlsld(); 245 0x7: WarnUnimpl::smlsldx(); 246 } 247 0x15: decode RN { 248 0xf: decode MISC_OPCODE { 249 0x1: WarnUnimpl::smmul(); 250 0x3: WarnUnimpl::smmulr(); 251 } 252 default: decode MISC_OPCODE { 253 0x1: WarnUnimpl::smmla(); 254 0x3: WarnUnimpl::smmlar(); 255 0xd: WarnUnimpl::smmls(); 256 0xf: WarnUnimpl::smmlsr(); 257 } 258 } 259 0x18: decode RN { 260 0xf: WarnUnimpl::usada8(); 261 default: WarnUnimpl::usad8(); 262 } 263 } 264 } 265 0x4: ArmMacroMem::armMacroMem(); 266 0x5: decode OPCODE_24 { 267 // Branch (and Link) Instructions 268 0: Branch::b({{ }}); 269 1: Branch::bl({{ }}, Link); 270 } 271 0x6: decode CPNUM { 272 0xb: decode LOADOP { 273 0x0: WarnUnimpl::fstmx(); 274 0x1: WarnUnimpl::fldmx(); 275 } 276 } 277 0x7: decode OPCODE_24 { 278 0: decode OPCODE_4 { 279 0: decode CPNUM { 280 0xa, 0xb: decode OPCODE_23_20 { 281##include "vfp.isa" 282 } 283 } // CPNUM 284 1: decode CPNUM { // 27-24=1110,4 ==1 285 1: decode OPCODE_15_12 { 286 format FloatOp { 287 0xf: decode OPCODE_23_21 { 288 format FloatCmp { 289 0x4: cmf({{ Fn.df }}, {{ Fm.df }}); 290 0x5: cnf({{ Fn.df }}, {{ -Fm.df }}); 291 0x6: cmfe({{ Fn.df }}, {{ Fm.df}}); 292 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}}); 293 } 294 } 295 default: decode OPCODE_23_20 { 296 0x0: decode OPCODE_7 { 297 0: flts({{ Fn.sf = (float) Rd.sw; }}); 298 1: fltd({{ Fn.df = (double) Rd.sw; }}); 299 } 300 0x1: decode OPCODE_7 { 301 0: fixs({{ Rd = (uint32_t) Fm.sf; }}); 302 1: fixd({{ Rd = (uint32_t) Fm.df; }}); 303 } 304 0x2: wfs({{ Fpsr = Rd; }}); 305 0x3: rfs({{ Rd = Fpsr; }}); 306 0x4: FailUnimpl::wfc(); 307 0x5: FailUnimpl::rfc(); 308 } 309 } // format FloatOp 310 } 311 0xa: decode MISC_OPCODE { 312 0x1: decode MEDIA_OPCODE { 313 0xf: decode RN { 314 0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }}); 315 0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }}); 316 0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }}); 317 } 318 0xe: decode RN { 319 0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }}); 320 0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }}); 321 0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }}); 322 } 323 } // MEDIA_OPCODE (MISC_OPCODE 0x1) 324 } // MISC_OPCODE (CPNUM 0xA) 325 0xf: decode RN { 326 // Barrriers, Cache Maintence, NOPS 327 7: decode OPCODE_23_21 { 328 0: decode RM { 329 0: decode OPC2 { 330 4: decode OPCODE_20 { 331 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi 332 } 333 } 334 1: WarnUnimpl::cp15_cache_maint(); 335 4: WarnUnimpl::cp15_par(); 336 5: decode OPC2 { 337 0,1: WarnUnimpl::cp15_cache_maint2(); 338 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore); 339 6,7: WarnUnimpl::cp15_bp_maint(); 340 } 341 6: WarnUnimpl::cp15_cache_maint3(); 342 8: WarnUnimpl::cp15_va_to_pa(); 343 10: decode OPC2 { 344 1,2: WarnUnimpl::cp15_cache_maint3(); 345 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore); 346 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore); 347 } 348 11: WarnUnimpl::cp15_cache_maint4(); 349 13: decode OPC2 { 350 1: decode OPCODE_20 { 351 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch 352 } 353 } 354 14: WarnUnimpl::cp15_cache_maint5(); 355 } // RM 356 } // OPCODE_23_21 CR 357 358 // Thread ID and context ID registers 359 // Thread ID register needs cheaper access than miscreg 360 13: WarnUnimpl::mcr_mrc_cp15_c7(); 361 362 // All the rest 363 default: decode OPCODE_20 { 364 0: PredOp::mcr_cp15({{ 365 fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 366 }}); 367 1: PredOp::mrc_cp15({{ 368 fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 369 }}); 370 } 371 } // RN 372 } // CPNUM (OP4 == 1) 373 } //OPCODE_4 374 375#if FULL_SYSTEM 376 1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 377#else 378 1: PredOp::swi({{ if (testPredicate(CondCodes, condCode)) 379 { 380 if (IMMED_23_0) 381 xc->syscall(IMMED_23_0); 382 else 383 xc->syscall(R7); 384 } 385 }}); 386#endif // FULL_SYSTEM 387 } // OPCODE_24 388 389} 390} 391 392