isa.cc revision 13759
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 156019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 166019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 176019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 186019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 196019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 206019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 216019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 226019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 236019Shines@cs.fsu.edu * this software without specific prior written permission. 246019Shines@cs.fsu.edu * 256019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366019Shines@cs.fsu.edu * 376019Shines@cs.fsu.edu * Authors: Gabe Black 386019Shines@cs.fsu.edu * Ali Saidi 396019Shines@cs.fsu.edu */ 406019Shines@cs.fsu.edu 416735Sgblack@eecs.umich.edu#include "arch/arm/isa.hh" 426735Sgblack@eecs.umich.edu#include "arch/arm/pmu.hh" 4310037SARM gem5 Developers#include "arch/arm/system.hh" 4410037SARM gem5 Developers#include "arch/arm/tlb.hh" 456019Shines@cs.fsu.edu#include "arch/arm/tlbi_op.hh" 466019Shines@cs.fsu.edu#include "cpu/base.hh" 476019Shines@cs.fsu.edu#include "cpu/checker/cpu.hh" 4811793Sbrandon.potter@amd.com#include "debug/Arm.hh" 4911793Sbrandon.potter@amd.com#include "debug/MiscRegs.hh" 5010037SARM gem5 Developers#include "dev/arm/generic_timer.hh" 5110037SARM gem5 Developers#include "dev/arm/gic_v3.hh" 5210037SARM gem5 Developers#include "dev/arm/gic_v3_cpu_interface.hh" 538229Snate@binkert.org#include "params/ArmISA.hh" 548229Snate@binkert.org#include "sim/faults.hh" 556019Shines@cs.fsu.edu#include "sim/stat_control.hh" 568232Snate@binkert.org#include "sim/system.hh" 578782Sgblack@eecs.umich.edu 586019Shines@cs.fsu.edunamespace ArmISA 596019Shines@cs.fsu.edu{ 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.eduISA::ISA(Params *p) 6210037SARM gem5 Developers : SimObject(p), 6310037SARM gem5 Developers system(NULL), 6410037SARM gem5 Developers _decoderFlavour(p->decoderFlavour), 6510037SARM gem5 Developers _vecRegRenameMode(Enums::Full), 6610037SARM gem5 Developers pmu(p->pmu), 6710037SARM gem5 Developers haveGICv3CPUInterface(false), 6810037SARM gem5 Developers impdefAsNop(p->impdef_nop) 6910037SARM gem5 Developers{ 7010037SARM gem5 Developers miscRegs[MISCREG_SCTLR_RST] = 0; 7110037SARM gem5 Developers 7210037SARM gem5 Developers // Hook up a dummy device if we haven't been configured with a 7310037SARM gem5 Developers // real PMU. By using a dummy device, we don't need to check that 7410037SARM gem5 Developers // the PMU exist every time we try to access a PMU register. 7510037SARM gem5 Developers if (!pmu) 7610037SARM gem5 Developers pmu = &dummyDevice; 7710037SARM gem5 Developers 7810037SARM gem5 Developers // Give all ISA devices a pointer to this ISA 7910037SARM gem5 Developers pmu->setISA(this); 8010037SARM gem5 Developers 8110037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 8210037SARM gem5 Developers 8310037SARM gem5 Developers // Cache system-level properties 8410037SARM gem5 Developers if (FullSystem && system) { 8510037SARM gem5 Developers highestELIs64 = system->highestELIs64(); 8610037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8710037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8810037SARM gem5 Developers haveCrypto = system->haveCrypto(); 8910037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 9010037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 9110037SARM gem5 Developers physAddrRange = system->physAddrRange(); 9210037SARM gem5 Developers haveSVE = system->haveSVE(); 9310037SARM gem5 Developers sveVL = system->sveVL(); 9410037SARM gem5 Developers } else { 9510037SARM gem5 Developers highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9610037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9710037SARM gem5 Developers haveCrypto = true; 9810037SARM gem5 Developers haveLargeAsid64 = false; 9910037SARM gem5 Developers physAddrRange = 32; // dummy value 10010037SARM gem5 Developers haveSVE = true; 10110037SARM gem5 Developers sveVL = p->sve_vl_se; 1026019Shines@cs.fsu.edu } 10310037SARM gem5 Developers 10410037SARM gem5 Developers // Initial rename mode depends on highestEL 10510037SARM gem5 Developers const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 1066019Shines@cs.fsu.edu highestELIs64 ? Enums::Full : Enums::Elem; 10710037SARM gem5 Developers 10810037SARM gem5 Developers initializeMiscRegMetadata(); 10910037SARM gem5 Developers preUnflattenMiscReg(); 11010037SARM gem5 Developers 11110037SARM gem5 Developers clear(); 11210037SARM gem5 Developers} 11310037SARM gem5 Developers 11410037SARM gem5 Developersstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 11510037SARM gem5 Developers 11610037SARM gem5 Developersconst ArmISAParams * 11710037SARM gem5 DevelopersISA::params() const 11810037SARM gem5 Developers{ 11910037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 12010037SARM gem5 Developers} 12110037SARM gem5 Developers 12210037SARM gem5 Developersvoid 12310037SARM gem5 DevelopersISA::clear() 12410037SARM gem5 Developers{ 12510037SARM gem5 Developers const Params *p(params()); 12610037SARM gem5 Developers 12710037SARM gem5 Developers SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 12810037SARM gem5 Developers memset(miscRegs, 0, sizeof(miscRegs)); 12910037SARM gem5 Developers 13010037SARM gem5 Developers initID32(p); 13110037SARM gem5 Developers 13210037SARM gem5 Developers // We always initialize AArch64 ID registers even 13310037SARM gem5 Developers // if we are in AArch32. This is done since if we 13410037SARM gem5 Developers // are in SE mode we don't know if our ArmProcess is 13510037SARM gem5 Developers // AArch32 or AArch64 13610037SARM gem5 Developers initID64(p); 13710037SARM gem5 Developers 13810037SARM gem5 Developers // Start with an event in the mailbox 13910037SARM gem5 Developers miscRegs[MISCREG_SEV_MAILBOX] = 1; 14010037SARM gem5 Developers 14110037SARM gem5 Developers // Separate Instruction and Data TLBs 14210037SARM gem5 Developers miscRegs[MISCREG_TLBTR] = 1; 14310037SARM gem5 Developers 14410037SARM gem5 Developers MVFR0 mvfr0 = 0; 14510037SARM gem5 Developers mvfr0.advSimdRegisters = 2; 14610037SARM gem5 Developers mvfr0.singlePrecision = 2; 1476019Shines@cs.fsu.edu mvfr0.doublePrecision = 2; 14810037SARM gem5 Developers mvfr0.vfpExceptionTrapping = 0; 14910037SARM gem5 Developers mvfr0.divide = 1; 15010037SARM gem5 Developers mvfr0.squareRoot = 1; 1516019Shines@cs.fsu.edu mvfr0.shortVectors = 1; 15210037SARM gem5 Developers mvfr0.roundingModes = 1; 15310037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 15410037SARM gem5 Developers 15510037SARM gem5 Developers MVFR1 mvfr1 = 0; 15610037SARM gem5 Developers mvfr1.flushToZero = 1; 15710037SARM gem5 Developers mvfr1.defaultNaN = 1; 15810037SARM gem5 Developers mvfr1.advSimdLoadStore = 1; 15910037SARM gem5 Developers mvfr1.advSimdInteger = 1; 16010037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 16110037SARM gem5 Developers mvfr1.advSimdHalfPrecision = 1; 16210037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 16310037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 16410037SARM gem5 Developers 16510037SARM gem5 Developers // Reset values of PRRR and NMRR are implementation dependent 16610037SARM gem5 Developers 16710037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 16810037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 16910037SARM gem5 Developers (1 << 19) | // 19 17010037SARM gem5 Developers (0 << 18) | // 18 17110037SARM gem5 Developers (0 << 17) | // 17 17210037SARM gem5 Developers (1 << 16) | // 16 17310037SARM gem5 Developers (2 << 14) | // 15:14 17410037SARM gem5 Developers (0 << 12) | // 13:12 17510037SARM gem5 Developers (2 << 10) | // 11:10 17610037SARM gem5 Developers (2 << 8) | // 9:8 17710037SARM gem5 Developers (2 << 6) | // 7:6 17810037SARM gem5 Developers (2 << 4) | // 5:4 17910037SARM gem5 Developers (1 << 2) | // 3:2 18012571Sgiacomo.travaglini@arm.com 0; // 1:0 18110037SARM gem5 Developers 18210037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 18310037SARM gem5 Developers (1 << 30) | // 31:30 18410037SARM gem5 Developers (0 << 26) | // 27:26 18510037SARM gem5 Developers (0 << 24) | // 25:24 18610037SARM gem5 Developers (3 << 22) | // 23:22 18710037SARM gem5 Developers (2 << 20) | // 21:20 18810037SARM gem5 Developers (0 << 18) | // 19:18 18910037SARM gem5 Developers (0 << 16) | // 17:16 19010037SARM gem5 Developers (1 << 14) | // 15:14 19110037SARM gem5 Developers (0 << 12) | // 13:12 19210037SARM gem5 Developers (2 << 10) | // 11:10 1936019Shines@cs.fsu.edu (0 << 8) | // 9:8 19410037SARM gem5 Developers (3 << 6) | // 7:6 19510037SARM gem5 Developers (2 << 4) | // 5:4 19610037SARM gem5 Developers (0 << 2) | // 3:2 1976019Shines@cs.fsu.edu 0; // 1:0 19810037SARM gem5 Developers 19910037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 20010037SARM gem5 Developers // Initialize AArch64 state 20112517Srekai.gonzalezalberquilla@arm.com clear64(p); 20210037SARM gem5 Developers return; 20310037SARM gem5 Developers } 20410037SARM gem5 Developers 20512517Srekai.gonzalezalberquilla@arm.com // Initialize AArch32 state... 20612517Srekai.gonzalezalberquilla@arm.com clear32(p, sctlr_rst); 20712517Srekai.gonzalezalberquilla@arm.com} 20810037SARM gem5 Developers 20912517Srekai.gonzalezalberquilla@arm.comvoid 21012517Srekai.gonzalezalberquilla@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 21112517Srekai.gonzalezalberquilla@arm.com{ 21210037SARM gem5 Developers CPSR cpsr = 0; 21312517Srekai.gonzalezalberquilla@arm.com cpsr.mode = MODE_USER; 21412517Srekai.gonzalezalberquilla@arm.com 21512517Srekai.gonzalezalberquilla@arm.com if (FullSystem) { 21610037SARM gem5 Developers miscRegs[MISCREG_MVBAR] = system->resetAddr(); 21712517Srekai.gonzalezalberquilla@arm.com } 21812517Srekai.gonzalezalberquilla@arm.com 21912517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_CPSR] = cpsr; 22010037SARM gem5 Developers updateRegMap(cpsr); 22112517Srekai.gonzalezalberquilla@arm.com 22212517Srekai.gonzalezalberquilla@arm.com SCTLR sctlr = 0; 22312517Srekai.gonzalezalberquilla@arm.com sctlr.te = (bool) sctlr_rst.te; 22410037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 22512517Srekai.gonzalezalberquilla@arm.com sctlr.v = (bool) sctlr_rst.v; 22612517Srekai.gonzalezalberquilla@arm.com sctlr.u = 1; 22712517Srekai.gonzalezalberquilla@arm.com sctlr.xp = 1; 22810037SARM gem5 Developers sctlr.rao2 = 1; 22912517Srekai.gonzalezalberquilla@arm.com sctlr.rao3 = 1; 23012517Srekai.gonzalezalberquilla@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 23112517Srekai.gonzalezalberquilla@arm.com sctlr.uci = 1; 23210037SARM gem5 Developers sctlr.dze = 1; 23312517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 23412517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 23512517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_HCPTR] = 0; 23610037SARM gem5 Developers 23710037SARM gem5 Developers miscRegs[MISCREG_CPACR] = 0; 23812517Srekai.gonzalezalberquilla@arm.com 23912517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 24012517Srekai.gonzalezalberquilla@arm.com 24112512Sgiacomo.travaglini@arm.com if (haveLPAE) { 24212517Srekai.gonzalezalberquilla@arm.com TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 24312517Srekai.gonzalezalberquilla@arm.com ttbcr.eae = 0; 24412517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_TTBCR_NS] = ttbcr; 24510037SARM gem5 Developers // Enforce consistency with system-level settings 24612517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 24712517Srekai.gonzalezalberquilla@arm.com } 24812517Srekai.gonzalezalberquilla@arm.com 24910037SARM gem5 Developers if (haveSecurity) { 25012517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_SCTLR_S] = sctlr; 25112517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_SCR] = 0; 25212517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_VBAR_S] = 0; 25310037SARM gem5 Developers } else { 25412517Srekai.gonzalezalberquilla@arm.com // we're always non-secure 25512517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_SCR] = 1; 25612517Srekai.gonzalezalberquilla@arm.com } 25710037SARM gem5 Developers 25812517Srekai.gonzalezalberquilla@arm.com //XXX We need to initialize the rest of the state. 25912517Srekai.gonzalezalberquilla@arm.com} 26012517Srekai.gonzalezalberquilla@arm.com 26110037SARM gem5 Developersvoid 26210037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 26312517Srekai.gonzalezalberquilla@arm.com{ 26412517Srekai.gonzalezalberquilla@arm.com CPSR cpsr = 0; 26512517Srekai.gonzalezalberquilla@arm.com Addr rvbar = system->resetAddr(); 26610037SARM gem5 Developers switch (system->highestEL()) { 26710037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 26812517Srekai.gonzalezalberquilla@arm.com // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 26912517Srekai.gonzalezalberquilla@arm.com // value 27012517Srekai.gonzalezalberquilla@arm.com case EL3: 27110037SARM gem5 Developers cpsr.mode = MODE_EL3H; 27210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 27312517Srekai.gonzalezalberquilla@arm.com break; 27412517Srekai.gonzalezalberquilla@arm.com case EL2: 27512517Srekai.gonzalezalberquilla@arm.com cpsr.mode = MODE_EL2H; 27610037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 27710037SARM gem5 Developers break; 27812517Srekai.gonzalezalberquilla@arm.com case EL1: 27912517Srekai.gonzalezalberquilla@arm.com cpsr.mode = MODE_EL1H; 28012517Srekai.gonzalezalberquilla@arm.com miscRegs[MISCREG_RVBAR_EL1] = rvbar; 28112299Sandreas.sandberg@arm.com break; 28212299Sandreas.sandberg@arm.com default: 28312517Srekai.gonzalezalberquilla@arm.com panic("Invalid highest implemented exception level"); 28412517Srekai.gonzalezalberquilla@arm.com break; 28512517Srekai.gonzalezalberquilla@arm.com } 28610037SARM gem5 Developers 28710037SARM gem5 Developers // Initialize rest of CPSR 28812517Srekai.gonzalezalberquilla@arm.com cpsr.daif = 0xf; // Mask all interrupts 28912517Srekai.gonzalezalberquilla@arm.com cpsr.ss = 0; 29012517Srekai.gonzalezalberquilla@arm.com cpsr.il = 0; 29110037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 29210037SARM gem5 Developers updateRegMap(cpsr); 29312517Srekai.gonzalezalberquilla@arm.com 29412517Srekai.gonzalezalberquilla@arm.com // Initialize other control registers 2956019Shines@cs.fsu.edu miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 29610037SARM gem5 Developers if (haveSecurity) { 2977362Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2986735Sgblack@eecs.umich.edu miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 29910037SARM gem5 Developers } else if (haveVirtualization) { 3006019Shines@cs.fsu.edu // also MISCREG_SCTLR_EL2 (by mapping) 30110037SARM gem5 Developers miscRegs[MISCREG_HSCTLR] = 0x30c50830; 30210037SARM gem5 Developers } else { 3037400SAli.Saidi@ARM.com // also MISCREG_SCTLR_EL1 (by mapping) 3046735Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 3056735Sgblack@eecs.umich.edu // Always non-secure 30610037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 3076735Sgblack@eecs.umich.edu } 30810037SARM gem5 Developers} 30910037SARM gem5 Developers 31010037SARM gem5 Developersvoid 31110037SARM gem5 DevelopersISA::initID32(const ArmISAParams *p) 3127400SAli.Saidi@ARM.com{ 31310037SARM gem5 Developers // Initialize configurable default values 31410037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 31510037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 31610037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 31710037SARM gem5 Developers 31810037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 31910037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 32010037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 32110037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 32210037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 32310037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 32410037SARM gem5 Developers 32510037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 32610037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 32710037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 32810037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 32910037SARM gem5 Developers 3306019Shines@cs.fsu.edu miscRegs[MISCREG_ID_ISAR5] = insertBits( 3316019Shines@cs.fsu.edu miscRegs[MISCREG_ID_ISAR5], 19, 4, 33210037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 33310037SARM gem5 Developers} 33410037SARM gem5 Developers 33510037SARM gem5 Developersvoid 33610037SARM gem5 DevelopersISA::initID64(const ArmISAParams *p) 33710037SARM gem5 Developers{ 33810037SARM gem5 Developers // Initialize configurable id registers 33910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 34010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 34111574SCurtis.Dunham@arm.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 34211574SCurtis.Dunham@arm.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 34311574SCurtis.Dunham@arm.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 34411574SCurtis.Dunham@arm.com 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 34710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 34810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 34910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 35010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 35110037SARM gem5 Developers 35212511Schuan.zhu@arm.com miscRegs[MISCREG_ID_DFR0_EL1] = 35310037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 35410037SARM gem5 Developers 35510037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 35610037SARM gem5 Developers 35710037SARM gem5 Developers // SVE 35810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 35910037SARM gem5 Developers if (haveSecurity) { 36010037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 36110037SARM gem5 Developers } else if (haveVirtualization) { 36210037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 36310037SARM gem5 Developers } else { 36410037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 36510037SARM gem5 Developers } 36610037SARM gem5 Developers 36710037SARM gem5 Developers // Enforce consistency with system-level settings... 36810037SARM gem5 Developers 36910037SARM gem5 Developers // EL3 37010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 37210037SARM gem5 Developers haveSecurity ? 0x2 : 0x0); 37310037SARM gem5 Developers // EL2 37410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 37610037SARM gem5 Developers haveVirtualization ? 0x2 : 0x0); 37710037SARM gem5 Developers // SVE 37810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 38010037SARM gem5 Developers haveSVE ? 0x1 : 0x0); 38110037SARM gem5 Developers // Large ASID support 38210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 38410037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 38510037SARM gem5 Developers // Physical address size 38610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 38810037SARM gem5 Developers encodePhysAddrRange64(physAddrRange)); 38910037SARM gem5 Developers // Crypto 39010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 39110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 39210037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 39312402Sgiacomo.travaglini@arm.com} 39410037SARM gem5 Developers 39510037SARM gem5 Developersvoid 39610037SARM gem5 DevelopersISA::startup(ThreadContext *tc) 39710037SARM gem5 Developers{ 39810037SARM gem5 Developers pmu->setThreadContext(tc); 39910037SARM gem5 Developers 40010037SARM gem5 Developers if (system) { 40110037SARM gem5 Developers Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 40210037SARM gem5 Developers if (gicv3) { 40310037SARM gem5 Developers haveGICv3CPUInterface = true; 40410037SARM gem5 Developers gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 40510037SARM gem5 Developers gicv3CpuInterface->setISA(this); 40610037SARM gem5 Developers } 40710037SARM gem5 Developers } 40810037SARM gem5 Developers} 40910037SARM gem5 Developers 41010037SARM gem5 Developers 41110037SARM gem5 DevelopersRegVal 41210037SARM gem5 DevelopersISA::readMiscRegNoEffect(int misc_reg) const 41310037SARM gem5 Developers{ 41410037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 41510037SARM gem5 Developers 41610037SARM gem5 Developers const auto ® = lookUpMiscReg[misc_reg]; // bit masks 41710037SARM gem5 Developers const auto &map = getMiscIndices(misc_reg); 41810037SARM gem5 Developers int lower = map.first, upper = map.second; 41910037SARM gem5 Developers // NB!: apply architectural masks according to desired register, 42010037SARM gem5 Developers // despite possibly getting value from different (mapped) register. 42110037SARM gem5 Developers auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 42210037SARM gem5 Developers |(miscRegs[upper] << 32)); 42310037SARM gem5 Developers if (val & reg.res0()) { 42410037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 42510037SARM gem5 Developers miscRegName[misc_reg], val & reg.res0()); 42610037SARM gem5 Developers } 42710037SARM gem5 Developers if ((val & reg.res1()) != reg.res1()) { 42810037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 42912569Sgiacomo.travaglini@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 4306019Shines@cs.fsu.edu } 43110037SARM gem5 Developers return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 43210037SARM gem5 Developers} 43312569Sgiacomo.travaglini@arm.com 43412569Sgiacomo.travaglini@arm.com 43512569Sgiacomo.travaglini@arm.comRegVal 43612569Sgiacomo.travaglini@arm.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 43712569Sgiacomo.travaglini@arm.com{ 43810037SARM gem5 Developers CPSR cpsr = 0; 43912569Sgiacomo.travaglini@arm.com PCState pc = 0; 44012569Sgiacomo.travaglini@arm.com SCR scr = 0; 44112569Sgiacomo.travaglini@arm.com 44212569Sgiacomo.travaglini@arm.com if (misc_reg == MISCREG_CPSR) { 44312569Sgiacomo.travaglini@arm.com cpsr = miscRegs[misc_reg]; 44412569Sgiacomo.travaglini@arm.com pc = tc->pcState(); 44512569Sgiacomo.travaglini@arm.com cpsr.j = pc.jazelle() ? 1 : 0; 44612569Sgiacomo.travaglini@arm.com cpsr.t = pc.thumb() ? 1 : 0; 44712569Sgiacomo.travaglini@arm.com return cpsr; 44812569Sgiacomo.travaglini@arm.com } 44912569Sgiacomo.travaglini@arm.com 45012569Sgiacomo.travaglini@arm.com#ifndef NDEBUG 45112569Sgiacomo.travaglini@arm.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 45212402Sgiacomo.travaglini@arm.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 45312569Sgiacomo.travaglini@arm.com warn("Unimplemented system register %s read.\n", 45412569Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 45510037SARM gem5 Developers else 45612569Sgiacomo.travaglini@arm.com panic("Unimplemented system register %s read.\n", 45712569Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 45812569Sgiacomo.travaglini@arm.com } 45912569Sgiacomo.travaglini@arm.com#endif 46012569Sgiacomo.travaglini@arm.com 46112569Sgiacomo.travaglini@arm.com switch (unflattenMiscReg(misc_reg)) { 46212569Sgiacomo.travaglini@arm.com case MISCREG_HCR: 46312569Sgiacomo.travaglini@arm.com { 46412569Sgiacomo.travaglini@arm.com if (!haveVirtualization) 46512569Sgiacomo.travaglini@arm.com return 0; 46612569Sgiacomo.travaglini@arm.com else 46712569Sgiacomo.travaglini@arm.com return readMiscRegNoEffect(MISCREG_HCR); 46812569Sgiacomo.travaglini@arm.com } 46912569Sgiacomo.travaglini@arm.com case MISCREG_CPACR: 47012569Sgiacomo.travaglini@arm.com { 47112569Sgiacomo.travaglini@arm.com const uint32_t ones = (uint32_t)(-1); 47212569Sgiacomo.travaglini@arm.com CPACR cpacrMask = 0; 47312569Sgiacomo.travaglini@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 47412569Sgiacomo.travaglini@arm.com // be readable? (straight copy from the write code) 47512569Sgiacomo.travaglini@arm.com cpacrMask.cp10 = ones; 47612569Sgiacomo.travaglini@arm.com cpacrMask.cp11 = ones; 47710037SARM gem5 Developers cpacrMask.asedis = ones; 47810037SARM gem5 Developers 47910037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 48010037SARM gem5 Developers if (haveSecurity) { 48110037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 48210037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 4836735Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 4848782Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 4858782Sgblack@eecs.umich.edu // NB: Skipping the full loop, here 4866735Sgblack@eecs.umich.edu if (!nsacr.cp10) cpacrMask.cp10 = 0; 4876019Shines@cs.fsu.edu if (!nsacr.cp11) cpacrMask.cp11 = 0; 4886735Sgblack@eecs.umich.edu } 48910037SARM gem5 Developers } 4908303SAli.Saidi@ARM.com RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 49110338SCurtis.Dunham@arm.com val &= cpacrMask; 49210338SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49310338SCurtis.Dunham@arm.com miscRegName[misc_reg], val); 49410338SCurtis.Dunham@arm.com return val; 4958303SAli.Saidi@ARM.com } 4967720Sgblack@eecs.umich.edu case MISCREG_MPIDR: 4978205SAli.Saidi@ARM.com case MISCREG_MPIDR_EL1: 4988205SAli.Saidi@ARM.com return readMPIDR(system, tc); 4998205SAli.Saidi@ARM.com case MISCREG_VMPIDR: 5006735Sgblack@eecs.umich.edu case MISCREG_VMPIDR_EL2: 50110037SARM gem5 Developers // top bit defined as RES1 50210037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 50310037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 50410037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 50512398Sgiacomo.travaglini@arm.com case MISCREG_MIDR: 50610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 50810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 51010037SARM gem5 Developers } else { 51110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 51210037SARM gem5 Developers } 51310037SARM gem5 Developers break; 51410037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 51510037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 51610037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 51710037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 51812569Sgiacomo.travaglini@arm.com case MISCREG_TCMTR: // No TCM's 51912569Sgiacomo.travaglini@arm.com return 0; 52012569Sgiacomo.travaglini@arm.com 52110037SARM gem5 Developers case MISCREG_CLIDR: 52210037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 52310037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 52410037SARM gem5 Developers "ARM implementations.\n"); 52510037SARM gem5 Developers return 0x00200000; 52610037SARM gem5 Developers case MISCREG_CCSIDR: 52710037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 52810037SARM gem5 Developers "always reads as 0.\n"); 52910037SARM gem5 Developers break; 53010037SARM gem5 Developers case MISCREG_CTR: // AArch32, ARMv7, top bit set 53110037SARM gem5 Developers case MISCREG_CTR_EL0: // AArch64 53210037SARM gem5 Developers { 53310037SARM gem5 Developers //all caches have the same line size in gem5 53410037SARM gem5 Developers //4 byte words in ARM 53510037SARM gem5 Developers unsigned lineSizeWords = 53610037SARM gem5 Developers tc->getSystemPtr()->cacheLineSize() / 4; 53710037SARM gem5 Developers unsigned log2LineSizeWords = 0; 53810037SARM gem5 Developers 53910037SARM gem5 Developers while (lineSizeWords >>= 1) { 54010037SARM gem5 Developers ++log2LineSizeWords; 54110037SARM gem5 Developers } 54210037SARM gem5 Developers 54310037SARM gem5 Developers CTR ctr = 0; 54410037SARM gem5 Developers //log2 of minimun i-cache line size (words) 5456735Sgblack@eecs.umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5466735Sgblack@eecs.umich.edu //b11 - gem5 uses pipt 5476735Sgblack@eecs.umich.edu ctr.l1IndexPolicy = 0x3; 54810037SARM gem5 Developers //log2 of minimum d-cache line size (words) 5498518Sgeoffrey.blake@arm.com ctr.dCacheLineSize = log2LineSizeWords; 5508518Sgeoffrey.blake@arm.com //log2 of max reservation size (words) 5516735Sgblack@eecs.umich.edu ctr.erg = log2LineSizeWords; 55210037SARM gem5 Developers //log2 of max writeback size (words) 55310037SARM gem5 Developers ctr.cwg = log2LineSizeWords; 55410037SARM gem5 Developers //b100 - gem5 format is ARMv7 55510037SARM gem5 Developers ctr.format = 0x4; 55610037SARM gem5 Developers 55710037SARM gem5 Developers return ctr; 55810037SARM gem5 Developers } 55910037SARM gem5 Developers case MISCREG_ACTLR: 56010037SARM gem5 Developers warn("Not doing anything for miscreg ACTLR\n"); 56110037SARM gem5 Developers break; 56210037SARM gem5 Developers 56310037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 5646735Sgblack@eecs.umich.edu case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 5656735Sgblack@eecs.umich.edu case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 5666735Sgblack@eecs.umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 5676735Sgblack@eecs.umich.edu return pmu->readMiscReg(misc_reg); 5686735Sgblack@eecs.umich.edu 5696735Sgblack@eecs.umich.edu case MISCREG_CPSR_Q: 5706735Sgblack@eecs.umich.edu panic("shouldn't be reading this register seperately\n"); 5716735Sgblack@eecs.umich.edu case MISCREG_FPSCR_QC: 5726735Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 57310037SARM gem5 Developers case MISCREG_FPSCR_EXC: 57410037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 57510037SARM gem5 Developers case MISCREG_FPSR: 5766735Sgblack@eecs.umich.edu { 5776735Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 5786735Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 5796735Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 58010037SARM gem5 Developers fpscrMask.dzc = ones; 58110037SARM gem5 Developers fpscrMask.ofc = ones; 58210037SARM gem5 Developers fpscrMask.ufc = ones; 58310037SARM gem5 Developers fpscrMask.ixc = ones; 58410037SARM gem5 Developers fpscrMask.idc = ones; 58510037SARM gem5 Developers fpscrMask.qc = ones; 58612589Snikos.nikoleris@arm.com fpscrMask.v = ones; 58710037SARM gem5 Developers fpscrMask.c = ones; 58810037SARM gem5 Developers fpscrMask.z = ones; 58910037SARM gem5 Developers fpscrMask.n = ones; 5906735Sgblack@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 5916735Sgblack@eecs.umich.edu } 5927093Sgblack@eecs.umich.edu case MISCREG_FPCR: 5937093Sgblack@eecs.umich.edu { 5947720Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 5957585SAli.Saidi@arm.com FPSCR fpscrMask = 0; 5967720Sgblack@eecs.umich.edu fpscrMask.len = ones; 5977720Sgblack@eecs.umich.edu fpscrMask.fz16 = ones; 5987720Sgblack@eecs.umich.edu fpscrMask.stride = ones; 5997720Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 6007720Sgblack@eecs.umich.edu fpscrMask.fz = ones; 6017720Sgblack@eecs.umich.edu fpscrMask.dn = ones; 60210037SARM gem5 Developers fpscrMask.ahp = ones; 60310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 6047720Sgblack@eecs.umich.edu } 6056019Shines@cs.fsu.edu case MISCREG_NZCV: 6067189Sgblack@eecs.umich.edu { 6077400SAli.Saidi@ARM.com CPSR cpsr = 0; 60810417Sandreas.hansson@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 60910037SARM gem5 Developers cpsr.c = tc->readCCReg(CCREG_C); 61010037SARM gem5 Developers cpsr.v = tc->readCCReg(CCREG_V); 61110037SARM gem5 Developers return cpsr; 61210037SARM gem5 Developers } 61310037SARM gem5 Developers case MISCREG_DAIF: 61410037SARM gem5 Developers { 61510037SARM gem5 Developers CPSR cpsr = 0; 61610037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 61711574SCurtis.Dunham@arm.com return cpsr; 61811574SCurtis.Dunham@arm.com } 61911574SCurtis.Dunham@arm.com case MISCREG_SP_EL0: 62011574SCurtis.Dunham@arm.com { 62111574SCurtis.Dunham@arm.com return tc->readIntReg(INTREG_SP0); 62210037SARM gem5 Developers } 62310037SARM gem5 Developers case MISCREG_SP_EL1: 62410037SARM gem5 Developers { 62510037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 62610037SARM gem5 Developers } 62710037SARM gem5 Developers case MISCREG_SP_EL2: 62810037SARM gem5 Developers { 62910037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 63010037SARM gem5 Developers } 63110037SARM gem5 Developers case MISCREG_SPSEL: 63210037SARM gem5 Developers { 63310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 63410037SARM gem5 Developers } 63510338SCurtis.Dunham@arm.com case MISCREG_CURRENTEL: 63610338SCurtis.Dunham@arm.com { 63710338SCurtis.Dunham@arm.com return miscRegs[MISCREG_CPSR] & 0xc; 63810037SARM gem5 Developers } 63910037SARM gem5 Developers case MISCREG_L2CTLR: 64010037SARM gem5 Developers { 64110037SARM gem5 Developers // mostly unimplemented, just set NumCPUs field from sim and return 64210037SARM gem5 Developers L2CTLR l2ctlr = 0; 64310037SARM gem5 Developers // b00:1CPU to b11:4CPUs 64410037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 64510037SARM gem5 Developers return l2ctlr; 64610037SARM gem5 Developers } 64710037SARM gem5 Developers case MISCREG_DBGDIDR: 64810338SCurtis.Dunham@arm.com /* For now just implement the version number. 64910037SARM gem5 Developers * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 65010037SARM gem5 Developers */ 65110037SARM gem5 Developers return 0x5 << 16; 65210037SARM gem5 Developers case MISCREG_DBGDSCRint: 65310037SARM gem5 Developers return 0; 65410037SARM gem5 Developers case MISCREG_ISR: 65510037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 65610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 65710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 65810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 65910037SARM gem5 Developers case MISCREG_ISR_EL1: 66010037SARM gem5 Developers return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 66110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 66210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 66310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 66410037SARM gem5 Developers case MISCREG_DCZID_EL0: 66510037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 66610037SARM gem5 Developers case MISCREG_HCPTR: 66712511Schuan.zhu@arm.com { 66812511Schuan.zhu@arm.com RegVal val = readMiscRegNoEffect(misc_reg); 66910037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 67010037SARM gem5 Developers val &= ~(1 << 14); 67110037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 67210037SARM gem5 Developers // HCPTR is RAO/WI 67310037SARM gem5 Developers bool secure_lookup = haveSecurity && 67410037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 67510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 67610037SARM gem5 Developers if (!secure_lookup) { 67710037SARM gem5 Developers RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 67810037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 67910037SARM gem5 Developers } 68010037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 68112511Schuan.zhu@arm.com val |= 0x33FF; 68210037SARM gem5 Developers return (val); 68310037SARM gem5 Developers } 68410037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 68510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 68610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 68710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 68810037SARM gem5 Developers 68910037SARM gem5 Developers case MISCREG_ID_PFR0: 69010037SARM gem5 Developers // !ThumbEE | !Jazelle | Thumb | ARM 69110037SARM gem5 Developers return 0x00000031; 69210037SARM gem5 Developers case MISCREG_ID_PFR1: 69312398Sgiacomo.travaglini@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 69410037SARM gem5 Developers bool haveTimer = (system->getGenericTimer() != NULL); 69510037SARM gem5 Developers return 0x00000001 69610037SARM gem5 Developers | (haveSecurity ? 0x00000010 : 0x0) 69710037SARM gem5 Developers | (haveVirtualization ? 0x00001000 : 0x0) 69810037SARM gem5 Developers | (haveTimer ? 0x00010000 : 0x0); 69910037SARM gem5 Developers } 70010417Sandreas.hansson@arm.com case MISCREG_ID_AA64PFR0_EL1: 7017400SAli.Saidi@ARM.com return 0x0000000000000002 | // AArch{64,32} supported at EL0 7028782Sgblack@eecs.umich.edu 0x0000000000000020 | // EL1 70311150Smitch.hayenga@arm.com (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 7048782Sgblack@eecs.umich.edu (haveSecurity ? 0x0000000000002000 : 0) | // EL3 7058782Sgblack@eecs.umich.edu (haveSVE ? 0x0000000100000000 : 0) | // SVE 70610037SARM gem5 Developers (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 70710037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 70810037SARM gem5 Developers return 0; // bits [63:0] RES0 (reserved for future use) 70910037SARM gem5 Developers 71010037SARM gem5 Developers // Generic Timer registers 71110037SARM gem5 Developers case MISCREG_CNTHV_CTL_EL2: 71210037SARM gem5 Developers case MISCREG_CNTHV_CVAL_EL2: 71310037SARM gem5 Developers case MISCREG_CNTHV_TVAL_EL2: 71410037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 71510037SARM gem5 Developers case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 71610037SARM gem5 Developers case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 71710037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 71810037SARM gem5 Developers return getGenericTimer(tc).readMiscReg(misc_reg); 71910037SARM gem5 Developers 72010037SARM gem5 Developers case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 72110037SARM gem5 Developers case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 72210037SARM gem5 Developers return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 72310037SARM gem5 Developers 72410037SARM gem5 Developers default: 7257400SAli.Saidi@ARM.com break; 7267400SAli.Saidi@ARM.com 7277189Sgblack@eecs.umich.edu } 72810417Sandreas.hansson@arm.com return readMiscRegNoEffect(misc_reg); 7297189Sgblack@eecs.umich.edu} 7308782Sgblack@eecs.umich.edu 7318782Sgblack@eecs.umich.eduvoid 7328806Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, RegVal val) 7338806Sgblack@eecs.umich.edu{ 7348806Sgblack@eecs.umich.edu assert(misc_reg < NumMiscRegs); 7358806Sgblack@eecs.umich.edu 7368806Sgblack@eecs.umich.edu const auto ® = lookUpMiscReg[misc_reg]; // bit masks 7378806Sgblack@eecs.umich.edu const auto &map = getMiscIndices(misc_reg); 7388806Sgblack@eecs.umich.edu int lower = map.first, upper = map.second; 7398806Sgblack@eecs.umich.edu 7408806Sgblack@eecs.umich.edu auto v = (val & ~reg.wi()) | reg.rao(); 7418806Sgblack@eecs.umich.edu if (upper > 0) { 7428806Sgblack@eecs.umich.edu miscRegs[lower] = bits(v, 31, 0); 7437189Sgblack@eecs.umich.edu miscRegs[upper] = bits(v, 63, 32); 7448806Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 7458806Sgblack@eecs.umich.edu misc_reg, lower, upper, v); 7467189Sgblack@eecs.umich.edu } else { 7477189Sgblack@eecs.umich.edu miscRegs[lower] = v; 7487189Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 74910037SARM gem5 Developers misc_reg, lower, v); 75010037SARM gem5 Developers } 75110037SARM gem5 Developers} 75210037SARM gem5 Developers 75310037SARM gem5 Developersvoid 75410037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 75510037SARM gem5 Developers{ 75610037SARM gem5 Developers 75710037SARM gem5 Developers RegVal newVal = val; 75810037SARM gem5 Developers bool secure_lookup; 75910037SARM gem5 Developers SCR scr; 76010037SARM gem5 Developers 76110037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 76210037SARM gem5 Developers updateRegMap(val); 76310037SARM gem5 Developers 76410037SARM gem5 Developers 76510037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 76610037SARM gem5 Developers int old_mode = old_cpsr.mode; 76710037SARM gem5 Developers CPSR cpsr = val; 76812402Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 76912402Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 77012402Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 77112402Sgiacomo.travaglini@arm.com } 77212402Sgiacomo.travaglini@arm.com 77312402Sgiacomo.travaglini@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 77410037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 77510037SARM gem5 Developers PCState pc = tc->pcState(); 77610037SARM gem5 Developers pc.nextThumb(cpsr.t); 77710037SARM gem5 Developers pc.nextJazelle(cpsr.j); 77810037SARM gem5 Developers pc.illegalExec(cpsr.il == 1); 77910037SARM gem5 Developers 78010037SARM gem5 Developers tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 78110037SARM gem5 Developers 78210037SARM gem5 Developers // Follow slightly different semantics if a CheckerCPU object 78310037SARM gem5 Developers // is connected 78410037SARM gem5 Developers CheckerCPU *checker = tc->getCheckerCpuPtr(); 78510037SARM gem5 Developers if (checker) { 78610037SARM gem5 Developers tc->pcStateNoRecord(pc); 78710037SARM gem5 Developers } else { 78810037SARM gem5 Developers tc->pcState(pc); 78910037SARM gem5 Developers } 79010037SARM gem5 Developers } else { 79110037SARM gem5 Developers#ifndef NDEBUG 79210037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 79310037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 7947197Sgblack@eecs.umich.edu warn("Unimplemented system register %s write with %#x.\n", 79510417Sandreas.hansson@arm.com miscRegName[misc_reg], val); 7967197Sgblack@eecs.umich.edu else 7978782Sgblack@eecs.umich.edu panic("Unimplemented system register %s write with %#x.\n", 7988782Sgblack@eecs.umich.edu miscRegName[misc_reg], val); 7998806Sgblack@eecs.umich.edu } 8008806Sgblack@eecs.umich.edu#endif 8017197Sgblack@eecs.umich.edu switch (unflattenMiscReg(misc_reg)) { 8028806Sgblack@eecs.umich.edu case MISCREG_CPACR: 8038806Sgblack@eecs.umich.edu { 8048806Sgblack@eecs.umich.edu 80510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 80610037SARM gem5 Developers CPACR cpacrMask = 0; 80710037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 80810037SARM gem5 Developers // be writable 80910037SARM gem5 Developers cpacrMask.cp10 = ones; 81010037SARM gem5 Developers cpacrMask.cp11 = ones; 81111877Sbrandon.potter@amd.com cpacrMask.asedis = ones; 81211877Sbrandon.potter@amd.com 8138806Sgblack@eecs.umich.edu // Security Extensions may limit the writability of CPACR 8148806Sgblack@eecs.umich.edu if (haveSecurity) { 8158806Sgblack@eecs.umich.edu scr = readMiscRegNoEffect(MISCREG_SCR); 8168806Sgblack@eecs.umich.edu CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 8178806Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 8188806Sgblack@eecs.umich.edu NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 8197197Sgblack@eecs.umich.edu // NB: Skipping the full loop, here 8207197Sgblack@eecs.umich.edu if (!nsacr.cp10) cpacrMask.cp10 = 0; 82110037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 82210037SARM gem5 Developers } 82310037SARM gem5 Developers } 82410037SARM gem5 Developers 82510037SARM gem5 Developers RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 82610037SARM gem5 Developers newVal &= cpacrMask; 82710037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 82810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 82910037SARM gem5 Developers miscRegName[misc_reg], newVal); 83010037SARM gem5 Developers } 83110037SARM gem5 Developers break; 83210037SARM gem5 Developers case MISCREG_CPACR_EL1: 83310037SARM gem5 Developers { 83410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 83510037SARM gem5 Developers CPACR cpacrMask = 0; 83610037SARM gem5 Developers cpacrMask.tta = ones; 83710037SARM gem5 Developers cpacrMask.fpen = ones; 83810037SARM gem5 Developers if (haveSVE) { 83910037SARM gem5 Developers cpacrMask.zen = ones; 84010037SARM gem5 Developers } 84110037SARM gem5 Developers newVal &= cpacrMask; 84210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 84310037SARM gem5 Developers miscRegName[misc_reg], newVal); 84410037SARM gem5 Developers } 84510037SARM gem5 Developers break; 84610037SARM gem5 Developers case MISCREG_CPTR_EL2: 84710037SARM gem5 Developers { 84810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 84910037SARM gem5 Developers CPTR cptrMask = 0; 85010037SARM gem5 Developers cptrMask.tcpac = ones; 85110037SARM gem5 Developers cptrMask.tta = ones; 85210037SARM gem5 Developers cptrMask.tfp = ones; 85310037SARM gem5 Developers if (haveSVE) { 85410037SARM gem5 Developers cptrMask.tz = ones; 85510037SARM gem5 Developers } 85610037SARM gem5 Developers newVal &= cptrMask; 85710037SARM gem5 Developers cptrMask = 0; 85810037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 85910037SARM gem5 Developers cptrMask.res1_7_0_el2 = ones; 86010037SARM gem5 Developers if (!haveSVE) { 86110037SARM gem5 Developers cptrMask.res1_8_el2 = ones; 86210037SARM gem5 Developers } 86312402Sgiacomo.travaglini@arm.com cptrMask.res1_9_el2 = ones; 86412402Sgiacomo.travaglini@arm.com newVal |= cptrMask; 86512402Sgiacomo.travaglini@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 86612402Sgiacomo.travaglini@arm.com miscRegName[misc_reg], newVal); 86712402Sgiacomo.travaglini@arm.com } 86812402Sgiacomo.travaglini@arm.com break; 86910037SARM gem5 Developers case MISCREG_CPTR_EL3: 87010037SARM gem5 Developers { 87110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87210037SARM gem5 Developers CPTR cptrMask = 0; 87310037SARM gem5 Developers cptrMask.tcpac = ones; 87410037SARM gem5 Developers cptrMask.tta = ones; 87510037SARM gem5 Developers cptrMask.tfp = ones; 87610037SARM gem5 Developers if (haveSVE) { 87711576SDylan.Johnson@ARM.com cptrMask.ez = ones; 87811576SDylan.Johnson@ARM.com } 87911576SDylan.Johnson@ARM.com newVal &= cptrMask; 88011576SDylan.Johnson@ARM.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 88111576SDylan.Johnson@ARM.com miscRegName[misc_reg], newVal); 88211576SDylan.Johnson@ARM.com } 88310037SARM gem5 Developers break; 88410037SARM gem5 Developers case MISCREG_CSSELR: 88510037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 88610037SARM gem5 Developers return; 88710037SARM gem5 Developers 88810037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 88910037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 89010037SARM gem5 Developers return; 89110037SARM gem5 Developers 89210037SARM gem5 Developers case MISCREG_FPSCR: 89310037SARM gem5 Developers { 89410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89510037SARM gem5 Developers FPSCR fpscrMask = 0; 89610037SARM gem5 Developers fpscrMask.ioc = ones; 89710037SARM gem5 Developers fpscrMask.dzc = ones; 89810037SARM gem5 Developers fpscrMask.ofc = ones; 89910037SARM gem5 Developers fpscrMask.ufc = ones; 90010037SARM gem5 Developers fpscrMask.ixc = ones; 90110037SARM gem5 Developers fpscrMask.idc = ones; 90210037SARM gem5 Developers fpscrMask.ioe = ones; 90310037SARM gem5 Developers fpscrMask.dze = ones; 90410037SARM gem5 Developers fpscrMask.ofe = ones; 90510037SARM gem5 Developers fpscrMask.ufe = ones; 90610037SARM gem5 Developers fpscrMask.ixe = ones; 90710037SARM gem5 Developers fpscrMask.ide = ones; 90812511Schuan.zhu@arm.com fpscrMask.len = ones; 90912511Schuan.zhu@arm.com fpscrMask.fz16 = ones; 91012511Schuan.zhu@arm.com fpscrMask.stride = ones; 91112511Schuan.zhu@arm.com fpscrMask.rMode = ones; 91212511Schuan.zhu@arm.com fpscrMask.fz = ones; 91312511Schuan.zhu@arm.com fpscrMask.dn = ones; 91412511Schuan.zhu@arm.com fpscrMask.ahp = ones; 91512511Schuan.zhu@arm.com fpscrMask.qc = ones; 91612511Schuan.zhu@arm.com fpscrMask.v = ones; 91712511Schuan.zhu@arm.com fpscrMask.c = ones; 91812511Schuan.zhu@arm.com fpscrMask.z = ones; 91912511Schuan.zhu@arm.com fpscrMask.n = ones; 92012511Schuan.zhu@arm.com newVal = (newVal & (uint32_t)fpscrMask) | 92112511Schuan.zhu@arm.com (readMiscRegNoEffect(MISCREG_FPSCR) & 92212511Schuan.zhu@arm.com ~(uint32_t)fpscrMask); 92312511Schuan.zhu@arm.com tc->getDecoderPtr()->setContext(newVal); 92412511Schuan.zhu@arm.com } 92512511Schuan.zhu@arm.com break; 92612511Schuan.zhu@arm.com case MISCREG_FPSR: 92712511Schuan.zhu@arm.com { 92812511Schuan.zhu@arm.com const uint32_t ones = (uint32_t)(-1); 92912511Schuan.zhu@arm.com FPSCR fpscrMask = 0; 93012511Schuan.zhu@arm.com fpscrMask.ioc = ones; 93112511Schuan.zhu@arm.com fpscrMask.dzc = ones; 93212511Schuan.zhu@arm.com fpscrMask.ofc = ones; 93310037SARM gem5 Developers fpscrMask.ufc = ones; 93410037SARM gem5 Developers fpscrMask.ixc = ones; 93510037SARM gem5 Developers fpscrMask.idc = ones; 93610037SARM gem5 Developers fpscrMask.qc = ones; 93710037SARM gem5 Developers fpscrMask.v = ones; 93810037SARM gem5 Developers fpscrMask.c = ones; 93910037SARM gem5 Developers fpscrMask.z = ones; 94010037SARM gem5 Developers fpscrMask.n = ones; 94110037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 94210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 94310037SARM gem5 Developers ~(uint32_t)fpscrMask); 94410037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 94510037SARM gem5 Developers } 94610037SARM gem5 Developers break; 94710037SARM gem5 Developers case MISCREG_FPCR: 94810037SARM gem5 Developers { 94910417Sandreas.hansson@arm.com const uint32_t ones = (uint32_t)(-1); 95010037SARM gem5 Developers FPSCR fpscrMask = 0; 95110037SARM gem5 Developers fpscrMask.len = ones; 95210037SARM gem5 Developers fpscrMask.fz16 = ones; 95310037SARM gem5 Developers fpscrMask.stride = ones; 95410037SARM gem5 Developers fpscrMask.rMode = ones; 95510037SARM gem5 Developers fpscrMask.fz = ones; 95610037SARM gem5 Developers fpscrMask.dn = ones; 95710037SARM gem5 Developers fpscrMask.ahp = ones; 95810037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 95910037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 96010037SARM gem5 Developers ~(uint32_t)fpscrMask); 96110037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 96210037SARM gem5 Developers } 96312509Schuan.zhu@arm.com break; 96412509Schuan.zhu@arm.com case MISCREG_CPSR_Q: 96512509Schuan.zhu@arm.com { 96612509Schuan.zhu@arm.com assert(!(newVal & ~CpsrMaskQ)); 96712509Schuan.zhu@arm.com newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 96812509Schuan.zhu@arm.com misc_reg = MISCREG_CPSR; 96912509Schuan.zhu@arm.com } 97012509Schuan.zhu@arm.com break; 97112509Schuan.zhu@arm.com case MISCREG_FPSCR_QC: 97212509Schuan.zhu@arm.com { 97312509Schuan.zhu@arm.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 97412509Schuan.zhu@arm.com (newVal & FpscrQcMask); 97512509Schuan.zhu@arm.com misc_reg = MISCREG_FPSCR; 97612509Schuan.zhu@arm.com } 97712509Schuan.zhu@arm.com break; 97812509Schuan.zhu@arm.com case MISCREG_FPSCR_EXC: 97912509Schuan.zhu@arm.com { 98012509Schuan.zhu@arm.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 98112509Schuan.zhu@arm.com (newVal & FpscrExcMask); 98212509Schuan.zhu@arm.com misc_reg = MISCREG_FPSCR; 98312509Schuan.zhu@arm.com } 98412509Schuan.zhu@arm.com break; 98512509Schuan.zhu@arm.com case MISCREG_FPEXC: 98612509Schuan.zhu@arm.com { 98710037SARM gem5 Developers // vfpv3 architecture, section B.6.1 of DDI04068 98810037SARM gem5 Developers // bit 29 - valid only if fpexc[31] is 0 98910037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 99012509Schuan.zhu@arm.com newVal = (newVal & fpexcMask) | 99112509Schuan.zhu@arm.com (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 99212509Schuan.zhu@arm.com } 99312509Schuan.zhu@arm.com break; 99410037SARM gem5 Developers case MISCREG_HCR: 99510037SARM gem5 Developers { 99610037SARM gem5 Developers if (!haveVirtualization) 99710037SARM gem5 Developers return; 99810037SARM gem5 Developers } 99910037SARM gem5 Developers break; 100010037SARM gem5 Developers case MISCREG_IFSR: 100110037SARM gem5 Developers { 100210037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 10037362Sgblack@eecs.umich.edu const uint32_t ifsrMask = 10047362Sgblack@eecs.umich.edu mask(31, 13) | mask(11, 11) | mask(8, 6); 100510417Sandreas.hansson@arm.com newVal = newVal & ~ifsrMask; 10067362Sgblack@eecs.umich.edu } 100710037SARM gem5 Developers break; 100810037SARM gem5 Developers case MISCREG_DFSR: 100910037SARM gem5 Developers { 101010037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 101110037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 101210037SARM gem5 Developers newVal = newVal & ~dfsrMask; 101310037SARM gem5 Developers } 101410037SARM gem5 Developers break; 101510037SARM gem5 Developers case MISCREG_AMAIR0: 101610037SARM gem5 Developers case MISCREG_AMAIR1: 101710037SARM gem5 Developers { 101810037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 101910037SARM gem5 Developers // Valid only with LPAE 102010037SARM gem5 Developers if (!haveLPAE) 102110037SARM gem5 Developers return; 102210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 102310037SARM gem5 Developers } 102410037SARM gem5 Developers break; 102510037SARM gem5 Developers case MISCREG_SCR: 102610037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 102710037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 102810037SARM gem5 Developers break; 102910037SARM gem5 Developers case MISCREG_SCTLR: 103011150Smitch.hayenga@arm.com { 103110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 103210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 103310037SARM gem5 Developers 103410037SARM gem5 Developers MiscRegIndex sctlr_idx; 103510037SARM gem5 Developers if (haveSecurity && !highestELIs64 && !scr.ns) { 103610037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_S; 10378205SAli.Saidi@ARM.com } else { 103810037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_NS; 103911496Sandreas.sandberg@arm.com } 104012570Sgiacomo.travaglini@arm.com 104110037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 104210037SARM gem5 Developers SCTLR new_sctlr = newVal; 104310037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 104410037SARM gem5 Developers miscRegs[sctlr_idx] = (RegVal)new_sctlr; 104510037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 104610037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 104710037SARM gem5 Developers } 104810037SARM gem5 Developers case MISCREG_MIDR: 104910037SARM gem5 Developers case MISCREG_ID_PFR0: 105010037SARM gem5 Developers case MISCREG_ID_PFR1: 105110037SARM gem5 Developers case MISCREG_ID_DFR0: 105210037SARM gem5 Developers case MISCREG_ID_MMFR0: 105310037SARM gem5 Developers case MISCREG_ID_MMFR1: 105410037SARM gem5 Developers case MISCREG_ID_MMFR2: 105511585SDylan.Johnson@ARM.com case MISCREG_ID_MMFR3: 105611585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR0: 105711585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR1: 105811585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR2: 105911585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR3: 106011585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR4: 106111585SDylan.Johnson@ARM.com case MISCREG_ID_ISAR5: 106211585SDylan.Johnson@ARM.com 106311585SDylan.Johnson@ARM.com case MISCREG_MPIDR: 106411585SDylan.Johnson@ARM.com case MISCREG_FPSID: 106511585SDylan.Johnson@ARM.com case MISCREG_TLBTR: 106610037SARM gem5 Developers case MISCREG_MVFR0: 106710037SARM gem5 Developers case MISCREG_MVFR1: 106810037SARM gem5 Developers 106910037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 107012570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64AFR1_EL1: 107112570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64DFR0_EL1: 107212570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64DFR1_EL1: 107312570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64ISAR0_EL1: 107412570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64ISAR1_EL1: 107512570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR0_EL1: 107612570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR1_EL1: 107712570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR2_EL1: 107812570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64PFR0_EL1: 107912570Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64PFR1_EL1: 108012570Sgiacomo.travaglini@arm.com // ID registers are constants. 108112570Sgiacomo.travaglini@arm.com return; 108212570Sgiacomo.travaglini@arm.com 108312570Sgiacomo.travaglini@arm.com // TLB Invalidate All 108412570Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 108512570Sgiacomo.travaglini@arm.com { 108612570Sgiacomo.travaglini@arm.com assert32(tc); 108712570Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 108812570Sgiacomo.travaglini@arm.com 108912570Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 109012570Sgiacomo.travaglini@arm.com tlbiOp(tc); 109112570Sgiacomo.travaglini@arm.com return; 109212570Sgiacomo.travaglini@arm.com } 109312570Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 109412570Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLIS: 109512570Sgiacomo.travaglini@arm.com { 109612570Sgiacomo.travaglini@arm.com assert32(tc); 109712570Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 109812570Sgiacomo.travaglini@arm.com 109912570Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 110012570Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 110112570Sgiacomo.travaglini@arm.com return; 110212570Sgiacomo.travaglini@arm.com } 110312570Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 110412570Sgiacomo.travaglini@arm.com case MISCREG_ITLBIALL: 110512570Sgiacomo.travaglini@arm.com { 110612570Sgiacomo.travaglini@arm.com assert32(tc); 110710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 110812570Sgiacomo.travaglini@arm.com 110910037SARM gem5 Developers ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 11107362Sgblack@eecs.umich.edu tlbiOp(tc); 11118314Sgeoffrey.blake@arm.com return; 111212570Sgiacomo.travaglini@arm.com } 111312570Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 111412570Sgiacomo.travaglini@arm.com case MISCREG_DTLBIALL: 111512570Sgiacomo.travaglini@arm.com { 111612570Sgiacomo.travaglini@arm.com assert32(tc); 111712570Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 111812570Sgiacomo.travaglini@arm.com 111910037SARM gem5 Developers DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 112012570Sgiacomo.travaglini@arm.com tlbiOp(tc); 112112570Sgiacomo.travaglini@arm.com return; 112212570Sgiacomo.travaglini@arm.com } 112310037SARM gem5 Developers // TLB Invalidate by VA 112412570Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 112512570Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 112612570Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 112712570Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 112810037SARM gem5 Developers case MISCREG_TLBIMVAL: 112910037SARM gem5 Developers { 113010037SARM gem5 Developers assert32(tc); 113110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 113210037SARM gem5 Developers 113310037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 113410037SARM gem5 Developers haveSecurity && !scr.ns, 113510037SARM gem5 Developers mbits(newVal, 31, 12), 113610037SARM gem5 Developers bits(newVal, 7,0)); 113710037SARM gem5 Developers 113810037SARM gem5 Developers tlbiOp(tc); 113910037SARM gem5 Developers return; 114010037SARM gem5 Developers } 114110037SARM gem5 Developers // TLB Invalidate by VA, Inner Shareable 114210037SARM gem5 Developers case MISCREG_TLBIMVAIS: 114310037SARM gem5 Developers case MISCREG_TLBIMVALIS: 114410037SARM gem5 Developers { 114510037SARM gem5 Developers assert32(tc); 114610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 114710037SARM gem5 Developers 114810037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 114910037SARM gem5 Developers haveSecurity && !scr.ns, 115010037SARM gem5 Developers mbits(newVal, 31, 12), 115110037SARM gem5 Developers bits(newVal, 7,0)); 115210037SARM gem5 Developers 115310037SARM gem5 Developers tlbiOp.broadcast(tc); 115410037SARM gem5 Developers return; 115510037SARM gem5 Developers } 115610037SARM gem5 Developers // TLB Invalidate by ASID match 115710037SARM gem5 Developers case MISCREG_TLBIASID: 115810037SARM gem5 Developers { 115910037SARM gem5 Developers assert32(tc); 116010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 116110037SARM gem5 Developers 116210037SARM gem5 Developers TLBIASID tlbiOp(EL1, 116310037SARM gem5 Developers haveSecurity && !scr.ns, 116410037SARM gem5 Developers bits(newVal, 7,0)); 116510037SARM gem5 Developers 116610037SARM gem5 Developers tlbiOp(tc); 116710037SARM gem5 Developers return; 116810037SARM gem5 Developers } 116910037SARM gem5 Developers // TLB Invalidate by ASID match, Inner Shareable 117010037SARM gem5 Developers case MISCREG_TLBIASIDIS: 117110037SARM gem5 Developers { 117210037SARM gem5 Developers assert32(tc); 117310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117410037SARM gem5 Developers 117510037SARM gem5 Developers TLBIASID tlbiOp(EL1, 117610037SARM gem5 Developers haveSecurity && !scr.ns, 117710037SARM gem5 Developers bits(newVal, 7,0)); 117810037SARM gem5 Developers 117910037SARM gem5 Developers tlbiOp.broadcast(tc); 118010037SARM gem5 Developers return; 118110037SARM gem5 Developers } 118210037SARM gem5 Developers // mcr tlbimvaal(is) is invalidating all matching entries 118310037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 118410037SARM gem5 Developers // in the tlb the last level of lookup only. 118510037SARM gem5 Developers // TLB Invalidate by VA, All ASID 118610037SARM gem5 Developers case MISCREG_TLBIMVAA: 118710037SARM gem5 Developers case MISCREG_TLBIMVAAL: 118810037SARM gem5 Developers { 118910037SARM gem5 Developers assert32(tc); 119010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 119110037SARM gem5 Developers 119210037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 119310037SARM gem5 Developers mbits(newVal, 31,12), false); 119410037SARM gem5 Developers 119510037SARM gem5 Developers tlbiOp(tc); 119610037SARM gem5 Developers return; 119710037SARM gem5 Developers } 119810037SARM gem5 Developers // TLB Invalidate by VA, All ASID, Inner Shareable 119910037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 120010037SARM gem5 Developers case MISCREG_TLBIMVAALIS: 120110037SARM gem5 Developers { 120210037SARM gem5 Developers assert32(tc); 120310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 120410037SARM gem5 Developers 120510037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 120610037SARM gem5 Developers mbits(newVal, 31,12), false); 120710037SARM gem5 Developers 120810037SARM gem5 Developers tlbiOp.broadcast(tc); 120910037SARM gem5 Developers return; 121010037SARM gem5 Developers } 121110037SARM gem5 Developers // mcr tlbimvalh(is) is invalidating all matching entries 121210037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 121310037SARM gem5 Developers // in the tlb the last level of lookup only. 121410037SARM gem5 Developers // TLB Invalidate by VA, Hyp mode 121510037SARM gem5 Developers case MISCREG_TLBIMVAH: 121610037SARM gem5 Developers case MISCREG_TLBIMVALH: 121710037SARM gem5 Developers { 121810037SARM gem5 Developers assert32(tc); 121910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 122010037SARM gem5 Developers 122110037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 122210037SARM gem5 Developers mbits(newVal, 31,12), true); 122310037SARM gem5 Developers 122410037SARM gem5 Developers tlbiOp(tc); 122510037SARM gem5 Developers return; 122610037SARM gem5 Developers } 122710037SARM gem5 Developers // TLB Invalidate by VA, Hyp mode, Inner Shareable 122810037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 122910037SARM gem5 Developers case MISCREG_TLBIMVALHIS: 123010037SARM gem5 Developers { 123110037SARM gem5 Developers assert32(tc); 123210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123310037SARM gem5 Developers 123410037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 123510037SARM gem5 Developers mbits(newVal, 31,12), true); 123610037SARM gem5 Developers 123710037SARM gem5 Developers tlbiOp.broadcast(tc); 123810037SARM gem5 Developers return; 123910037SARM gem5 Developers } 124010037SARM gem5 Developers // mcr tlbiipas2l(is) is invalidating all matching entries 124110037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 124210037SARM gem5 Developers // in the tlb the last level of lookup only. 124311581SDylan.Johnson@ARM.com // TLB Invalidate by Intermediate Physical Address, Stage 2 124410037SARM gem5 Developers case MISCREG_TLBIIPAS2: 124510037SARM gem5 Developers case MISCREG_TLBIIPAS2L: 124610037SARM gem5 Developers { 124710037SARM gem5 Developers assert32(tc); 124810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 124910037SARM gem5 Developers 125010037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 125110037SARM gem5 Developers haveSecurity && !scr.ns, 125210037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 125310367SAndrew.Bardsley@arm.com 125410367SAndrew.Bardsley@arm.com tlbiOp(tc); 125510037SARM gem5 Developers return; 125610037SARM gem5 Developers } 125710037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2, 125810037SARM gem5 Developers // Inner Shareable 125910037SARM gem5 Developers case MISCREG_TLBIIPAS2IS: 126010037SARM gem5 Developers case MISCREG_TLBIIPAS2LIS: 126110037SARM gem5 Developers { 126210037SARM gem5 Developers assert32(tc); 126310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126410037SARM gem5 Developers 126510037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 126610037SARM gem5 Developers haveSecurity && !scr.ns, 126710037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 126810037SARM gem5 Developers 126910037SARM gem5 Developers tlbiOp.broadcast(tc); 127010037SARM gem5 Developers return; 127110037SARM gem5 Developers } 127210037SARM gem5 Developers // Instruction TLB Invalidate by VA 127310037SARM gem5 Developers case MISCREG_ITLBIMVA: 127410037SARM gem5 Developers { 127510037SARM gem5 Developers assert32(tc); 127610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127710037SARM gem5 Developers 127810037SARM gem5 Developers ITLBIMVA tlbiOp(EL1, 127910037SARM gem5 Developers haveSecurity && !scr.ns, 128010037SARM gem5 Developers mbits(newVal, 31, 12), 128110037SARM gem5 Developers bits(newVal, 7,0)); 128210037SARM gem5 Developers 128310037SARM gem5 Developers tlbiOp(tc); 128410037SARM gem5 Developers return; 128510037SARM gem5 Developers } 128610037SARM gem5 Developers // Data TLB Invalidate by VA 128710037SARM gem5 Developers case MISCREG_DTLBIMVA: 128810037SARM gem5 Developers { 128910037SARM gem5 Developers assert32(tc); 129010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 129110037SARM gem5 Developers 129210037SARM gem5 Developers DTLBIMVA tlbiOp(EL1, 129310037SARM gem5 Developers haveSecurity && !scr.ns, 129410037SARM gem5 Developers mbits(newVal, 31, 12), 129510037SARM gem5 Developers bits(newVal, 7,0)); 129610037SARM gem5 Developers 129710037SARM gem5 Developers tlbiOp(tc); 129810037SARM gem5 Developers return; 129910037SARM gem5 Developers } 130010037SARM gem5 Developers // Instruction TLB Invalidate by ASID match 130110037SARM gem5 Developers case MISCREG_ITLBIASID: 130210037SARM gem5 Developers { 130310037SARM gem5 Developers assert32(tc); 130410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 130510037SARM gem5 Developers 130610037SARM gem5 Developers ITLBIASID tlbiOp(EL1, 130710037SARM gem5 Developers haveSecurity && !scr.ns, 130810037SARM gem5 Developers bits(newVal, 7,0)); 130911581SDylan.Johnson@ARM.com 131010037SARM gem5 Developers tlbiOp(tc); 131110037SARM gem5 Developers return; 131210037SARM gem5 Developers } 131310037SARM gem5 Developers // Data TLB Invalidate by ASID match 131410037SARM gem5 Developers case MISCREG_DTLBIASID: 131510037SARM gem5 Developers { 131610037SARM gem5 Developers assert32(tc); 131710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 131810037SARM gem5 Developers 131910037SARM gem5 Developers DTLBIASID tlbiOp(EL1, 132010037SARM gem5 Developers haveSecurity && !scr.ns, 132110037SARM gem5 Developers bits(newVal, 7,0)); 132210037SARM gem5 Developers 132310037SARM gem5 Developers tlbiOp(tc); 132410037SARM gem5 Developers return; 132510037SARM gem5 Developers } 132610037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp 132710037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 132810037SARM gem5 Developers { 132910037SARM gem5 Developers assert32(tc); 133010037SARM gem5 Developers 133110037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 133210037SARM gem5 Developers tlbiOp(tc); 133310037SARM gem5 Developers return; 133410037SARM gem5 Developers } 133510037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 133610037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 133710037SARM gem5 Developers { 133810037SARM gem5 Developers assert32(tc); 133910037SARM gem5 Developers 134010037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 134110037SARM gem5 Developers tlbiOp.broadcast(tc); 134210037SARM gem5 Developers return; 134310037SARM gem5 Developers } 134410037SARM gem5 Developers // TLB Invalidate All, Hyp mode 134510037SARM gem5 Developers case MISCREG_TLBIALLH: 134610037SARM gem5 Developers { 134710037SARM gem5 Developers assert32(tc); 134810037SARM gem5 Developers 134910037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 135010037SARM gem5 Developers tlbiOp(tc); 135110037SARM gem5 Developers return; 135210037SARM gem5 Developers } 135310037SARM gem5 Developers // TLB Invalidate All, Hyp mode, Inner Shareable 135410037SARM gem5 Developers case MISCREG_TLBIALLHIS: 135510037SARM gem5 Developers { 135610037SARM gem5 Developers assert32(tc); 135710037SARM gem5 Developers 135810037SARM gem5 Developers TLBIALLN tlbiOp(EL1, true); 135910037SARM gem5 Developers tlbiOp.broadcast(tc); 136010037SARM gem5 Developers return; 136110037SARM gem5 Developers } 136210037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3 136310037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 136410037SARM gem5 Developers { 136510037SARM gem5 Developers assert64(tc); 136610037SARM gem5 Developers 136710037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 136810037SARM gem5 Developers tlbiOp(tc); 136910037SARM gem5 Developers return; 137010417Sandreas.hansson@arm.com } 137110037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3, Inner Shareable 137210037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 137310037SARM gem5 Developers { 137410037SARM gem5 Developers assert64(tc); 137510037SARM gem5 Developers 137610037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 137710037SARM gem5 Developers tlbiOp.broadcast(tc); 137810037SARM gem5 Developers return; 137910037SARM gem5 Developers } 138010037SARM gem5 Developers // AArch64 TLB Invalidate All, EL2, Inner Shareable 138110037SARM gem5 Developers case MISCREG_TLBI_ALLE2: 138210037SARM gem5 Developers case MISCREG_TLBI_ALLE2IS: 138310037SARM gem5 Developers { 138410037SARM gem5 Developers assert64(tc); 138510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 138610037SARM gem5 Developers 138710037SARM gem5 Developers TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 138810037SARM gem5 Developers tlbiOp(tc); 138910037SARM gem5 Developers return; 139010037SARM gem5 Developers } 139110037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1 139210037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 139310037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 139410037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 139510037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 139610037SARM gem5 Developers { 139710037SARM gem5 Developers assert64(tc); 139810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 139911581SDylan.Johnson@ARM.com 140010037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 140110037SARM gem5 Developers tlbiOp(tc); 140210037SARM gem5 Developers return; 140310037SARM gem5 Developers } 140410037SARM gem5 Developers // AArch64 TLB Invalidate All, EL1, Inner Shareable 140510037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 140610037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 140710037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 140810037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 140910037SARM gem5 Developers { 141010037SARM gem5 Developers assert64(tc); 141110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 141210037SARM gem5 Developers 141310037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 141410037SARM gem5 Developers tlbiOp.broadcast(tc); 141510037SARM gem5 Developers return; 141610037SARM gem5 Developers } 141710037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs 141810037SARM gem5 Developers // only store entries 141910037SARM gem5 Developers // from the last level of translation table walks 142010037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 142110037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3 142210037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 142310037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 142410037SARM gem5 Developers { 142510037SARM gem5 Developers assert64(tc); 142610037SARM gem5 Developers 142710037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 142810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 142910037SARM gem5 Developers 0xbeef); 143010037SARM gem5 Developers tlbiOp(tc); 143110037SARM gem5 Developers return; 143210037SARM gem5 Developers } 143310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 143410037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 143510037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 143610037SARM gem5 Developers { 143710037SARM gem5 Developers assert64(tc); 143811581SDylan.Johnson@ARM.com 143910037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 144010037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 144110037SARM gem5 Developers 0xbeef); 144210037SARM gem5 Developers 144310037SARM gem5 Developers tlbiOp.broadcast(tc); 144410037SARM gem5 Developers return; 144510037SARM gem5 Developers } 144610037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2 144710037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 144810037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 144910037SARM gem5 Developers { 145010037SARM gem5 Developers assert64(tc); 145110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 145210037SARM gem5 Developers 145310037SARM gem5 Developers TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 145410037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 145510037SARM gem5 Developers 0xbeef); 145610037SARM gem5 Developers tlbiOp(tc); 145710037SARM gem5 Developers return; 145810037SARM gem5 Developers } 145910037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 146010037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 146110037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 146210037SARM gem5 Developers { 146310037SARM gem5 Developers assert64(tc); 146410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 146510037SARM gem5 Developers 146610037SARM gem5 Developers TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 146710037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 146810037SARM gem5 Developers 0xbeef); 146910417Sandreas.hansson@arm.com 147010037SARM gem5 Developers tlbiOp.broadcast(tc); 147110037SARM gem5 Developers return; 147210037SARM gem5 Developers } 147310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1 147410037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 147510037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 147610037SARM gem5 Developers { 147712568Sgiacomo.travaglini@arm.com assert64(tc); 147812568Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147912568Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 148012568Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 148112568Sgiacomo.travaglini@arm.com 148212568Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 148312568Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 148412568Sgiacomo.travaglini@arm.com asid); 148512568Sgiacomo.travaglini@arm.com 148612568Sgiacomo.travaglini@arm.com tlbiOp(tc); 148712568Sgiacomo.travaglini@arm.com return; 148812568Sgiacomo.travaglini@arm.com } 148912568Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 149012568Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1IS_Xt: 149110037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 149210037SARM gem5 Developers { 149310037SARM gem5 Developers assert64(tc); 149410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 149510037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 149610037SARM gem5 Developers bits(newVal, 55, 48); 149710037SARM gem5 Developers 149810417Sandreas.hansson@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 149910037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 150011150Smitch.hayenga@arm.com asid); 150110037SARM gem5 Developers 150210037SARM gem5 Developers tlbiOp.broadcast(tc); 150310037SARM gem5 Developers return; 150410037SARM gem5 Developers } 150510037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1 150610037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 150710037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 150810037SARM gem5 Developers { 150910037SARM gem5 Developers assert64(tc); 151010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 151110037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 151210037SARM gem5 Developers bits(newVal, 55, 48); 151310037SARM gem5 Developers 151410037SARM gem5 Developers TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 151510037SARM gem5 Developers tlbiOp(tc); 151610037SARM gem5 Developers return; 151710037SARM gem5 Developers } 151810037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 151910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 152010037SARM gem5 Developers { 152110037SARM gem5 Developers assert64(tc); 152211581SDylan.Johnson@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 152311581SDylan.Johnson@ARM.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 152410037SARM gem5 Developers bits(newVal, 55, 48); 15257362Sgblack@eecs.umich.edu 15267362Sgblack@eecs.umich.edu TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 152712299Sandreas.sandberg@arm.com tlbiOp.broadcast(tc); 152812299Sandreas.sandberg@arm.com return; 152912299Sandreas.sandberg@arm.com } 153012299Sandreas.sandberg@arm.com // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 153112299Sandreas.sandberg@arm.com // entries from the last level of translation table walks 153212299Sandreas.sandberg@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 153312299Sandreas.sandberg@arm.com case MISCREG_TLBI_VAAE1_Xt: 153412299Sandreas.sandberg@arm.com case MISCREG_TLBI_VAALE1_Xt: 153512299Sandreas.sandberg@arm.com { 153612299Sandreas.sandberg@arm.com assert64(tc); 153712299Sandreas.sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 153812299Sandreas.sandberg@arm.com 153912299Sandreas.sandberg@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 154012299Sandreas.sandberg@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 154112299Sandreas.sandberg@arm.com 154212299Sandreas.sandberg@arm.com tlbiOp(tc); 154312299Sandreas.sandberg@arm.com return; 154412299Sandreas.sandberg@arm.com } 154512299Sandreas.sandberg@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 154612732Sandreas.sandberg@arm.com case MISCREG_TLBI_VAAE1IS_Xt: 154712732Sandreas.sandberg@arm.com case MISCREG_TLBI_VAALE1IS_Xt: 154812732Sandreas.sandberg@arm.com { 154912732Sandreas.sandberg@arm.com assert64(tc); 155012732Sandreas.sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 155112732Sandreas.sandberg@arm.com 15527652Sminkyu.jeong@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 155310417Sandreas.hansson@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 15548518Sgeoffrey.blake@arm.com 15558806Sgblack@eecs.umich.edu tlbiOp.broadcast(tc); 15568806Sgblack@eecs.umich.edu return; 15578806Sgblack@eecs.umich.edu } 15588806Sgblack@eecs.umich.edu // AArch64 TLB Invalidate by Intermediate Physical Address, 15598806Sgblack@eecs.umich.edu // Stage 2, EL1 15608806Sgblack@eecs.umich.edu case MISCREG_TLBI_IPAS2E1_Xt: 15618806Sgblack@eecs.umich.edu case MISCREG_TLBI_IPAS2LE1_Xt: 156211150Smitch.hayenga@arm.com { 15638518Sgeoffrey.blake@arm.com assert64(tc); 15648518Sgeoffrey.blake@arm.com scr = readMiscReg(MISCREG_SCR, tc); 156510037SARM gem5 Developers 156610037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 156710037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 156810037SARM gem5 Developers 156910037SARM gem5 Developers tlbiOp(tc); 157010037SARM gem5 Developers return; 157110037SARM gem5 Developers } 157210037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 157310037SARM gem5 Developers // Stage 2, EL1, Inner Shareable 157410037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 157510037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 157610037SARM gem5 Developers { 157710037SARM gem5 Developers assert64(tc); 157810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 157910037SARM gem5 Developers 158010037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 158110037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 158210037SARM gem5 Developers 158310037SARM gem5 Developers tlbiOp.broadcast(tc); 158412299Sandreas.sandberg@arm.com return; 158510037SARM gem5 Developers } 158610037SARM gem5 Developers case MISCREG_ACTLR: 158710037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 158810037SARM gem5 Developers break; 158910037SARM gem5 Developers 159010037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 159110037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 159210037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 159310037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 15946019Shines@cs.fsu.edu pmu->setMiscReg(misc_reg, newVal); 15956019Shines@cs.fsu.edu break; 1596 1597 1598 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1599 { 1600 HSTR hstrMask = 0; 1601 hstrMask.tjdbx = 1; 1602 newVal &= ~((uint32_t) hstrMask); 1603 break; 1604 } 1605 case MISCREG_HCPTR: 1606 { 1607 // If a CP bit in NSACR is 0 then the corresponding bit in 1608 // HCPTR is RAO/WI. Same applies to NSASEDIS 1609 secure_lookup = haveSecurity && 1610 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1611 readMiscRegNoEffect(MISCREG_CPSR)); 1612 if (!secure_lookup) { 1613 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1614 RegVal mask = 1615 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1616 newVal = (newVal & ~mask) | (oldValue & mask); 1617 } 1618 break; 1619 } 1620 case MISCREG_HDFAR: // alias for secure DFAR 1621 misc_reg = MISCREG_DFAR_S; 1622 break; 1623 case MISCREG_HIFAR: // alias for secure IFAR 1624 misc_reg = MISCREG_IFAR_S; 1625 break; 1626 case MISCREG_ATS1CPR: 1627 case MISCREG_ATS1CPW: 1628 case MISCREG_ATS1CUR: 1629 case MISCREG_ATS1CUW: 1630 case MISCREG_ATS12NSOPR: 1631 case MISCREG_ATS12NSOPW: 1632 case MISCREG_ATS12NSOUR: 1633 case MISCREG_ATS12NSOUW: 1634 case MISCREG_ATS1HR: 1635 case MISCREG_ATS1HW: 1636 { 1637 Request::Flags flags = 0; 1638 BaseTLB::Mode mode = BaseTLB::Read; 1639 TLB::ArmTranslationType tranType = TLB::NormalTran; 1640 Fault fault; 1641 switch(misc_reg) { 1642 case MISCREG_ATS1CPR: 1643 flags = TLB::MustBeOne; 1644 tranType = TLB::S1CTran; 1645 mode = BaseTLB::Read; 1646 break; 1647 case MISCREG_ATS1CPW: 1648 flags = TLB::MustBeOne; 1649 tranType = TLB::S1CTran; 1650 mode = BaseTLB::Write; 1651 break; 1652 case MISCREG_ATS1CUR: 1653 flags = TLB::MustBeOne | TLB::UserMode; 1654 tranType = TLB::S1CTran; 1655 mode = BaseTLB::Read; 1656 break; 1657 case MISCREG_ATS1CUW: 1658 flags = TLB::MustBeOne | TLB::UserMode; 1659 tranType = TLB::S1CTran; 1660 mode = BaseTLB::Write; 1661 break; 1662 case MISCREG_ATS12NSOPR: 1663 if (!haveSecurity) 1664 panic("Security Extensions required for ATS12NSOPR"); 1665 flags = TLB::MustBeOne; 1666 tranType = TLB::S1S2NsTran; 1667 mode = BaseTLB::Read; 1668 break; 1669 case MISCREG_ATS12NSOPW: 1670 if (!haveSecurity) 1671 panic("Security Extensions required for ATS12NSOPW"); 1672 flags = TLB::MustBeOne; 1673 tranType = TLB::S1S2NsTran; 1674 mode = BaseTLB::Write; 1675 break; 1676 case MISCREG_ATS12NSOUR: 1677 if (!haveSecurity) 1678 panic("Security Extensions required for ATS12NSOUR"); 1679 flags = TLB::MustBeOne | TLB::UserMode; 1680 tranType = TLB::S1S2NsTran; 1681 mode = BaseTLB::Read; 1682 break; 1683 case MISCREG_ATS12NSOUW: 1684 if (!haveSecurity) 1685 panic("Security Extensions required for ATS12NSOUW"); 1686 flags = TLB::MustBeOne | TLB::UserMode; 1687 tranType = TLB::S1S2NsTran; 1688 mode = BaseTLB::Write; 1689 break; 1690 case MISCREG_ATS1HR: // only really useful from secure mode. 1691 flags = TLB::MustBeOne; 1692 tranType = TLB::HypMode; 1693 mode = BaseTLB::Read; 1694 break; 1695 case MISCREG_ATS1HW: 1696 flags = TLB::MustBeOne; 1697 tranType = TLB::HypMode; 1698 mode = BaseTLB::Write; 1699 break; 1700 } 1701 // If we're in timing mode then doing the translation in 1702 // functional mode then we're slightly distorting performance 1703 // results obtained from simulations. The translation should be 1704 // done in the same mode the core is running in. NOTE: This 1705 // can't be an atomic translation because that causes problems 1706 // with unexpected atomic snoop requests. 1707 warn("Translating via %s in functional mode! Fix Me!\n", 1708 miscRegName[misc_reg]); 1709 1710 auto req = std::make_shared<Request>( 1711 0, val, 0, flags, Request::funcMasterId, 1712 tc->pcState().pc(), tc->contextId()); 1713 1714 fault = getDTBPtr(tc)->translateFunctional( 1715 req, tc, mode, tranType); 1716 1717 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1718 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1719 1720 RegVal newVal; 1721 if (fault == NoFault) { 1722 Addr paddr = req->getPaddr(); 1723 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1724 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1725 newVal = (paddr & mask(39, 12)) | 1726 (getDTBPtr(tc)->getAttr()); 1727 } else { 1728 newVal = (paddr & 0xfffff000) | 1729 (getDTBPtr(tc)->getAttr()); 1730 } 1731 DPRINTF(MiscRegs, 1732 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1733 val, newVal); 1734 } else { 1735 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1736 armFault->update(tc); 1737 // Set fault bit and FSR 1738 FSR fsr = armFault->getFsr(tc); 1739 1740 newVal = ((fsr >> 9) & 1) << 11; 1741 if (newVal) { 1742 // LPAE - rearange fault status 1743 newVal |= ((fsr >> 0) & 0x3f) << 1; 1744 } else { 1745 // VMSA - rearange fault status 1746 newVal |= ((fsr >> 0) & 0xf) << 1; 1747 newVal |= ((fsr >> 10) & 0x1) << 5; 1748 newVal |= ((fsr >> 12) & 0x1) << 6; 1749 } 1750 newVal |= 0x1; // F bit 1751 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1752 newVal |= armFault->isStage2() ? 0x200 : 0; 1753 DPRINTF(MiscRegs, 1754 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1755 val, fsr, newVal); 1756 } 1757 setMiscRegNoEffect(MISCREG_PAR, newVal); 1758 return; 1759 } 1760 case MISCREG_TTBCR: 1761 { 1762 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1763 const uint32_t ones = (uint32_t)(-1); 1764 TTBCR ttbcrMask = 0; 1765 TTBCR ttbcrNew = newVal; 1766 1767 // ARM DDI 0406C.b, ARMv7-32 1768 ttbcrMask.n = ones; // T0SZ 1769 if (haveSecurity) { 1770 ttbcrMask.pd0 = ones; 1771 ttbcrMask.pd1 = ones; 1772 } 1773 ttbcrMask.epd0 = ones; 1774 ttbcrMask.irgn0 = ones; 1775 ttbcrMask.orgn0 = ones; 1776 ttbcrMask.sh0 = ones; 1777 ttbcrMask.ps = ones; // T1SZ 1778 ttbcrMask.a1 = ones; 1779 ttbcrMask.epd1 = ones; 1780 ttbcrMask.irgn1 = ones; 1781 ttbcrMask.orgn1 = ones; 1782 ttbcrMask.sh1 = ones; 1783 if (haveLPAE) 1784 ttbcrMask.eae = ones; 1785 1786 if (haveLPAE && ttbcrNew.eae) { 1787 newVal = newVal & ttbcrMask; 1788 } else { 1789 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1790 } 1791 // Invalidate TLB MiscReg 1792 getITBPtr(tc)->invalidateMiscReg(); 1793 getDTBPtr(tc)->invalidateMiscReg(); 1794 break; 1795 } 1796 case MISCREG_TTBR0: 1797 case MISCREG_TTBR1: 1798 { 1799 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1800 if (haveLPAE) { 1801 if (ttbcr.eae) { 1802 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1803 // ARMv8 AArch32 bit 63-56 only 1804 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1805 newVal = (newVal & (~ttbrMask)); 1806 } 1807 } 1808 // Invalidate TLB MiscReg 1809 getITBPtr(tc)->invalidateMiscReg(); 1810 getDTBPtr(tc)->invalidateMiscReg(); 1811 break; 1812 } 1813 case MISCREG_SCTLR_EL1: 1814 case MISCREG_CONTEXTIDR: 1815 case MISCREG_PRRR: 1816 case MISCREG_NMRR: 1817 case MISCREG_MAIR0: 1818 case MISCREG_MAIR1: 1819 case MISCREG_DACR: 1820 case MISCREG_VTTBR: 1821 case MISCREG_SCR_EL3: 1822 case MISCREG_HCR_EL2: 1823 case MISCREG_TCR_EL1: 1824 case MISCREG_TCR_EL2: 1825 case MISCREG_TCR_EL3: 1826 case MISCREG_SCTLR_EL2: 1827 case MISCREG_SCTLR_EL3: 1828 case MISCREG_HSCTLR: 1829 case MISCREG_TTBR0_EL1: 1830 case MISCREG_TTBR1_EL1: 1831 case MISCREG_TTBR0_EL2: 1832 case MISCREG_TTBR1_EL2: 1833 case MISCREG_TTBR0_EL3: 1834 getITBPtr(tc)->invalidateMiscReg(); 1835 getDTBPtr(tc)->invalidateMiscReg(); 1836 break; 1837 case MISCREG_NZCV: 1838 { 1839 CPSR cpsr = val; 1840 1841 tc->setCCReg(CCREG_NZ, cpsr.nz); 1842 tc->setCCReg(CCREG_C, cpsr.c); 1843 tc->setCCReg(CCREG_V, cpsr.v); 1844 } 1845 break; 1846 case MISCREG_DAIF: 1847 { 1848 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1849 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1850 newVal = cpsr; 1851 misc_reg = MISCREG_CPSR; 1852 } 1853 break; 1854 case MISCREG_SP_EL0: 1855 tc->setIntReg(INTREG_SP0, newVal); 1856 break; 1857 case MISCREG_SP_EL1: 1858 tc->setIntReg(INTREG_SP1, newVal); 1859 break; 1860 case MISCREG_SP_EL2: 1861 tc->setIntReg(INTREG_SP2, newVal); 1862 break; 1863 case MISCREG_SPSEL: 1864 { 1865 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1866 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1867 newVal = cpsr; 1868 misc_reg = MISCREG_CPSR; 1869 } 1870 break; 1871 case MISCREG_CURRENTEL: 1872 { 1873 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1874 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1875 newVal = cpsr; 1876 misc_reg = MISCREG_CPSR; 1877 } 1878 break; 1879 case MISCREG_AT_S1E1R_Xt: 1880 case MISCREG_AT_S1E1W_Xt: 1881 case MISCREG_AT_S1E0R_Xt: 1882 case MISCREG_AT_S1E0W_Xt: 1883 case MISCREG_AT_S1E2R_Xt: 1884 case MISCREG_AT_S1E2W_Xt: 1885 case MISCREG_AT_S12E1R_Xt: 1886 case MISCREG_AT_S12E1W_Xt: 1887 case MISCREG_AT_S12E0R_Xt: 1888 case MISCREG_AT_S12E0W_Xt: 1889 case MISCREG_AT_S1E3R_Xt: 1890 case MISCREG_AT_S1E3W_Xt: 1891 { 1892 RequestPtr req = std::make_shared<Request>(); 1893 Request::Flags flags = 0; 1894 BaseTLB::Mode mode = BaseTLB::Read; 1895 TLB::ArmTranslationType tranType = TLB::NormalTran; 1896 Fault fault; 1897 switch(misc_reg) { 1898 case MISCREG_AT_S1E1R_Xt: 1899 flags = TLB::MustBeOne; 1900 tranType = TLB::S1E1Tran; 1901 mode = BaseTLB::Read; 1902 break; 1903 case MISCREG_AT_S1E1W_Xt: 1904 flags = TLB::MustBeOne; 1905 tranType = TLB::S1E1Tran; 1906 mode = BaseTLB::Write; 1907 break; 1908 case MISCREG_AT_S1E0R_Xt: 1909 flags = TLB::MustBeOne | TLB::UserMode; 1910 tranType = TLB::S1E0Tran; 1911 mode = BaseTLB::Read; 1912 break; 1913 case MISCREG_AT_S1E0W_Xt: 1914 flags = TLB::MustBeOne | TLB::UserMode; 1915 tranType = TLB::S1E0Tran; 1916 mode = BaseTLB::Write; 1917 break; 1918 case MISCREG_AT_S1E2R_Xt: 1919 flags = TLB::MustBeOne; 1920 tranType = TLB::S1E2Tran; 1921 mode = BaseTLB::Read; 1922 break; 1923 case MISCREG_AT_S1E2W_Xt: 1924 flags = TLB::MustBeOne; 1925 tranType = TLB::S1E2Tran; 1926 mode = BaseTLB::Write; 1927 break; 1928 case MISCREG_AT_S12E0R_Xt: 1929 flags = TLB::MustBeOne | TLB::UserMode; 1930 tranType = TLB::S12E0Tran; 1931 mode = BaseTLB::Read; 1932 break; 1933 case MISCREG_AT_S12E0W_Xt: 1934 flags = TLB::MustBeOne | TLB::UserMode; 1935 tranType = TLB::S12E0Tran; 1936 mode = BaseTLB::Write; 1937 break; 1938 case MISCREG_AT_S12E1R_Xt: 1939 flags = TLB::MustBeOne; 1940 tranType = TLB::S12E1Tran; 1941 mode = BaseTLB::Read; 1942 break; 1943 case MISCREG_AT_S12E1W_Xt: 1944 flags = TLB::MustBeOne; 1945 tranType = TLB::S12E1Tran; 1946 mode = BaseTLB::Write; 1947 break; 1948 case MISCREG_AT_S1E3R_Xt: 1949 flags = TLB::MustBeOne; 1950 tranType = TLB::S1E3Tran; 1951 mode = BaseTLB::Read; 1952 break; 1953 case MISCREG_AT_S1E3W_Xt: 1954 flags = TLB::MustBeOne; 1955 tranType = TLB::S1E3Tran; 1956 mode = BaseTLB::Write; 1957 break; 1958 } 1959 // If we're in timing mode then doing the translation in 1960 // functional mode then we're slightly distorting performance 1961 // results obtained from simulations. The translation should be 1962 // done in the same mode the core is running in. NOTE: This 1963 // can't be an atomic translation because that causes problems 1964 // with unexpected atomic snoop requests. 1965 warn("Translating via %s in functional mode! Fix Me!\n", 1966 miscRegName[misc_reg]); 1967 1968 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1969 tc->pcState().pc()); 1970 req->setContext(tc->contextId()); 1971 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1972 tranType); 1973 1974 RegVal newVal; 1975 if (fault == NoFault) { 1976 Addr paddr = req->getPaddr(); 1977 uint64_t attr = getDTBPtr(tc)->getAttr(); 1978 uint64_t attr1 = attr >> 56; 1979 if (!attr1 || attr1 ==0x44) { 1980 attr |= 0x100; 1981 attr &= ~ uint64_t(0x80); 1982 } 1983 newVal = (paddr & mask(47, 12)) | attr; 1984 DPRINTF(MiscRegs, 1985 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1986 val, newVal); 1987 } else { 1988 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1989 armFault->update(tc); 1990 // Set fault bit and FSR 1991 FSR fsr = armFault->getFsr(tc); 1992 1993 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1994 if (cpsr.width) { // AArch32 1995 newVal = ((fsr >> 9) & 1) << 11; 1996 // rearrange fault status 1997 newVal |= ((fsr >> 0) & 0x3f) << 1; 1998 newVal |= 0x1; // F bit 1999 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2000 newVal |= armFault->isStage2() ? 0x200 : 0; 2001 } else { // AArch64 2002 newVal = 1; // F bit 2003 newVal |= fsr << 1; // FST 2004 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2005 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2006 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2007 newVal |= 1 << 11; // RES1 2008 } 2009 DPRINTF(MiscRegs, 2010 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2011 val, fsr, newVal); 2012 } 2013 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2014 return; 2015 } 2016 case MISCREG_SPSR_EL3: 2017 case MISCREG_SPSR_EL2: 2018 case MISCREG_SPSR_EL1: 2019 // Force bits 23:21 to 0 2020 newVal = val & ~(0x7 << 21); 2021 break; 2022 case MISCREG_L2CTLR: 2023 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2024 miscRegName[misc_reg], uint32_t(val)); 2025 break; 2026 2027 // Generic Timer registers 2028 case MISCREG_CNTHV_CTL_EL2: 2029 case MISCREG_CNTHV_CVAL_EL2: 2030 case MISCREG_CNTHV_TVAL_EL2: 2031 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2032 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2033 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2034 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2035 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2036 break; 2037 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2038 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2039 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2040 return; 2041 case MISCREG_ZCR_EL3: 2042 case MISCREG_ZCR_EL2: 2043 case MISCREG_ZCR_EL1: 2044 tc->getDecoderPtr()->setSveLen( 2045 (getCurSveVecLenInBits(tc) >> 7) - 1); 2046 break; 2047 } 2048 } 2049 setMiscRegNoEffect(misc_reg, newVal); 2050} 2051 2052BaseISADevice & 2053ISA::getGenericTimer(ThreadContext *tc) 2054{ 2055 // We only need to create an ISA interface the first time we try 2056 // to access the timer. 2057 if (timer) 2058 return *timer.get(); 2059 2060 assert(system); 2061 GenericTimer *generic_timer(system->getGenericTimer()); 2062 if (!generic_timer) { 2063 panic("Trying to get a generic timer from a system that hasn't " 2064 "been configured to use a generic timer.\n"); 2065 } 2066 2067 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2068 timer->setThreadContext(tc); 2069 2070 return *timer.get(); 2071} 2072 2073BaseISADevice & 2074ISA::getGICv3CPUInterface(ThreadContext *tc) 2075{ 2076 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2077 return *gicv3CpuInterface.get(); 2078} 2079 2080unsigned 2081ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2082{ 2083 if (!FullSystem) { 2084 return sveVL * 128; 2085 } 2086 2087 panic_if(!tc, 2088 "A ThreadContext is needed to determine the SVE vector length " 2089 "in full-system mode"); 2090 2091 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2092 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2093 2094 unsigned len = 0; 2095 2096 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2097 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2098 } 2099 2100 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2101 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2102 } else if (haveVirtualization && !inSecureState(tc) && 2103 (el == EL0 || el == EL1)) { 2104 len = std::min( 2105 len, 2106 static_cast<unsigned>( 2107 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2108 } 2109 2110 if (el == EL3) { 2111 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2112 } else if (haveSecurity) { 2113 len = std::min( 2114 len, 2115 static_cast<unsigned>( 2116 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2117 } 2118 2119 len = std::min(len, sveVL - 1); 2120 2121 return (len + 1) * 128; 2122} 2123 2124void 2125ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2126{ 2127 auto vv = vc.as<uint64_t>(); 2128 for (int i = 2; i < eCount; ++i) { 2129 vv[i] = 0; 2130 } 2131} 2132 2133} // namespace ArmISA 2134 2135ArmISA::ISA * 2136ArmISAParams::create() 2137{ 2138 return new ArmISA::ISA(this); 2139} 2140