isa.cc revision 12478
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2016 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4511793Sbrandon.potter@amd.com#include "cpu/base.hh" 468887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 478232Snate@binkert.org#include "debug/Arm.hh" 488232Snate@binkert.org#include "debug/MiscRegs.hh" 4910844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 509384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 517678Sgblack@eecs.umich.edu#include "sim/faults.hh" 528059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 538284SAli.Saidi@ARM.com#include "sim/system.hh" 547405SAli.Saidi@ARM.com 557405SAli.Saidi@ARM.comnamespace ArmISA 567405SAli.Saidi@ARM.com{ 577405SAli.Saidi@ARM.com 5810037SARM gem5 Developers 5910037SARM gem5 Developers/** 6011768SCurtis.Dunham@arm.com * Some registers alias with others, and therefore need to be translated. 6112477SCurtis.Dunham@arm.com * When two mapping registers are given, they are the 32b lower and 6212477SCurtis.Dunham@arm.com * upper halves, respectively, of the 64b register being mapped. 6311768SCurtis.Dunham@arm.com * aligned with reference documentation ARM DDI 0487A.i pp 1540-1543 6410037SARM gem5 Developers */ 6512477SCurtis.Dunham@arm.comvoid 6612477SCurtis.Dunham@arm.comISA::initializeMiscRegMetadata() 6712477SCurtis.Dunham@arm.com{ 6812477SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_EL1).mapsTo(MISCREG_ACTLR_NS); 6912477SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR0_EL1).mapsTo(MISCREG_ADFSR_NS); 7012477SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR1_EL1).mapsTo(MISCREG_AIFSR_NS); 7112477SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR_EL1).mapsTo(MISCREG_AMAIR0_NS, 7212477SCurtis.Dunham@arm.com MISCREG_AMAIR1_NS); 7312477SCurtis.Dunham@arm.com InitReg(MISCREG_CONTEXTIDR_EL1).mapsTo(MISCREG_CONTEXTIDR_NS); 7412477SCurtis.Dunham@arm.com InitReg(MISCREG_CPACR_EL1).mapsTo(MISCREG_CPACR); 7512477SCurtis.Dunham@arm.com InitReg(MISCREG_CSSELR_EL1).mapsTo(MISCREG_CSSELR_NS); 7612477SCurtis.Dunham@arm.com InitReg(MISCREG_DACR32_EL2).mapsTo(MISCREG_DACR_NS); 7712477SCurtis.Dunham@arm.com InitReg(MISCREG_FAR_EL1).mapsTo(MISCREG_DFAR_NS, 7812477SCurtis.Dunham@arm.com MISCREG_IFAR_NS); 7911768SCurtis.Dunham@arm.com // ESR_EL1 -> DFSR 8012477SCurtis.Dunham@arm.com InitReg(MISCREG_HACR_EL2).mapsTo(MISCREG_HACR); 8112477SCurtis.Dunham@arm.com InitReg(MISCREG_ACTLR_EL2).mapsTo(MISCREG_HACTLR); 8212477SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR0_EL2).mapsTo(MISCREG_HADFSR); 8312477SCurtis.Dunham@arm.com InitReg(MISCREG_AFSR1_EL2).mapsTo(MISCREG_HAIFSR); 8412477SCurtis.Dunham@arm.com InitReg(MISCREG_AMAIR_EL2).mapsTo(MISCREG_HAMAIR0, 8512477SCurtis.Dunham@arm.com MISCREG_HAMAIR1); 8612477SCurtis.Dunham@arm.com InitReg(MISCREG_CPTR_EL2).mapsTo(MISCREG_HCPTR); 8712477SCurtis.Dunham@arm.com InitReg(MISCREG_HCR_EL2).mapsTo(MISCREG_HCR /*, 8812477SCurtis.Dunham@arm.com MISCREG_HCR2*/); 8912477SCurtis.Dunham@arm.com InitReg(MISCREG_MDCR_EL2).mapsTo(MISCREG_HDCR); 9012477SCurtis.Dunham@arm.com InitReg(MISCREG_FAR_EL2).mapsTo(MISCREG_HDFAR, 9112477SCurtis.Dunham@arm.com MISCREG_HIFAR); 9212477SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR_EL2).mapsTo(MISCREG_HMAIR0, 9312477SCurtis.Dunham@arm.com MISCREG_HMAIR1); 9412477SCurtis.Dunham@arm.com InitReg(MISCREG_HPFAR_EL2).mapsTo(MISCREG_HPFAR); 9512477SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_EL2).mapsTo(MISCREG_HSCTLR); 9612477SCurtis.Dunham@arm.com InitReg(MISCREG_ESR_EL2).mapsTo(MISCREG_HSR); 9712477SCurtis.Dunham@arm.com InitReg(MISCREG_HSTR_EL2).mapsTo(MISCREG_HSTR); 9812477SCurtis.Dunham@arm.com InitReg(MISCREG_TCR_EL2).mapsTo(MISCREG_HTCR); 9912477SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL2).mapsTo(MISCREG_HTPIDR); 10012477SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_EL2).mapsTo(MISCREG_HTTBR); 10112477SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_EL2).mapsTo(MISCREG_HVBAR); 10212477SCurtis.Dunham@arm.com InitReg(MISCREG_IFSR32_EL2).mapsTo(MISCREG_IFSR_NS); 10312477SCurtis.Dunham@arm.com InitReg(MISCREG_MAIR_EL1).mapsTo(MISCREG_PRRR_NS, 10412477SCurtis.Dunham@arm.com MISCREG_NMRR_NS); 10512477SCurtis.Dunham@arm.com InitReg(MISCREG_PAR_EL1).mapsTo(MISCREG_PAR_NS); 10611768SCurtis.Dunham@arm.com // RMR_EL1 -> RMR 10711768SCurtis.Dunham@arm.com // RMR_EL2 -> HRMR 10812477SCurtis.Dunham@arm.com InitReg(MISCREG_SCTLR_EL1).mapsTo(MISCREG_SCTLR_NS); 10912477SCurtis.Dunham@arm.com InitReg(MISCREG_SDER32_EL3).mapsTo(MISCREG_SDER); 11012477SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL1).mapsTo(MISCREG_TPIDRPRW_NS); 11112477SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDRRO_EL0).mapsTo(MISCREG_TPIDRURO_NS); 11212477SCurtis.Dunham@arm.com InitReg(MISCREG_TPIDR_EL0).mapsTo(MISCREG_TPIDRURW_NS); 11312477SCurtis.Dunham@arm.com InitReg(MISCREG_TCR_EL1).mapsTo(MISCREG_TTBCR_NS); 11412477SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR0_EL1).mapsTo(MISCREG_TTBR0_NS); 11512477SCurtis.Dunham@arm.com InitReg(MISCREG_TTBR1_EL1).mapsTo(MISCREG_TTBR1_NS); 11612477SCurtis.Dunham@arm.com InitReg(MISCREG_VBAR_EL1).mapsTo(MISCREG_VBAR_NS); 11712477SCurtis.Dunham@arm.com InitReg(MISCREG_VMPIDR_EL2).mapsTo(MISCREG_VMPIDR); 11812477SCurtis.Dunham@arm.com InitReg(MISCREG_VPIDR_EL2).mapsTo(MISCREG_VPIDR); 11912477SCurtis.Dunham@arm.com InitReg(MISCREG_VTCR_EL2).mapsTo(MISCREG_VTCR); 12012477SCurtis.Dunham@arm.com InitReg(MISCREG_VTTBR_EL2).mapsTo(MISCREG_VTTBR); 12112477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTFRQ_EL0).mapsTo(MISCREG_CNTFRQ); 12212477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHCTL_EL2).mapsTo(MISCREG_CNTHCTL); 12312477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CTL_EL2).mapsTo(MISCREG_CNTHP_CTL); 12412477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_CVAL_EL2).mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ 12512477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTHP_TVAL_EL2).mapsTo(MISCREG_CNTHP_TVAL); 12612477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTKCTL_EL1).mapsTo(MISCREG_CNTKCTL); 12712477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CTL_EL0).mapsTo(MISCREG_CNTP_CTL_NS); 12812477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_CVAL_EL0).mapsTo(MISCREG_CNTP_CVAL_NS); /* 64b */ 12912477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTP_TVAL_EL0).mapsTo(MISCREG_CNTP_TVAL_NS); 13012477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTPCT_EL0).mapsTo(MISCREG_CNTPCT); /* 64b */ 13112477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CTL_EL0).mapsTo(MISCREG_CNTV_CTL); 13212477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_CVAL_EL0).mapsTo(MISCREG_CNTV_CVAL); /* 64b */ 13312477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTV_TVAL_EL0).mapsTo(MISCREG_CNTV_TVAL); 13412477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVCT_EL0).mapsTo(MISCREG_CNTVCT); /* 64b */ 13512477SCurtis.Dunham@arm.com InitReg(MISCREG_CNTVOFF_EL2).mapsTo(MISCREG_CNTVOFF); /* 64b */ 13612477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGAUTHSTATUS_EL1).mapsTo(MISCREG_DBGAUTHSTATUS); 13712477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR0_EL1).mapsTo(MISCREG_DBGBCR0); 13812477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR1_EL1).mapsTo(MISCREG_DBGBCR1); 13912477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR2_EL1).mapsTo(MISCREG_DBGBCR2); 14012477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR3_EL1).mapsTo(MISCREG_DBGBCR3); 14112477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR4_EL1).mapsTo(MISCREG_DBGBCR4); 14212477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBCR5_EL1).mapsTo(MISCREG_DBGBCR5); 14312477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR0_EL1).mapsTo(MISCREG_DBGBVR0 /*, 14412477SCurtis.Dunham@arm.com MISCREG_DBGBXVR0 */); 14512477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR1_EL1).mapsTo(MISCREG_DBGBVR1 /*, 14612477SCurtis.Dunham@arm.com MISCREG_DBGBXVR1 */); 14712477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR2_EL1).mapsTo(MISCREG_DBGBVR2 /*, 14812477SCurtis.Dunham@arm.com MISCREG_DBGBXVR2 */); 14912477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR3_EL1).mapsTo(MISCREG_DBGBVR3 /*, 15012477SCurtis.Dunham@arm.com MISCREG_DBGBXVR3 */); 15112477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR4_EL1).mapsTo(MISCREG_DBGBVR4 /*, 15212477SCurtis.Dunham@arm.com MISCREG_DBGBXVR4 */); 15312477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGBVR5_EL1).mapsTo(MISCREG_DBGBVR5 /*, 15412477SCurtis.Dunham@arm.com MISCREG_DBGBXVR5 */); 15512477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMSET_EL1).mapsTo(MISCREG_DBGCLAIMSET); 15612477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGCLAIMCLR_EL1).mapsTo(MISCREG_DBGCLAIMCLR); 15711768SCurtis.Dunham@arm.com // DBGDTR_EL0 -> DBGDTR{R or T}Xint 15811768SCurtis.Dunham@arm.com // DBGDTRRX_EL0 -> DBGDTRRXint 15911768SCurtis.Dunham@arm.com // DBGDTRTX_EL0 -> DBGDTRRXint 16012477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGPRCR_EL1).mapsTo(MISCREG_DBGPRCR); 16112477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGVCR32_EL2).mapsTo(MISCREG_DBGVCR); 16212477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR0_EL1).mapsTo(MISCREG_DBGWCR0); 16312477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR1_EL1).mapsTo(MISCREG_DBGWCR1); 16412477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR2_EL1).mapsTo(MISCREG_DBGWCR2); 16512477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWCR3_EL1).mapsTo(MISCREG_DBGWCR3); 16612477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR0_EL1).mapsTo(MISCREG_DBGWVR0); 16712477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR1_EL1).mapsTo(MISCREG_DBGWVR1); 16812477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR2_EL1).mapsTo(MISCREG_DBGWVR2); 16912477SCurtis.Dunham@arm.com InitReg(MISCREG_DBGWVR3_EL1).mapsTo(MISCREG_DBGWVR3); 17012477SCurtis.Dunham@arm.com InitReg(MISCREG_ID_DFR0_EL1).mapsTo(MISCREG_ID_DFR0); 17112477SCurtis.Dunham@arm.com InitReg(MISCREG_MDCCSR_EL0).mapsTo(MISCREG_DBGDSCRint); 17212477SCurtis.Dunham@arm.com InitReg(MISCREG_MDRAR_EL1).mapsTo(MISCREG_DBGDRAR); 17312477SCurtis.Dunham@arm.com InitReg(MISCREG_MDSCR_EL1).mapsTo(MISCREG_DBGDSCRext); 17412477SCurtis.Dunham@arm.com InitReg(MISCREG_OSDLR_EL1).mapsTo(MISCREG_DBGOSDLR); 17512477SCurtis.Dunham@arm.com InitReg(MISCREG_OSDTRRX_EL1).mapsTo(MISCREG_DBGDTRRXext); 17612477SCurtis.Dunham@arm.com InitReg(MISCREG_OSDTRTX_EL1).mapsTo(MISCREG_DBGDTRTXext); 17712477SCurtis.Dunham@arm.com InitReg(MISCREG_OSECCR_EL1).mapsTo(MISCREG_DBGOSECCR); 17812477SCurtis.Dunham@arm.com InitReg(MISCREG_OSLAR_EL1).mapsTo(MISCREG_DBGOSLAR); 17912477SCurtis.Dunham@arm.com InitReg(MISCREG_OSLSR_EL1).mapsTo(MISCREG_DBGOSLSR); 18012477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCCNTR_EL0).mapsTo(MISCREG_PMCCNTR); 18112477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID0_EL0).mapsTo(MISCREG_PMCEID0); 18212477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCEID1_EL0).mapsTo(MISCREG_PMCEID1); 18312477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENSET_EL0).mapsTo(MISCREG_PMCNTENSET); 18412477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCNTENCLR_EL0).mapsTo(MISCREG_PMCNTENCLR); 18512477SCurtis.Dunham@arm.com InitReg(MISCREG_PMCR_EL0).mapsTo(MISCREG_PMCR); 18612477SCurtis.Dunham@arm.com/* InitReg(MISCREG_PMEVCNTR0_EL0).mapsTo(MISCREG_PMEVCNTR0); 18712477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR1_EL0).mapsTo(MISCREG_PMEVCNTR1); 18812477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR2_EL0).mapsTo(MISCREG_PMEVCNTR2); 18912477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR3_EL0).mapsTo(MISCREG_PMEVCNTR3); 19012477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR4_EL0).mapsTo(MISCREG_PMEVCNTR4); 19112477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVCNTR5_EL0).mapsTo(MISCREG_PMEVCNTR5); 19212477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER0_EL0).mapsTo(MISCREG_PMEVTYPER0); 19312477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER1_EL0).mapsTo(MISCREG_PMEVTYPER1); 19412477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER2_EL0).mapsTo(MISCREG_PMEVTYPER2); 19512477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER3_EL0).mapsTo(MISCREG_PMEVTYPER3); 19612477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER4_EL0).mapsTo(MISCREG_PMEVTYPER4); 19712477SCurtis.Dunham@arm.com InitReg(MISCREG_PMEVTYPER5_EL0).mapsTo(MISCREG_PMEVTYPER5); */ 19812477SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENCLR_EL1).mapsTo(MISCREG_PMINTENCLR); 19912477SCurtis.Dunham@arm.com InitReg(MISCREG_PMINTENSET_EL1).mapsTo(MISCREG_PMINTENSET); 20012477SCurtis.Dunham@arm.com// InitReg(MISCREG_PMOVSCLR_EL0).mapsTo(MISCREG_PMOVSCLR); 20112477SCurtis.Dunham@arm.com InitReg(MISCREG_PMOVSSET_EL0).mapsTo(MISCREG_PMOVSSET); 20212477SCurtis.Dunham@arm.com InitReg(MISCREG_PMSELR_EL0).mapsTo(MISCREG_PMSELR); 20312477SCurtis.Dunham@arm.com InitReg(MISCREG_PMSWINC_EL0).mapsTo(MISCREG_PMSWINC); 20412477SCurtis.Dunham@arm.com InitReg(MISCREG_PMUSERENR_EL0).mapsTo(MISCREG_PMUSERENR); 20512477SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVCNTR_EL0).mapsTo(MISCREG_PMXEVCNTR); 20612477SCurtis.Dunham@arm.com InitReg(MISCREG_PMXEVTYPER_EL0).mapsTo(MISCREG_PMXEVTYPER); 20711768SCurtis.Dunham@arm.com 20812478SCurtis.Dunham@arm.com InitReg(MISCREG_SCR).res0(0xff40) // [31:16], [6] 20912478SCurtis.Dunham@arm.com .res1(0x0030); // [5:4] 21012478SCurtis.Dunham@arm.com 21111768SCurtis.Dunham@arm.com // from ARM DDI 0487A.i, template text 21211768SCurtis.Dunham@arm.com // "AArch64 System register ___ can be mapped to 21311768SCurtis.Dunham@arm.com // AArch32 System register ___, but this is not 21411768SCurtis.Dunham@arm.com // architecturally mandated." 21512477SCurtis.Dunham@arm.com InitReg(MISCREG_SCR_EL3).mapsTo(MISCREG_SCR); // D7-2005 21611768SCurtis.Dunham@arm.com // MDCR_EL3 -> SDCR, D7-2108 (the latter is unimpl. in gem5) 21712477SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL1).mapsTo(MISCREG_SPSR_SVC); // C5.2.17 SPSR_EL1 21812477SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL2).mapsTo(MISCREG_SPSR_HYP); // C5.2.18 SPSR_EL2 21912477SCurtis.Dunham@arm.com InitReg(MISCREG_SPSR_EL3).mapsTo(MISCREG_SPSR_MON); // C5.2.19 SPSR_EL3 22012477SCurtis.Dunham@arm.com} 22110037SARM gem5 Developers 2229384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 22310461SAndreas.Sandberg@ARM.com : SimObject(p), 22410461SAndreas.Sandberg@ARM.com system(NULL), 22511165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 22612109SRekai.GonzalezAlberquilla@arm.com _vecRegRenameMode(p->vecRegRenameMode), 22710461SAndreas.Sandberg@ARM.com pmu(p->pmu), 22812477SCurtis.Dunham@arm.com lookUpMiscReg(NUM_MISCREGS) 2299384SAndreas.Sandberg@arm.com{ 23011770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 23110037SARM gem5 Developers 23210461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 23310461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 23410461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 23510461SAndreas.Sandberg@ARM.com if (!pmu) 23610461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 23710461SAndreas.Sandberg@ARM.com 23810609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 23910609Sandreas.sandberg@arm.com pmu->setISA(this); 24010609Sandreas.sandberg@arm.com 24110037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 24210037SARM gem5 Developers 24310037SARM gem5 Developers // Cache system-level properties 24410037SARM gem5 Developers if (FullSystem && system) { 24511771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 24610037SARM gem5 Developers haveSecurity = system->haveSecurity(); 24710037SARM gem5 Developers haveLPAE = system->haveLPAE(); 24810037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 24910037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 25010037SARM gem5 Developers physAddrRange64 = system->physAddrRange64(); 25110037SARM gem5 Developers } else { 25211771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 25310037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 25410037SARM gem5 Developers haveLargeAsid64 = false; 25510037SARM gem5 Developers physAddrRange64 = 32; // dummy value 25610037SARM gem5 Developers } 25710037SARM gem5 Developers 25812477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 25910037SARM gem5 Developers preUnflattenMiscReg(); 26010037SARM gem5 Developers 2619384SAndreas.Sandberg@arm.com clear(); 2629384SAndreas.Sandberg@arm.com} 2639384SAndreas.Sandberg@arm.com 2649384SAndreas.Sandberg@arm.comconst ArmISAParams * 2659384SAndreas.Sandberg@arm.comISA::params() const 2669384SAndreas.Sandberg@arm.com{ 2679384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 2689384SAndreas.Sandberg@arm.com} 2699384SAndreas.Sandberg@arm.com 2707427Sgblack@eecs.umich.eduvoid 2717427Sgblack@eecs.umich.eduISA::clear() 2727427Sgblack@eecs.umich.edu{ 2739385SAndreas.Sandberg@arm.com const Params *p(params()); 2749385SAndreas.Sandberg@arm.com 2757427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 2767427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 27710037SARM gem5 Developers 27810037SARM gem5 Developers // Initialize configurable default values 27910037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 28010037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 28110037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 28210037SARM gem5 Developers 28310037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 28410037SARM gem5 Developers // Initialize AArch64 state 28510037SARM gem5 Developers clear64(p); 28610037SARM gem5 Developers return; 28710037SARM gem5 Developers } 28810037SARM gem5 Developers 28910037SARM gem5 Developers // Initialize AArch32 state... 29010037SARM gem5 Developers 2917427Sgblack@eecs.umich.edu CPSR cpsr = 0; 2927427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 2937427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2947427Sgblack@eecs.umich.edu updateRegMap(cpsr); 2957427Sgblack@eecs.umich.edu 2967427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 29710037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 29810037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 29910037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 30010037SARM gem5 Developers sctlr.u = 1; 3017427Sgblack@eecs.umich.edu sctlr.xp = 1; 3027427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 3037427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 30410037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 30510204SAli.Saidi@ARM.com sctlr.uci = 1; 30610204SAli.Saidi@ARM.com sctlr.dze = 1; 30710037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 3087427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 30910037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 3107427Sgblack@eecs.umich.edu 31110037SARM gem5 Developers // Start with an event in the mailbox 3127427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 3137427Sgblack@eecs.umich.edu 31410037SARM gem5 Developers // Separate Instruction and Data TLBs 3157427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 3167427Sgblack@eecs.umich.edu 3177427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 3187427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 3197427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 3207427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 3217427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 3227427Sgblack@eecs.umich.edu mvfr0.divide = 1; 3237427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 3247427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 3257427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 3267427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 3277427Sgblack@eecs.umich.edu 3287427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 3297427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 3307427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 3317427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 3327427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 3337427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 3347427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 3357427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 3367427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 3377427Sgblack@eecs.umich.edu 3387436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 3397436Sdam.sunwoo@arm.com 34010037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 34110037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 3427436Sdam.sunwoo@arm.com (1 << 19) | // 19 3437436Sdam.sunwoo@arm.com (0 << 18) | // 18 3447436Sdam.sunwoo@arm.com (0 << 17) | // 17 3457436Sdam.sunwoo@arm.com (1 << 16) | // 16 3467436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 3477436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 3487436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 3497436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 3507436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 3517436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 3527436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 3537436Sdam.sunwoo@arm.com 0; // 1:0 35410037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 3557436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 3567436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 3577436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 3587436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 3597436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 3607436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 3617436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 3627436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 3637436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 3647436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 3657436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 3667436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 3677436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 3687436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 3697436Sdam.sunwoo@arm.com 0; // 1:0 3707436Sdam.sunwoo@arm.com 3717644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 3728147SAli.Saidi@ARM.com 3739385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 3749385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 3759385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 3769385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 3779385SAndreas.Sandberg@arm.com 3789385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 3799385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 3809385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 3819385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3829385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3839385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 3849385SAndreas.Sandberg@arm.com 3859385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 3869385SAndreas.Sandberg@arm.com 38710037SARM gem5 Developers if (haveLPAE) { 38810037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 38910037SARM gem5 Developers ttbcr.eae = 0; 39010037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 39110037SARM gem5 Developers // Enforce consistency with system-level settings 39210037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 39310037SARM gem5 Developers } 39410037SARM gem5 Developers 39510037SARM gem5 Developers if (haveSecurity) { 39610037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 39710037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 39810037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 39910037SARM gem5 Developers } else { 40010037SARM gem5 Developers // we're always non-secure 40110037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 40210037SARM gem5 Developers } 4038147SAli.Saidi@ARM.com 4047427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 4057427Sgblack@eecs.umich.edu} 4067427Sgblack@eecs.umich.edu 40710037SARM gem5 Developersvoid 40810037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 40910037SARM gem5 Developers{ 41010037SARM gem5 Developers CPSR cpsr = 0; 41110037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 41210037SARM gem5 Developers switch (system->highestEL()) { 41310037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 41410037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 41510037SARM gem5 Developers // value 41610037SARM gem5 Developers case EL3: 41710037SARM gem5 Developers cpsr.mode = MODE_EL3H; 41810037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 41910037SARM gem5 Developers break; 42010037SARM gem5 Developers case EL2: 42110037SARM gem5 Developers cpsr.mode = MODE_EL2H; 42210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 42310037SARM gem5 Developers break; 42410037SARM gem5 Developers case EL1: 42510037SARM gem5 Developers cpsr.mode = MODE_EL1H; 42610037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 42710037SARM gem5 Developers break; 42810037SARM gem5 Developers default: 42910037SARM gem5 Developers panic("Invalid highest implemented exception level"); 43010037SARM gem5 Developers break; 43110037SARM gem5 Developers } 43210037SARM gem5 Developers 43310037SARM gem5 Developers // Initialize rest of CPSR 43410037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 43510037SARM gem5 Developers cpsr.ss = 0; 43610037SARM gem5 Developers cpsr.il = 0; 43710037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 43810037SARM gem5 Developers updateRegMap(cpsr); 43910037SARM gem5 Developers 44010037SARM gem5 Developers // Initialize other control registers 44110037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 44210037SARM gem5 Developers if (haveSecurity) { 44311770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 44410037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 44511574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 44611770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 44711770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 44810037SARM gem5 Developers } else { 44911770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 45011770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 45110037SARM gem5 Developers // Always non-secure 45210037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 45310037SARM gem5 Developers } 45410037SARM gem5 Developers 45510037SARM gem5 Developers // Initialize configurable id registers 45610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 45710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 45810461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 45910461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 46010461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 46110461SAndreas.Sandberg@ARM.com 46210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 46310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 46410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 46510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 46610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 46710037SARM gem5 Developers 46810461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 46910461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 47010461SAndreas.Sandberg@ARM.com 47110461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 47210461SAndreas.Sandberg@ARM.com 47310037SARM gem5 Developers // Enforce consistency with system-level settings... 47410037SARM gem5 Developers 47510037SARM gem5 Developers // EL3 47610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 47710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 47811574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 47910037SARM gem5 Developers // EL2 48010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 48110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 48211574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 48310037SARM gem5 Developers // Large ASID support 48410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 48510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 48610037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 48710037SARM gem5 Developers // Physical address size 48810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 48910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 49010037SARM gem5 Developers encodePhysAddrRange64(physAddrRange64)); 49110037SARM gem5 Developers} 49210037SARM gem5 Developers 4937405SAli.Saidi@ARM.comMiscReg 49410035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 4957405SAli.Saidi@ARM.com{ 4967405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4977614Sminkyu.jeong@arm.com 49812478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 49912478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 50012478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 50112478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 50212478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 50312478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 50412478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 50512478SCurtis.Dunham@arm.com if (val & reg.res0()) { 50612478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 50712478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 50812478SCurtis.Dunham@arm.com } 50912478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 51012478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 51112478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 51212478SCurtis.Dunham@arm.com } 51312478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 5147405SAli.Saidi@ARM.com} 5157405SAli.Saidi@ARM.com 5167405SAli.Saidi@ARM.com 5177405SAli.Saidi@ARM.comMiscReg 5187405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 5197405SAli.Saidi@ARM.com{ 52010037SARM gem5 Developers CPSR cpsr = 0; 52110037SARM gem5 Developers PCState pc = 0; 52210037SARM gem5 Developers SCR scr = 0; 5239050Schander.sudanthi@arm.com 5247405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 52510037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 52610037SARM gem5 Developers pc = tc->pcState(); 5277720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 5287720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 5297405SAli.Saidi@ARM.com return cpsr; 5307405SAli.Saidi@ARM.com } 5317757SAli.Saidi@ARM.com 53210037SARM gem5 Developers#ifndef NDEBUG 53310037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 53410037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 53510037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 53610037SARM gem5 Developers miscRegName[misc_reg]); 53710037SARM gem5 Developers else 53810037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 53910037SARM gem5 Developers miscRegName[misc_reg]); 54010037SARM gem5 Developers } 54110037SARM gem5 Developers#endif 54210037SARM gem5 Developers 54310037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 54410037SARM gem5 Developers case MISCREG_HCR: 54510037SARM gem5 Developers { 54610037SARM gem5 Developers if (!haveVirtualization) 54710037SARM gem5 Developers return 0; 54810037SARM gem5 Developers else 54910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 55010037SARM gem5 Developers } 55110037SARM gem5 Developers case MISCREG_CPACR: 55210037SARM gem5 Developers { 55310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 55410037SARM gem5 Developers CPACR cpacrMask = 0; 55510037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 55610037SARM gem5 Developers // be readable? (straight copy from the write code) 55710037SARM gem5 Developers cpacrMask.cp10 = ones; 55810037SARM gem5 Developers cpacrMask.cp11 = ones; 55910037SARM gem5 Developers cpacrMask.asedis = ones; 56010037SARM gem5 Developers 56110037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 56210037SARM gem5 Developers if (haveSecurity) { 56310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 56410037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 56510037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 56610037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 56710037SARM gem5 Developers // NB: Skipping the full loop, here 56810037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 56910037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 57010037SARM gem5 Developers } 57110037SARM gem5 Developers } 57210037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 57310037SARM gem5 Developers val &= cpacrMask; 57410037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 57510037SARM gem5 Developers miscRegName[misc_reg], val); 57610037SARM gem5 Developers return val; 57710037SARM gem5 Developers } 5788284SAli.Saidi@ARM.com case MISCREG_MPIDR: 57910037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 58010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 58110037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 58210037SARM gem5 Developers return getMPIDR(system, tc); 5839050Schander.sudanthi@arm.com } else { 58410037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 58510037SARM gem5 Developers } 58610037SARM gem5 Developers break; 58710037SARM gem5 Developers case MISCREG_MPIDR_EL1: 58810037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 58910037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 59010037SARM gem5 Developers case MISCREG_VMPIDR: 59110037SARM gem5 Developers // top bit defined as RES1 59210037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 59310037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 59410037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 59510037SARM gem5 Developers case MISCREG_MIDR: 59610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 59710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 59810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 59910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 60010037SARM gem5 Developers } else { 60110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 6029050Schander.sudanthi@arm.com } 6038284SAli.Saidi@ARM.com break; 60410037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 60510037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 60610037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 60710037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 60810037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 60910037SARM gem5 Developers return 0; 61010037SARM gem5 Developers 6117405SAli.Saidi@ARM.com case MISCREG_CLIDR: 6127731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 6138468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 6148468Swade.walker@arm.com "ARM implementations.\n"); 6158468Swade.walker@arm.com return 0x00200000; 6167405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 6177731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 6187405SAli.Saidi@ARM.com "always reads as 0.\n"); 6197405SAli.Saidi@ARM.com break; 62011809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 62111809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 6229130Satgutier@umich.edu { 6239130Satgutier@umich.edu //all caches have the same line size in gem5 6249130Satgutier@umich.edu //4 byte words in ARM 6259130Satgutier@umich.edu unsigned lineSizeWords = 6269814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 6279130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 6289130Satgutier@umich.edu 6299130Satgutier@umich.edu while (lineSizeWords >>= 1) { 6309130Satgutier@umich.edu ++log2LineSizeWords; 6319130Satgutier@umich.edu } 6329130Satgutier@umich.edu 6339130Satgutier@umich.edu CTR ctr = 0; 6349130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 6359130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 6369130Satgutier@umich.edu //b11 - gem5 uses pipt 6379130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 6389130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 6399130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 6409130Satgutier@umich.edu //log2 of max reservation size (words) 6419130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 6429130Satgutier@umich.edu //log2 of max writeback size (words) 6439130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 6449130Satgutier@umich.edu //b100 - gem5 format is ARMv7 6459130Satgutier@umich.edu ctr.format = 0x4; 6469130Satgutier@umich.edu 6479130Satgutier@umich.edu return ctr; 6489130Satgutier@umich.edu } 6497583SAli.Saidi@arm.com case MISCREG_ACTLR: 6507583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 6517583SAli.Saidi@arm.com break; 65210461SAndreas.Sandberg@ARM.com 65310461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 65410461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 65510461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 65610461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 65710461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 65810461SAndreas.Sandberg@ARM.com 6598302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 6608302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 6617783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 6627783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 6637783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 6647783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 66510037SARM gem5 Developers case MISCREG_FPSR: 66610037SARM gem5 Developers { 66710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 66810037SARM gem5 Developers FPSCR fpscrMask = 0; 66910037SARM gem5 Developers fpscrMask.ioc = ones; 67010037SARM gem5 Developers fpscrMask.dzc = ones; 67110037SARM gem5 Developers fpscrMask.ofc = ones; 67210037SARM gem5 Developers fpscrMask.ufc = ones; 67310037SARM gem5 Developers fpscrMask.ixc = ones; 67410037SARM gem5 Developers fpscrMask.idc = ones; 67510037SARM gem5 Developers fpscrMask.qc = ones; 67610037SARM gem5 Developers fpscrMask.v = ones; 67710037SARM gem5 Developers fpscrMask.c = ones; 67810037SARM gem5 Developers fpscrMask.z = ones; 67910037SARM gem5 Developers fpscrMask.n = ones; 68010037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 68110037SARM gem5 Developers } 68210037SARM gem5 Developers case MISCREG_FPCR: 68310037SARM gem5 Developers { 68410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 68510037SARM gem5 Developers FPSCR fpscrMask = 0; 68610037SARM gem5 Developers fpscrMask.ioe = ones; 68710037SARM gem5 Developers fpscrMask.dze = ones; 68810037SARM gem5 Developers fpscrMask.ofe = ones; 68910037SARM gem5 Developers fpscrMask.ufe = ones; 69010037SARM gem5 Developers fpscrMask.ixe = ones; 69110037SARM gem5 Developers fpscrMask.ide = ones; 69210037SARM gem5 Developers fpscrMask.len = ones; 69310037SARM gem5 Developers fpscrMask.stride = ones; 69410037SARM gem5 Developers fpscrMask.rMode = ones; 69510037SARM gem5 Developers fpscrMask.fz = ones; 69610037SARM gem5 Developers fpscrMask.dn = ones; 69710037SARM gem5 Developers fpscrMask.ahp = ones; 69810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 69910037SARM gem5 Developers } 70010037SARM gem5 Developers case MISCREG_NZCV: 70110037SARM gem5 Developers { 70210037SARM gem5 Developers CPSR cpsr = 0; 70310338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 70410338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 70510338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 70610037SARM gem5 Developers return cpsr; 70710037SARM gem5 Developers } 70810037SARM gem5 Developers case MISCREG_DAIF: 70910037SARM gem5 Developers { 71010037SARM gem5 Developers CPSR cpsr = 0; 71110037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 71210037SARM gem5 Developers return cpsr; 71310037SARM gem5 Developers } 71410037SARM gem5 Developers case MISCREG_SP_EL0: 71510037SARM gem5 Developers { 71610037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 71710037SARM gem5 Developers } 71810037SARM gem5 Developers case MISCREG_SP_EL1: 71910037SARM gem5 Developers { 72010037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 72110037SARM gem5 Developers } 72210037SARM gem5 Developers case MISCREG_SP_EL2: 72310037SARM gem5 Developers { 72410037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 72510037SARM gem5 Developers } 72610037SARM gem5 Developers case MISCREG_SPSEL: 72710037SARM gem5 Developers { 72810037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 72910037SARM gem5 Developers } 73010037SARM gem5 Developers case MISCREG_CURRENTEL: 73110037SARM gem5 Developers { 73210037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 73310037SARM gem5 Developers } 7348549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 7358868SMatt.Horsnell@arm.com { 7368868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 7378868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 7388868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 7398868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 7408868SMatt.Horsnell@arm.com return l2ctlr; 7418868SMatt.Horsnell@arm.com } 7428868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 7438868SMatt.Horsnell@arm.com /* For now just implement the version number. 74410461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 7458868SMatt.Horsnell@arm.com */ 74610461SAndreas.Sandberg@ARM.com return 0x5 << 16; 74710037SARM gem5 Developers case MISCREG_DBGDSCRint: 7488868SMatt.Horsnell@arm.com return 0; 74910037SARM gem5 Developers case MISCREG_ISR: 75011150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 75110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 75210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 75310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 75410037SARM gem5 Developers case MISCREG_ISR_EL1: 75511150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 75610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 75710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 75810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 75910037SARM gem5 Developers case MISCREG_DCZID_EL0: 76010037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 76110037SARM gem5 Developers case MISCREG_HCPTR: 76210037SARM gem5 Developers { 76310037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 76410037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 76510037SARM gem5 Developers val &= ~(1 << 14); 76610037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 76710037SARM gem5 Developers // HCPTR is RAO/WI 76810037SARM gem5 Developers bool secure_lookup = haveSecurity && 76910037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 77010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 77110037SARM gem5 Developers if (!secure_lookup) { 77210037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 77310037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 77410037SARM gem5 Developers } 77510037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 77610037SARM gem5 Developers val |= 0x33FF; 77710037SARM gem5 Developers return (val); 77810037SARM gem5 Developers } 77910037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 78010037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 78110037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 78210037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 78310037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 78410037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 78511769SCurtis.Dunham@arm.com case MISCREG_SCTLR: 78611769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 78710037SARM gem5 Developers case MISCREG_SCTLR_EL1: 78811770SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 78911770SCurtis.Dunham@arm.com case MISCREG_SCTLR_EL2: 79010037SARM gem5 Developers case MISCREG_SCTLR_EL3: 79111770SCurtis.Dunham@arm.com case MISCREG_HSCTLR: 79211769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 79310844Sandreas.sandberg@arm.com 79411772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 79511772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 79611772SCurtis.Dunham@arm.com return 0x00000031; 79711772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 79811774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 79911774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 80011774SCurtis.Dunham@arm.com return 0x00000001 80111774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 80211774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 80311774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 80411774SCurtis.Dunham@arm.com } 80511773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 80611773SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 80711773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 80811773SCurtis.Dunham@arm.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 80911773SCurtis.Dunham@arm.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 81011773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 81111773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 81211772SCurtis.Dunham@arm.com 81310037SARM gem5 Developers // Generic Timer registers 81410844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 81510844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 81610844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 81710844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 81810844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 81910844Sandreas.sandberg@arm.com 82010188Sgeoffrey.blake@arm.com default: 82110037SARM gem5 Developers break; 82210037SARM gem5 Developers 8237405SAli.Saidi@ARM.com } 8247405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 8257405SAli.Saidi@ARM.com} 8267405SAli.Saidi@ARM.com 8277405SAli.Saidi@ARM.comvoid 8287405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 8297405SAli.Saidi@ARM.com{ 8307405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 8317614Sminkyu.jeong@arm.com 83212478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 83312478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 83412478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 83512478SCurtis.Dunham@arm.com 83612478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 83711771SCurtis.Dunham@arm.com if (upper > 0) { 83812478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 83912478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 84010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 84112478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 84210037SARM gem5 Developers } else { 84312478SCurtis.Dunham@arm.com miscRegs[lower] = v; 84410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 84512478SCurtis.Dunham@arm.com misc_reg, lower, v); 84610037SARM gem5 Developers } 8477405SAli.Saidi@ARM.com} 8487405SAli.Saidi@ARM.com 84912406Sgabeblack@google.comnamespace { 85012406Sgabeblack@google.com 85112406Sgabeblack@google.comtemplate<typename T> 85212406Sgabeblack@google.comTLB * 85312406Sgabeblack@google.comgetITBPtr(T *tc) 85412406Sgabeblack@google.com{ 85512406Sgabeblack@google.com auto tlb = dynamic_cast<TLB *>(tc->getITBPtr()); 85612406Sgabeblack@google.com assert(tlb); 85712406Sgabeblack@google.com return tlb; 85812406Sgabeblack@google.com} 85912406Sgabeblack@google.com 86012406Sgabeblack@google.comtemplate<typename T> 86112406Sgabeblack@google.comTLB * 86212406Sgabeblack@google.comgetDTBPtr(T *tc) 86312406Sgabeblack@google.com{ 86412406Sgabeblack@google.com auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr()); 86512406Sgabeblack@google.com assert(tlb); 86612406Sgabeblack@google.com return tlb; 86712406Sgabeblack@google.com} 86812406Sgabeblack@google.com 86912406Sgabeblack@google.com} // anonymous namespace 87012406Sgabeblack@google.com 8717405SAli.Saidi@ARM.comvoid 8727405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 8737405SAli.Saidi@ARM.com{ 8747749SAli.Saidi@ARM.com 8757405SAli.Saidi@ARM.com MiscReg newVal = val; 8768284SAli.Saidi@ARM.com int x; 87710037SARM gem5 Developers bool secure_lookup; 87810037SARM gem5 Developers bool hyp; 8798284SAli.Saidi@ARM.com System *sys; 8808284SAli.Saidi@ARM.com ThreadContext *oc; 88110037SARM gem5 Developers uint8_t target_el; 88210037SARM gem5 Developers uint16_t asid; 88310037SARM gem5 Developers SCR scr; 8848284SAli.Saidi@ARM.com 8857405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 8867405SAli.Saidi@ARM.com updateRegMap(val); 8877749SAli.Saidi@ARM.com 8887749SAli.Saidi@ARM.com 8897749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 8907749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 8917405SAli.Saidi@ARM.com CPSR cpsr = val; 8927749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 89312406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 89412406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 8957749SAli.Saidi@ARM.com } 8967749SAli.Saidi@ARM.com 8977614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 8987614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 8997720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 9007720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 9017720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 9028887Sgeoffrey.blake@arm.com 9038887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 9048887Sgeoffrey.blake@arm.com // is connected 9058887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 9068887Sgeoffrey.blake@arm.com if (checker) { 9078887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 9088887Sgeoffrey.blake@arm.com } else { 9098887Sgeoffrey.blake@arm.com tc->pcState(pc); 9108887Sgeoffrey.blake@arm.com } 9117408Sgblack@eecs.umich.edu } else { 91210037SARM gem5 Developers#ifndef NDEBUG 91310037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 91410037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 91510037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 91610037SARM gem5 Developers miscRegName[misc_reg], val); 91710037SARM gem5 Developers else 91810037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 91910037SARM gem5 Developers miscRegName[misc_reg], val); 92010037SARM gem5 Developers } 92110037SARM gem5 Developers#endif 92210037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 9237408Sgblack@eecs.umich.edu case MISCREG_CPACR: 9247408Sgblack@eecs.umich.edu { 9258206SWilliam.Wang@arm.com 9268206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 9278206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 9288206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 9298206SWilliam.Wang@arm.com // be writable 9308206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 9318206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 9328206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 93310037SARM gem5 Developers 93410037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 93510037SARM gem5 Developers if (haveSecurity) { 93610037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 93710037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 93810037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON)) { 93910037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 94010037SARM gem5 Developers // NB: Skipping the full loop, here 94110037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 94210037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 94310037SARM gem5 Developers } 94410037SARM gem5 Developers } 94510037SARM gem5 Developers 94610037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 9478206SWilliam.Wang@arm.com newVal &= cpacrMask; 94810037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 94910037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 95010037SARM gem5 Developers miscRegName[misc_reg], newVal); 95110037SARM gem5 Developers } 95210037SARM gem5 Developers break; 95310037SARM gem5 Developers case MISCREG_CPACR_EL1: 95410037SARM gem5 Developers { 95510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 95610037SARM gem5 Developers CPACR cpacrMask = 0; 95710037SARM gem5 Developers cpacrMask.tta = ones; 95810037SARM gem5 Developers cpacrMask.fpen = ones; 95910037SARM gem5 Developers newVal &= cpacrMask; 96010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 96110037SARM gem5 Developers miscRegName[misc_reg], newVal); 96210037SARM gem5 Developers } 96310037SARM gem5 Developers break; 96410037SARM gem5 Developers case MISCREG_CPTR_EL2: 96510037SARM gem5 Developers { 96610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 96710037SARM gem5 Developers CPTR cptrMask = 0; 96810037SARM gem5 Developers cptrMask.tcpac = ones; 96910037SARM gem5 Developers cptrMask.tta = ones; 97010037SARM gem5 Developers cptrMask.tfp = ones; 97110037SARM gem5 Developers newVal &= cptrMask; 97210037SARM gem5 Developers cptrMask = 0; 97310037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 97410037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 97510037SARM gem5 Developers newVal |= cptrMask; 97610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 97710037SARM gem5 Developers miscRegName[misc_reg], newVal); 97810037SARM gem5 Developers } 97910037SARM gem5 Developers break; 98010037SARM gem5 Developers case MISCREG_CPTR_EL3: 98110037SARM gem5 Developers { 98210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 98310037SARM gem5 Developers CPTR cptrMask = 0; 98410037SARM gem5 Developers cptrMask.tcpac = ones; 98510037SARM gem5 Developers cptrMask.tta = ones; 98610037SARM gem5 Developers cptrMask.tfp = ones; 98710037SARM gem5 Developers newVal &= cptrMask; 9888206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 9898206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 9907408Sgblack@eecs.umich.edu } 9917408Sgblack@eecs.umich.edu break; 9927408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 9937731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 9948206SWilliam.Wang@arm.com return; 99510037SARM gem5 Developers 99610037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 99710037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 99810037SARM gem5 Developers return; 99910037SARM gem5 Developers 10007408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 10017408Sgblack@eecs.umich.edu { 10027408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 10037408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 10047408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 10057408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 10067408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 10077408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 10087408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 10097408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 101010037SARM gem5 Developers fpscrMask.ioe = ones; 101110037SARM gem5 Developers fpscrMask.dze = ones; 101210037SARM gem5 Developers fpscrMask.ofe = ones; 101310037SARM gem5 Developers fpscrMask.ufe = ones; 101410037SARM gem5 Developers fpscrMask.ixe = ones; 101510037SARM gem5 Developers fpscrMask.ide = ones; 10167408Sgblack@eecs.umich.edu fpscrMask.len = ones; 10177408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 10187408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 10197408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 10207408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 10217408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 10227408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 10237408Sgblack@eecs.umich.edu fpscrMask.v = ones; 10247408Sgblack@eecs.umich.edu fpscrMask.c = ones; 10257408Sgblack@eecs.umich.edu fpscrMask.z = ones; 10267408Sgblack@eecs.umich.edu fpscrMask.n = ones; 10277408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 102810037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 102910037SARM gem5 Developers ~(uint32_t)fpscrMask); 10309377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 10317408Sgblack@eecs.umich.edu } 10327408Sgblack@eecs.umich.edu break; 103310037SARM gem5 Developers case MISCREG_FPSR: 103410037SARM gem5 Developers { 103510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 103610037SARM gem5 Developers FPSCR fpscrMask = 0; 103710037SARM gem5 Developers fpscrMask.ioc = ones; 103810037SARM gem5 Developers fpscrMask.dzc = ones; 103910037SARM gem5 Developers fpscrMask.ofc = ones; 104010037SARM gem5 Developers fpscrMask.ufc = ones; 104110037SARM gem5 Developers fpscrMask.ixc = ones; 104210037SARM gem5 Developers fpscrMask.idc = ones; 104310037SARM gem5 Developers fpscrMask.qc = ones; 104410037SARM gem5 Developers fpscrMask.v = ones; 104510037SARM gem5 Developers fpscrMask.c = ones; 104610037SARM gem5 Developers fpscrMask.z = ones; 104710037SARM gem5 Developers fpscrMask.n = ones; 104810037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 104910037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 105010037SARM gem5 Developers ~(uint32_t)fpscrMask); 105110037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 105210037SARM gem5 Developers } 105310037SARM gem5 Developers break; 105410037SARM gem5 Developers case MISCREG_FPCR: 105510037SARM gem5 Developers { 105610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 105710037SARM gem5 Developers FPSCR fpscrMask = 0; 105810037SARM gem5 Developers fpscrMask.ioe = ones; 105910037SARM gem5 Developers fpscrMask.dze = ones; 106010037SARM gem5 Developers fpscrMask.ofe = ones; 106110037SARM gem5 Developers fpscrMask.ufe = ones; 106210037SARM gem5 Developers fpscrMask.ixe = ones; 106310037SARM gem5 Developers fpscrMask.ide = ones; 106410037SARM gem5 Developers fpscrMask.len = ones; 106510037SARM gem5 Developers fpscrMask.stride = ones; 106610037SARM gem5 Developers fpscrMask.rMode = ones; 106710037SARM gem5 Developers fpscrMask.fz = ones; 106810037SARM gem5 Developers fpscrMask.dn = ones; 106910037SARM gem5 Developers fpscrMask.ahp = ones; 107010037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 107110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 107210037SARM gem5 Developers ~(uint32_t)fpscrMask); 107310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 107410037SARM gem5 Developers } 107510037SARM gem5 Developers break; 10768302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 10778302SAli.Saidi@ARM.com { 10788302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 107910037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 10808302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 10818302SAli.Saidi@ARM.com } 10828302SAli.Saidi@ARM.com break; 10837783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 10847783SGiacomo.Gabrielli@arm.com { 108510037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 108610037SARM gem5 Developers (newVal & FpscrQcMask); 10877783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10887783SGiacomo.Gabrielli@arm.com } 10897783SGiacomo.Gabrielli@arm.com break; 10907783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 10917783SGiacomo.Gabrielli@arm.com { 109210037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 109310037SARM gem5 Developers (newVal & FpscrExcMask); 10947783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 10957783SGiacomo.Gabrielli@arm.com } 10967783SGiacomo.Gabrielli@arm.com break; 10977408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 10987408Sgblack@eecs.umich.edu { 10998206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 11008206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 11017408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 11027408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 110310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 11047408Sgblack@eecs.umich.edu } 11057408Sgblack@eecs.umich.edu break; 110610037SARM gem5 Developers case MISCREG_HCR: 110710037SARM gem5 Developers { 110810037SARM gem5 Developers if (!haveVirtualization) 110910037SARM gem5 Developers return; 111010037SARM gem5 Developers } 111110037SARM gem5 Developers break; 111210037SARM gem5 Developers case MISCREG_IFSR: 111310037SARM gem5 Developers { 111410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 111510037SARM gem5 Developers const uint32_t ifsrMask = 111610037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 111710037SARM gem5 Developers newVal = newVal & ~ifsrMask; 111810037SARM gem5 Developers } 111910037SARM gem5 Developers break; 112010037SARM gem5 Developers case MISCREG_DFSR: 112110037SARM gem5 Developers { 112210037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 112310037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 112410037SARM gem5 Developers newVal = newVal & ~dfsrMask; 112510037SARM gem5 Developers } 112610037SARM gem5 Developers break; 112710037SARM gem5 Developers case MISCREG_AMAIR0: 112810037SARM gem5 Developers case MISCREG_AMAIR1: 112910037SARM gem5 Developers { 113010037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 113110037SARM gem5 Developers // Valid only with LPAE 113210037SARM gem5 Developers if (!haveLPAE) 113310037SARM gem5 Developers return; 113410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 113510037SARM gem5 Developers } 113610037SARM gem5 Developers break; 113710037SARM gem5 Developers case MISCREG_SCR: 113812406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 113912406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 114010037SARM gem5 Developers break; 11417408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 11427408Sgblack@eecs.umich.edu { 11437408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 114410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 114511769SCurtis.Dunham@arm.com MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns) 114611769SCurtis.Dunham@arm.com ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS; 114710037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 11487408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 114910037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 115010037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 115112406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 115212406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 11537408Sgblack@eecs.umich.edu } 11549385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 11559385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 11569385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 115710461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 11589385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 11599385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 11609385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 11619385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 11629385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 11639385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 11649385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 11659385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 11669385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 11679385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 11689385SAndreas.Sandberg@arm.com 11699385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 11709385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 11717408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 11727408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 11737408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 117410037SARM gem5 Developers 117510037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 117610037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 117710037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 117810037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 117910037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 118010037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 118110037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 118210037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 118310037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 118410037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 11859385SAndreas.Sandberg@arm.com // ID registers are constants. 11867408Sgblack@eecs.umich.edu return; 11879385SAndreas.Sandberg@arm.com 118810037SARM gem5 Developers // TLBI all entries, EL0&1 inner sharable (ignored) 11897408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 119010037SARM gem5 Developers case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 119110037SARM gem5 Developers assert32(tc); 119210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 119310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 119410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 11958284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 11968284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 11978284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 119812406Sgabeblack@google.com getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 119912406Sgabeblack@google.com getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 12008887Sgeoffrey.blake@arm.com 12018887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 12028887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12038733Sgeoffrey.blake@arm.com if (checker) { 120412406Sgabeblack@google.com getITBPtr(checker)->flushAllSecurity(secure_lookup, 120512406Sgabeblack@google.com target_el); 120612406Sgabeblack@google.com getDTBPtr(checker)->flushAllSecurity(secure_lookup, 120712406Sgabeblack@google.com target_el); 12088733Sgeoffrey.blake@arm.com } 12098284SAli.Saidi@ARM.com } 12107408Sgblack@eecs.umich.edu return; 121110037SARM gem5 Developers // TLBI all entries, EL0&1, instruction side 12127408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 121310037SARM gem5 Developers assert32(tc); 121410037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 121510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 121610037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 121712406Sgabeblack@google.com getITBPtr(tc)->flushAllSecurity(secure_lookup, target_el); 12187408Sgblack@eecs.umich.edu return; 121910037SARM gem5 Developers // TLBI all entries, EL0&1, data side 12207408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 122110037SARM gem5 Developers assert32(tc); 122210037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 122310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 122410037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 122512406Sgabeblack@google.com getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el); 12267408Sgblack@eecs.umich.edu return; 122710037SARM gem5 Developers // TLBI based on VA, EL0&1 inner sharable (ignored) 12287408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 12297408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 123010037SARM gem5 Developers assert32(tc); 123110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 123210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 12348284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 12358284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 12368284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 123712406Sgabeblack@google.com getITBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12), 123810037SARM gem5 Developers bits(newVal, 7,0), 123910037SARM gem5 Developers secure_lookup, target_el); 124012406Sgabeblack@google.com getDTBPtr(oc)->flushMvaAsid(mbits(newVal, 31, 12), 124110037SARM gem5 Developers bits(newVal, 7,0), 124210037SARM gem5 Developers secure_lookup, target_el); 12438887Sgeoffrey.blake@arm.com 12448887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12458733Sgeoffrey.blake@arm.com if (checker) { 124612406Sgabeblack@google.com getITBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12), 124710037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 124812406Sgabeblack@google.com getDTBPtr(checker)->flushMvaAsid(mbits(newVal, 31, 12), 124910037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 12508733Sgeoffrey.blake@arm.com } 12518284SAli.Saidi@ARM.com } 12527408Sgblack@eecs.umich.edu return; 125310037SARM gem5 Developers // TLBI by ASID, EL0&1, inner sharable 12547408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 12557408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 125610037SARM gem5 Developers assert32(tc); 125710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 125810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 12608284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 12618284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 12628284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 126312406Sgabeblack@google.com getITBPtr(oc)->flushAsid(bits(newVal, 7,0), 126410037SARM gem5 Developers secure_lookup, target_el); 126512406Sgabeblack@google.com getDTBPtr(oc)->flushAsid(bits(newVal, 7,0), 126610037SARM gem5 Developers secure_lookup, target_el); 12678887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 12688733Sgeoffrey.blake@arm.com if (checker) { 126912406Sgabeblack@google.com getITBPtr(checker)->flushAsid(bits(newVal, 7,0), 127010037SARM gem5 Developers secure_lookup, target_el); 127112406Sgabeblack@google.com getDTBPtr(checker)->flushAsid(bits(newVal, 7,0), 127210037SARM gem5 Developers secure_lookup, target_el); 12738733Sgeoffrey.blake@arm.com } 12748284SAli.Saidi@ARM.com } 12757408Sgblack@eecs.umich.edu return; 127610037SARM gem5 Developers // TLBI by address, EL0&1, inner sharable (ignored) 12777408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 12787408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 127910037SARM gem5 Developers assert32(tc); 128010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 128110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 128210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 128310037SARM gem5 Developers hyp = 0; 128410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 128510037SARM gem5 Developers return; 128610037SARM gem5 Developers // TLBI by address, EL2, hypervisor mode 128710037SARM gem5 Developers case MISCREG_TLBIMVAH: 128810037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 128910037SARM gem5 Developers assert32(tc); 129010037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 129110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 129210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 129310037SARM gem5 Developers hyp = 1; 129410037SARM gem5 Developers tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 129510037SARM gem5 Developers return; 129610037SARM gem5 Developers // TLBI by address and asid, EL0&1, instruction side only 129710037SARM gem5 Developers case MISCREG_ITLBIMVA: 129810037SARM gem5 Developers assert32(tc); 129910037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 130010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 130110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 130212406Sgabeblack@google.com getITBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12), 130310037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 130410037SARM gem5 Developers return; 130510037SARM gem5 Developers // TLBI by address and asid, EL0&1, data side only 130610037SARM gem5 Developers case MISCREG_DTLBIMVA: 130710037SARM gem5 Developers assert32(tc); 130810037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 130910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 131010037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 131112406Sgabeblack@google.com getDTBPtr(tc)->flushMvaAsid(mbits(newVal, 31, 12), 131210037SARM gem5 Developers bits(newVal, 7,0), secure_lookup, target_el); 131310037SARM gem5 Developers return; 131410037SARM gem5 Developers // TLBI by ASID, EL0&1, instrution side only 131510037SARM gem5 Developers case MISCREG_ITLBIASID: 131610037SARM gem5 Developers assert32(tc); 131710037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 131810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 131910037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 132012406Sgabeblack@google.com getITBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup, 132110037SARM gem5 Developers target_el); 132210037SARM gem5 Developers return; 132310037SARM gem5 Developers // TLBI by ASID EL0&1 data size only 132410037SARM gem5 Developers case MISCREG_DTLBIASID: 132510037SARM gem5 Developers assert32(tc); 132610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 132710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 132810037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 132912406Sgabeblack@google.com getDTBPtr(tc)->flushAsid(bits(newVal, 7,0), secure_lookup, 133010037SARM gem5 Developers target_el); 133110037SARM gem5 Developers return; 133210037SARM gem5 Developers // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 133310037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 133410037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 133510037SARM gem5 Developers assert32(tc); 133610037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 133710037SARM gem5 Developers hyp = 0; 133810037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 133910037SARM gem5 Developers return; 134010037SARM gem5 Developers // TLBI all entries, EL2, hyp, 134110037SARM gem5 Developers case MISCREG_TLBIALLH: 134210037SARM gem5 Developers case MISCREG_TLBIALLHIS: 134310037SARM gem5 Developers assert32(tc); 134410037SARM gem5 Developers target_el = 1; // aarch32, use hyp bit 134510037SARM gem5 Developers hyp = 1; 134610037SARM gem5 Developers tlbiALLN(tc, hyp, target_el); 134710037SARM gem5 Developers return; 134810037SARM gem5 Developers // AArch64 TLBI: invalidate all entries EL3 134910037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 135010037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 135110037SARM gem5 Developers assert64(tc); 135210037SARM gem5 Developers target_el = 3; 135310037SARM gem5 Developers secure_lookup = true; 135410037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 135510037SARM gem5 Developers return; 135610037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 135710037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 135810037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 135910037SARM gem5 Developers // TLBI all entries, EL0&1 136010037SARM gem5 Developers case MISCREG_TLBI_ALLE1IS: 136110037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 136210037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stage 1, current VMID 136310037SARM gem5 Developers case MISCREG_TLBI_VMALLE1IS: 136410037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 136510037SARM gem5 Developers // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 136610037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 136710037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 136810037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 136910037SARM gem5 Developers assert64(tc); 137010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 137110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 137210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 137310037SARM gem5 Developers tlbiALL(tc, secure_lookup, target_el); 137410037SARM gem5 Developers return; 137510037SARM gem5 Developers // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 137610037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 137710037SARM gem5 Developers // from the last level of translation table walks 137810037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 137910037SARM gem5 Developers // TLBI all entries, EL0&1 138010037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 138110037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 138210037SARM gem5 Developers // TLBI by VA, EL3 regime stage 1, last level walk 138310037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 138410037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 138510037SARM gem5 Developers assert64(tc); 138610037SARM gem5 Developers target_el = 3; 138710037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 138810037SARM gem5 Developers secure_lookup = true; 138910037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 139010037SARM gem5 Developers return; 139110037SARM gem5 Developers // TLBI by VA, EL2 139210037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 139310037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 139410037SARM gem5 Developers // TLBI by VA, EL2, stage1 last level walk 139510037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 139610037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 139710037SARM gem5 Developers assert64(tc); 139810037SARM gem5 Developers target_el = 2; 139910037SARM gem5 Developers asid = 0xbeef; // does not matter, tlbi is global 140010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 140110037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 140210037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 140310037SARM gem5 Developers return; 140410037SARM gem5 Developers // TLBI by VA EL1 & 0, stage1, ASID, current VMID 140510037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 140610037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 140710037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 140810037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 140910037SARM gem5 Developers assert64(tc); 141010037SARM gem5 Developers asid = bits(newVal, 63, 48); 141110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 141210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 141310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 141410037SARM gem5 Developers tlbiVA(tc, newVal, asid, secure_lookup, target_el); 141510037SARM gem5 Developers return; 141610037SARM gem5 Developers // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 141710037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 141810037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 141910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 142010037SARM gem5 Developers assert64(tc); 142110037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 142210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 142310037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 14248284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 14258284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 14268284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 142710037SARM gem5 Developers asid = bits(newVal, 63, 48); 142810709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 142910037SARM gem5 Developers asid &= mask(8); 143012406Sgabeblack@google.com getITBPtr(oc)->flushAsid(asid, secure_lookup, target_el); 143112406Sgabeblack@google.com getDTBPtr(oc)->flushAsid(asid, secure_lookup, target_el); 143210037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 143310037SARM gem5 Developers if (checker) { 143412406Sgabeblack@google.com getITBPtr(checker)->flushAsid(asid, 143510037SARM gem5 Developers secure_lookup, target_el); 143612406Sgabeblack@google.com getDTBPtr(checker)->flushAsid(asid, 143710037SARM gem5 Developers secure_lookup, target_el); 143810037SARM gem5 Developers } 143910037SARM gem5 Developers } 144010037SARM gem5 Developers return; 144110037SARM gem5 Developers // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 144210037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 144310037SARM gem5 Developers // entries from the last level of translation table walks 144410037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 144510037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 144610037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 144710037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 144810037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 144910037SARM gem5 Developers assert64(tc); 145010037SARM gem5 Developers target_el = 1; // el 0 and 1 are handled together 145110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 145210037SARM gem5 Developers secure_lookup = haveSecurity && !scr.ns; 145310037SARM gem5 Developers sys = tc->getSystemPtr(); 145410037SARM gem5 Developers for (x = 0; x < sys->numContexts(); x++) { 145510037SARM gem5 Developers // @todo: extra controls on TLBI broadcast? 145610037SARM gem5 Developers oc = sys->getThreadContext(x); 145710037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 145812406Sgabeblack@google.com getITBPtr(oc)->flushMva(va, 145910037SARM gem5 Developers secure_lookup, false, target_el); 146012406Sgabeblack@google.com getDTBPtr(oc)->flushMva(va, 146110037SARM gem5 Developers secure_lookup, false, target_el); 14628887Sgeoffrey.blake@arm.com 14638887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 14648733Sgeoffrey.blake@arm.com if (checker) { 146512406Sgabeblack@google.com getITBPtr(checker)->flushMva(va, 146610037SARM gem5 Developers secure_lookup, false, target_el); 146712406Sgabeblack@google.com getDTBPtr(checker)->flushMva(va, 146810037SARM gem5 Developers secure_lookup, false, target_el); 14698733Sgeoffrey.blake@arm.com } 14708284SAli.Saidi@ARM.com } 14717408Sgblack@eecs.umich.edu return; 147210037SARM gem5 Developers // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 147310037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 147410037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 147510037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 147610037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 147710037SARM gem5 Developers assert64(tc); 147811584SDylan.Johnson@ARM.com target_el = 1; // EL 0 and 1 are handled together 147911584SDylan.Johnson@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 148011584SDylan.Johnson@ARM.com secure_lookup = haveSecurity && !scr.ns; 148111584SDylan.Johnson@ARM.com sys = tc->getSystemPtr(); 148211584SDylan.Johnson@ARM.com for (x = 0; x < sys->numContexts(); x++) { 148311584SDylan.Johnson@ARM.com oc = sys->getThreadContext(x); 148411584SDylan.Johnson@ARM.com Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; 148512406Sgabeblack@google.com getITBPtr(oc)->flushIpaVmid(ipa, 148611584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 148712406Sgabeblack@google.com getDTBPtr(oc)->flushIpaVmid(ipa, 148811584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 148911584SDylan.Johnson@ARM.com 149011584SDylan.Johnson@ARM.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 149111584SDylan.Johnson@ARM.com if (checker) { 149212406Sgabeblack@google.com getITBPtr(checker)->flushIpaVmid(ipa, 149311584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 149412406Sgabeblack@google.com getDTBPtr(checker)->flushIpaVmid(ipa, 149511584SDylan.Johnson@ARM.com secure_lookup, false, target_el); 149611584SDylan.Johnson@ARM.com } 149711584SDylan.Johnson@ARM.com } 14987405SAli.Saidi@ARM.com return; 14997583SAli.Saidi@arm.com case MISCREG_ACTLR: 15007583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 15017583SAli.Saidi@arm.com break; 150210461SAndreas.Sandberg@ARM.com 150310461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 150410461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 150510461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 150610461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 150710461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 15087583SAli.Saidi@arm.com break; 150910461SAndreas.Sandberg@ARM.com 151010461SAndreas.Sandberg@ARM.com 151110037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 151210037SARM gem5 Developers { 151310037SARM gem5 Developers HSTR hstrMask = 0; 151410037SARM gem5 Developers hstrMask.tjdbx = 1; 151510037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 151610037SARM gem5 Developers break; 151710037SARM gem5 Developers } 151810037SARM gem5 Developers case MISCREG_HCPTR: 151910037SARM gem5 Developers { 152010037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 152110037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 152210037SARM gem5 Developers secure_lookup = haveSecurity && 152310037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 152410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 152510037SARM gem5 Developers if (!secure_lookup) { 152610037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 152710037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 152810037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 152910037SARM gem5 Developers } 153010037SARM gem5 Developers break; 153110037SARM gem5 Developers } 153210037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 153310037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 153410037SARM gem5 Developers break; 153510037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 153610037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 153710037SARM gem5 Developers break; 153810037SARM gem5 Developers case MISCREG_ATS1CPR: 153910037SARM gem5 Developers case MISCREG_ATS1CPW: 154010037SARM gem5 Developers case MISCREG_ATS1CUR: 154110037SARM gem5 Developers case MISCREG_ATS1CUW: 154210037SARM gem5 Developers case MISCREG_ATS12NSOPR: 154310037SARM gem5 Developers case MISCREG_ATS12NSOPW: 154410037SARM gem5 Developers case MISCREG_ATS12NSOUR: 154510037SARM gem5 Developers case MISCREG_ATS12NSOUW: 154610037SARM gem5 Developers case MISCREG_ATS1HR: 154710037SARM gem5 Developers case MISCREG_ATS1HW: 15487436Sdam.sunwoo@arm.com { 154911608Snikos.nikoleris@arm.com Request::Flags flags = 0; 155010037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 155110037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 15527436Sdam.sunwoo@arm.com Fault fault; 15537436Sdam.sunwoo@arm.com switch(misc_reg) { 155410037SARM gem5 Developers case MISCREG_ATS1CPR: 155510037SARM gem5 Developers flags = TLB::MustBeOne; 155610037SARM gem5 Developers tranType = TLB::S1CTran; 155710037SARM gem5 Developers mode = BaseTLB::Read; 155810037SARM gem5 Developers break; 155910037SARM gem5 Developers case MISCREG_ATS1CPW: 156010037SARM gem5 Developers flags = TLB::MustBeOne; 156110037SARM gem5 Developers tranType = TLB::S1CTran; 156210037SARM gem5 Developers mode = BaseTLB::Write; 156310037SARM gem5 Developers break; 156410037SARM gem5 Developers case MISCREG_ATS1CUR: 156510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 156610037SARM gem5 Developers tranType = TLB::S1CTran; 156710037SARM gem5 Developers mode = BaseTLB::Read; 156810037SARM gem5 Developers break; 156910037SARM gem5 Developers case MISCREG_ATS1CUW: 157010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 157110037SARM gem5 Developers tranType = TLB::S1CTran; 157210037SARM gem5 Developers mode = BaseTLB::Write; 157310037SARM gem5 Developers break; 157410037SARM gem5 Developers case MISCREG_ATS12NSOPR: 157510037SARM gem5 Developers if (!haveSecurity) 157610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 157710037SARM gem5 Developers flags = TLB::MustBeOne; 157810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 157910037SARM gem5 Developers mode = BaseTLB::Read; 158010037SARM gem5 Developers break; 158110037SARM gem5 Developers case MISCREG_ATS12NSOPW: 158210037SARM gem5 Developers if (!haveSecurity) 158310037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 158410037SARM gem5 Developers flags = TLB::MustBeOne; 158510037SARM gem5 Developers tranType = TLB::S1S2NsTran; 158610037SARM gem5 Developers mode = BaseTLB::Write; 158710037SARM gem5 Developers break; 158810037SARM gem5 Developers case MISCREG_ATS12NSOUR: 158910037SARM gem5 Developers if (!haveSecurity) 159010037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 159110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159210037SARM gem5 Developers tranType = TLB::S1S2NsTran; 159310037SARM gem5 Developers mode = BaseTLB::Read; 159410037SARM gem5 Developers break; 159510037SARM gem5 Developers case MISCREG_ATS12NSOUW: 159610037SARM gem5 Developers if (!haveSecurity) 159710037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 159810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159910037SARM gem5 Developers tranType = TLB::S1S2NsTran; 160010037SARM gem5 Developers mode = BaseTLB::Write; 160110037SARM gem5 Developers break; 160210037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 160310037SARM gem5 Developers flags = TLB::MustBeOne; 160410037SARM gem5 Developers tranType = TLB::HypMode; 160510037SARM gem5 Developers mode = BaseTLB::Read; 160610037SARM gem5 Developers break; 160710037SARM gem5 Developers case MISCREG_ATS1HW: 160810037SARM gem5 Developers flags = TLB::MustBeOne; 160910037SARM gem5 Developers tranType = TLB::HypMode; 161010037SARM gem5 Developers mode = BaseTLB::Write; 161110037SARM gem5 Developers break; 16127436Sdam.sunwoo@arm.com } 161310037SARM gem5 Developers // If we're in timing mode then doing the translation in 161410037SARM gem5 Developers // functional mode then we're slightly distorting performance 161510037SARM gem5 Developers // results obtained from simulations. The translation should be 161610037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 161710037SARM gem5 Developers // can't be an atomic translation because that causes problems 161810037SARM gem5 Developers // with unexpected atomic snoop requests. 161910037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 162011560Sandreas.sandberg@arm.com Request req(0, val, 0, flags, Request::funcMasterId, 162111435Smitch.hayenga@arm.com tc->pcState().pc(), tc->contextId()); 162212406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 162312406Sgabeblack@google.com &req, tc, mode, tranType); 162410037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 162510037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 162610037SARM gem5 Developers 162710037SARM gem5 Developers MiscReg newVal; 16287436Sdam.sunwoo@arm.com if (fault == NoFault) { 162910653Sandreas.hansson@arm.com Addr paddr = req.getPaddr(); 163010037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 163110037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 163210037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 163312406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 163410037SARM gem5 Developers } else { 163510037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 163612406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 163710037SARM gem5 Developers } 16387436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 16397436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 164010037SARM gem5 Developers val, newVal); 164110037SARM gem5 Developers } else { 164210037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 164310037SARM gem5 Developers // Set fault bit and FSR 164410037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 164510037SARM gem5 Developers 164610037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 164710037SARM gem5 Developers if (newVal) { 164810037SARM gem5 Developers // LPAE - rearange fault status 164910037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 165010037SARM gem5 Developers } else { 165110037SARM gem5 Developers // VMSA - rearange fault status 165210037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 165310037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 165410037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 165510037SARM gem5 Developers } 165610037SARM gem5 Developers newVal |= 0x1; // F bit 165710037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 165810037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 165910037SARM gem5 Developers DPRINTF(MiscRegs, 166010037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 166110037SARM gem5 Developers val, fsr, newVal); 16627436Sdam.sunwoo@arm.com } 166310037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 16647436Sdam.sunwoo@arm.com return; 16657436Sdam.sunwoo@arm.com } 166610037SARM gem5 Developers case MISCREG_TTBCR: 166710037SARM gem5 Developers { 166810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 166910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 167010037SARM gem5 Developers TTBCR ttbcrMask = 0; 167110037SARM gem5 Developers TTBCR ttbcrNew = newVal; 167210037SARM gem5 Developers 167310037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 167410037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 167510037SARM gem5 Developers if (haveSecurity) { 167610037SARM gem5 Developers ttbcrMask.pd0 = ones; 167710037SARM gem5 Developers ttbcrMask.pd1 = ones; 167810037SARM gem5 Developers } 167910037SARM gem5 Developers ttbcrMask.epd0 = ones; 168010037SARM gem5 Developers ttbcrMask.irgn0 = ones; 168110037SARM gem5 Developers ttbcrMask.orgn0 = ones; 168210037SARM gem5 Developers ttbcrMask.sh0 = ones; 168310037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 168410037SARM gem5 Developers ttbcrMask.a1 = ones; 168510037SARM gem5 Developers ttbcrMask.epd1 = ones; 168610037SARM gem5 Developers ttbcrMask.irgn1 = ones; 168710037SARM gem5 Developers ttbcrMask.orgn1 = ones; 168810037SARM gem5 Developers ttbcrMask.sh1 = ones; 168910037SARM gem5 Developers if (haveLPAE) 169010037SARM gem5 Developers ttbcrMask.eae = ones; 169110037SARM gem5 Developers 169210037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 169310037SARM gem5 Developers newVal = newVal & ttbcrMask; 169410037SARM gem5 Developers } else { 169510037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 169610037SARM gem5 Developers } 169710037SARM gem5 Developers } 169812392Sjason@lowepower.com M5_FALLTHROUGH; 169910037SARM gem5 Developers case MISCREG_TTBR0: 170010037SARM gem5 Developers case MISCREG_TTBR1: 170110037SARM gem5 Developers { 170210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 170310037SARM gem5 Developers if (haveLPAE) { 170410037SARM gem5 Developers if (ttbcr.eae) { 170510037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 170610037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 170710037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 170810037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 170910037SARM gem5 Developers } 171010037SARM gem5 Developers } 171110037SARM gem5 Developers } 171212392Sjason@lowepower.com M5_FALLTHROUGH; 171310508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL1: 171410508SAli.Saidi@ARM.com { 171512406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 171612406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 171710508SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 171810508SAli.Saidi@ARM.com } 171912392Sjason@lowepower.com M5_FALLTHROUGH; 17207749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 17217749SAli.Saidi@ARM.com case MISCREG_PRRR: 17227749SAli.Saidi@ARM.com case MISCREG_NMRR: 172310037SARM gem5 Developers case MISCREG_MAIR0: 172410037SARM gem5 Developers case MISCREG_MAIR1: 17257749SAli.Saidi@ARM.com case MISCREG_DACR: 172610037SARM gem5 Developers case MISCREG_VTTBR: 172710037SARM gem5 Developers case MISCREG_SCR_EL3: 172811575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 172910037SARM gem5 Developers case MISCREG_TCR_EL1: 173010037SARM gem5 Developers case MISCREG_TCR_EL2: 173110037SARM gem5 Developers case MISCREG_TCR_EL3: 173210508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 173310508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 173411573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 173510037SARM gem5 Developers case MISCREG_TTBR0_EL1: 173610037SARM gem5 Developers case MISCREG_TTBR1_EL1: 173710037SARM gem5 Developers case MISCREG_TTBR0_EL2: 173810037SARM gem5 Developers case MISCREG_TTBR0_EL3: 173912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 174012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 17417749SAli.Saidi@ARM.com break; 174210037SARM gem5 Developers case MISCREG_NZCV: 174310037SARM gem5 Developers { 174410037SARM gem5 Developers CPSR cpsr = val; 174510037SARM gem5 Developers 174610338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 174710338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 174810338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 174910037SARM gem5 Developers } 175010037SARM gem5 Developers break; 175110037SARM gem5 Developers case MISCREG_DAIF: 175210037SARM gem5 Developers { 175310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 175410037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 175510037SARM gem5 Developers newVal = cpsr; 175610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 175710037SARM gem5 Developers } 175810037SARM gem5 Developers break; 175910037SARM gem5 Developers case MISCREG_SP_EL0: 176010037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 176110037SARM gem5 Developers break; 176210037SARM gem5 Developers case MISCREG_SP_EL1: 176310037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 176410037SARM gem5 Developers break; 176510037SARM gem5 Developers case MISCREG_SP_EL2: 176610037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 176710037SARM gem5 Developers break; 176810037SARM gem5 Developers case MISCREG_SPSEL: 176910037SARM gem5 Developers { 177010037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 177110037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 177210037SARM gem5 Developers newVal = cpsr; 177310037SARM gem5 Developers misc_reg = MISCREG_CPSR; 177410037SARM gem5 Developers } 177510037SARM gem5 Developers break; 177610037SARM gem5 Developers case MISCREG_CURRENTEL: 177710037SARM gem5 Developers { 177810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 177910037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 178010037SARM gem5 Developers newVal = cpsr; 178110037SARM gem5 Developers misc_reg = MISCREG_CPSR; 178210037SARM gem5 Developers } 178310037SARM gem5 Developers break; 178410037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 178510037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 178610037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 178710037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 178810037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 178910037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 179010037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 179110037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 179210037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 179310037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 179410037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 179510037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 179610037SARM gem5 Developers { 179710037SARM gem5 Developers RequestPtr req = new Request; 179811608Snikos.nikoleris@arm.com Request::Flags flags = 0; 179910037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 180010037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 180110037SARM gem5 Developers Fault fault; 180210037SARM gem5 Developers switch(misc_reg) { 180310037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 180410037SARM gem5 Developers flags = TLB::MustBeOne; 180511577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 180610037SARM gem5 Developers mode = BaseTLB::Read; 180710037SARM gem5 Developers break; 180810037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 180910037SARM gem5 Developers flags = TLB::MustBeOne; 181011577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 181110037SARM gem5 Developers mode = BaseTLB::Write; 181210037SARM gem5 Developers break; 181310037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 181410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 181511577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 181610037SARM gem5 Developers mode = BaseTLB::Read; 181710037SARM gem5 Developers break; 181810037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 181910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 182011577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 182110037SARM gem5 Developers mode = BaseTLB::Write; 182210037SARM gem5 Developers break; 182310037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 182410037SARM gem5 Developers flags = TLB::MustBeOne; 182511577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 182610037SARM gem5 Developers mode = BaseTLB::Read; 182710037SARM gem5 Developers break; 182810037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 182910037SARM gem5 Developers flags = TLB::MustBeOne; 183011577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 183110037SARM gem5 Developers mode = BaseTLB::Write; 183210037SARM gem5 Developers break; 183310037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 183410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 183511577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 183610037SARM gem5 Developers mode = BaseTLB::Read; 183710037SARM gem5 Developers break; 183810037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 183910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 184011577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 184110037SARM gem5 Developers mode = BaseTLB::Write; 184210037SARM gem5 Developers break; 184310037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 184410037SARM gem5 Developers flags = TLB::MustBeOne; 184511577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 184610037SARM gem5 Developers mode = BaseTLB::Read; 184710037SARM gem5 Developers break; 184810037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 184910037SARM gem5 Developers flags = TLB::MustBeOne; 185011577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 185110037SARM gem5 Developers mode = BaseTLB::Write; 185210037SARM gem5 Developers break; 185310037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 185410037SARM gem5 Developers flags = TLB::MustBeOne; 185511577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 185610037SARM gem5 Developers mode = BaseTLB::Read; 185710037SARM gem5 Developers break; 185810037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 185910037SARM gem5 Developers flags = TLB::MustBeOne; 186011577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 186110037SARM gem5 Developers mode = BaseTLB::Write; 186210037SARM gem5 Developers break; 186310037SARM gem5 Developers } 186410037SARM gem5 Developers // If we're in timing mode then doing the translation in 186510037SARM gem5 Developers // functional mode then we're slightly distorting performance 186610037SARM gem5 Developers // results obtained from simulations. The translation should be 186710037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 186810037SARM gem5 Developers // can't be an atomic translation because that causes problems 186910037SARM gem5 Developers // with unexpected atomic snoop requests. 187010037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 187111560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 187210037SARM gem5 Developers tc->pcState().pc()); 187311435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 187412406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 187512406Sgabeblack@google.com tranType); 187610037SARM gem5 Developers 187710037SARM gem5 Developers MiscReg newVal; 187810037SARM gem5 Developers if (fault == NoFault) { 187910037SARM gem5 Developers Addr paddr = req->getPaddr(); 188012406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 188110037SARM gem5 Developers uint64_t attr1 = attr >> 56; 188210037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 188310037SARM gem5 Developers attr |= 0x100; 188410037SARM gem5 Developers attr &= ~ uint64_t(0x80); 188510037SARM gem5 Developers } 188610037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 188710037SARM gem5 Developers DPRINTF(MiscRegs, 188810037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 188910037SARM gem5 Developers val, newVal); 189010037SARM gem5 Developers } else { 189110037SARM gem5 Developers ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 189210037SARM gem5 Developers // Set fault bit and FSR 189310037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 189410037SARM gem5 Developers 189511577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 189611577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 189711577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 189811577SDylan.Johnson@ARM.com // rearrange fault status 189911577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 190011577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 190111577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 190211577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 190311577SDylan.Johnson@ARM.com } else { // AArch64 190411577SDylan.Johnson@ARM.com newVal = 1; // F bit 190511577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 190611577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 190711577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 190811577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 190911577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 191011577SDylan.Johnson@ARM.com } 191110037SARM gem5 Developers DPRINTF(MiscRegs, 191210037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 191310037SARM gem5 Developers val, fsr, newVal); 191410037SARM gem5 Developers } 191510037SARM gem5 Developers delete req; 191610037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 191710037SARM gem5 Developers return; 191810037SARM gem5 Developers } 191910037SARM gem5 Developers case MISCREG_SPSR_EL3: 192010037SARM gem5 Developers case MISCREG_SPSR_EL2: 192110037SARM gem5 Developers case MISCREG_SPSR_EL1: 192210037SARM gem5 Developers // Force bits 23:21 to 0 192310037SARM gem5 Developers newVal = val & ~(0x7 << 21); 192410037SARM gem5 Developers break; 19258549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 19268549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 19278549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 192810037SARM gem5 Developers break; 192910037SARM gem5 Developers 193010037SARM gem5 Developers // Generic Timer registers 193110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 193210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 193310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 193410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 193510844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 193610037SARM gem5 Developers break; 19377405SAli.Saidi@ARM.com } 19387405SAli.Saidi@ARM.com } 19397405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 19407405SAli.Saidi@ARM.com} 19417405SAli.Saidi@ARM.com 194210037SARM gem5 Developersvoid 194310709SAndreas.Sandberg@ARM.comISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 194410709SAndreas.Sandberg@ARM.com bool secure_lookup, uint8_t target_el) 194510037SARM gem5 Developers{ 194610709SAndreas.Sandberg@ARM.com if (!haveLargeAsid64) 194710037SARM gem5 Developers asid &= mask(8); 194810037SARM gem5 Developers Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 194910037SARM gem5 Developers System *sys = tc->getSystemPtr(); 195010037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 195110037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 195212406Sgabeblack@google.com getITBPtr(oc)->flushMvaAsid(va, asid, 195310037SARM gem5 Developers secure_lookup, target_el); 195412406Sgabeblack@google.com getDTBPtr(oc)->flushMvaAsid(va, asid, 195510037SARM gem5 Developers secure_lookup, target_el); 195610037SARM gem5 Developers 195710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 195810037SARM gem5 Developers if (checker) { 195912406Sgabeblack@google.com getITBPtr(checker)->flushMvaAsid( 196010037SARM gem5 Developers va, asid, secure_lookup, target_el); 196112406Sgabeblack@google.com getDTBPtr(checker)->flushMvaAsid( 196210037SARM gem5 Developers va, asid, secure_lookup, target_el); 196310037SARM gem5 Developers } 196410037SARM gem5 Developers } 196510037SARM gem5 Developers} 196610037SARM gem5 Developers 196710037SARM gem5 Developersvoid 196810037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 196910037SARM gem5 Developers{ 197010037SARM gem5 Developers System *sys = tc->getSystemPtr(); 197110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 197210037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 197312406Sgabeblack@google.com getITBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 197412406Sgabeblack@google.com getDTBPtr(oc)->flushAllSecurity(secure_lookup, target_el); 197510037SARM gem5 Developers 197610037SARM gem5 Developers // If CheckerCPU is connected, need to notify it of a flush 197710037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 197810037SARM gem5 Developers if (checker) { 197912406Sgabeblack@google.com getITBPtr(checker)->flushAllSecurity(secure_lookup, 198010037SARM gem5 Developers target_el); 198112406Sgabeblack@google.com getDTBPtr(checker)->flushAllSecurity(secure_lookup, 198210037SARM gem5 Developers target_el); 198310037SARM gem5 Developers } 198410037SARM gem5 Developers } 198510037SARM gem5 Developers} 198610037SARM gem5 Developers 198710037SARM gem5 Developersvoid 198810037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 198910037SARM gem5 Developers{ 199010037SARM gem5 Developers System *sys = tc->getSystemPtr(); 199110037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 199210037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 199312406Sgabeblack@google.com getITBPtr(oc)->flushAllNs(hyp, target_el); 199412406Sgabeblack@google.com getDTBPtr(oc)->flushAllNs(hyp, target_el); 199510037SARM gem5 Developers 199610037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 199710037SARM gem5 Developers if (checker) { 199812406Sgabeblack@google.com getITBPtr(checker)->flushAllNs(hyp, target_el); 199912406Sgabeblack@google.com getDTBPtr(checker)->flushAllNs(hyp, target_el); 200010037SARM gem5 Developers } 200110037SARM gem5 Developers } 200210037SARM gem5 Developers} 200310037SARM gem5 Developers 200410037SARM gem5 Developersvoid 200510037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 200610037SARM gem5 Developers uint8_t target_el) 200710037SARM gem5 Developers{ 200810037SARM gem5 Developers System *sys = tc->getSystemPtr(); 200910037SARM gem5 Developers for (int x = 0; x < sys->numContexts(); x++) { 201010037SARM gem5 Developers ThreadContext *oc = sys->getThreadContext(x); 201112406Sgabeblack@google.com getITBPtr(oc)->flushMva(mbits(newVal, 31,12), 201210037SARM gem5 Developers secure_lookup, hyp, target_el); 201312406Sgabeblack@google.com getDTBPtr(oc)->flushMva(mbits(newVal, 31,12), 201410037SARM gem5 Developers secure_lookup, hyp, target_el); 201510037SARM gem5 Developers 201610037SARM gem5 Developers CheckerCPU *checker = oc->getCheckerCpuPtr(); 201710037SARM gem5 Developers if (checker) { 201812406Sgabeblack@google.com getITBPtr(checker)->flushMva(mbits(newVal, 31,12), 201910037SARM gem5 Developers secure_lookup, hyp, target_el); 202012406Sgabeblack@google.com getDTBPtr(checker)->flushMva(mbits(newVal, 31,12), 202110037SARM gem5 Developers secure_lookup, hyp, target_el); 202210037SARM gem5 Developers } 202310037SARM gem5 Developers } 202410037SARM gem5 Developers} 202510037SARM gem5 Developers 202610844Sandreas.sandberg@arm.comBaseISADevice & 202710844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 202810037SARM gem5 Developers{ 202910844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 203010844Sandreas.sandberg@arm.com // to access the timer. 203110844Sandreas.sandberg@arm.com if (timer) 203210844Sandreas.sandberg@arm.com return *timer.get(); 203310844Sandreas.sandberg@arm.com 203410844Sandreas.sandberg@arm.com assert(system); 203510844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 203610844Sandreas.sandberg@arm.com if (!generic_timer) { 203710844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 203810844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 203910037SARM gem5 Developers } 204010037SARM gem5 Developers 204111150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 204210844Sandreas.sandberg@arm.com return *timer.get(); 204310037SARM gem5 Developers} 204410037SARM gem5 Developers 20457405SAli.Saidi@ARM.com} 20469384SAndreas.Sandberg@arm.com 20479384SAndreas.Sandberg@arm.comArmISA::ISA * 20489384SAndreas.Sandberg@arm.comArmISAParams::create() 20499384SAndreas.Sandberg@arm.com{ 20509384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 20519384SAndreas.Sandberg@arm.com} 2052