isa_traits.hh revision 1858
12789Sktlim@umich.edu/* 29814Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38733Sgeoffrey.blake@arm.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 142789Sktlim@umich.edu * this software without specific prior written permission. 152789Sktlim@umich.edu * 162789Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172789Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182789Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192789Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202789Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212789Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222789Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232789Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242789Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252789Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262789Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272789Sktlim@umich.edu */ 282789Sktlim@umich.edu 292789Sktlim@umich.edu#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 302789Sktlim@umich.edu#define __ARCH_ALPHA_ISA_TRAITS_HH__ 312789Sktlim@umich.edu 322789Sktlim@umich.edu#include "arch/alpha/faults.hh" 332789Sktlim@umich.edu#include "base/misc.hh" 342789Sktlim@umich.edu#include "config/full_system.hh" 352789Sktlim@umich.edu#include "sim/host.hh" 362789Sktlim@umich.edu 372789Sktlim@umich.educlass FastCPU; 382789Sktlim@umich.educlass FullCPU; 392789Sktlim@umich.educlass Checkpoint; 402789Sktlim@umich.edu 418733Sgeoffrey.blake@arm.com#define TARGET_ALPHA 422789Sktlim@umich.edu 432789Sktlim@umich.edutemplate <class ISA> class StaticInst; 442789Sktlim@umich.edutemplate <class ISA> class StaticInstPtr; 452789Sktlim@umich.edu 462789Sktlim@umich.edunamespace EV5 { 478793Sgblack@eecs.umich.eduint DTB_ASN_ASN(uint64_t reg); 488793Sgblack@eecs.umich.eduint ITB_ASN_ASN(uint64_t reg); 498229Snate@binkert.org} 502789Sktlim@umich.edu 512789Sktlim@umich.educlass AlphaISA 523348Sbinkertn@umich.edu{ 532789Sktlim@umich.edu public: 548733Sgeoffrey.blake@arm.com 558887Sgeoffrey.blake@arm.com typedef uint32_t MachInst; 568733Sgeoffrey.blake@arm.com typedef uint64_t Addr; 572789Sktlim@umich.edu typedef uint8_t RegIndex; 582789Sktlim@umich.edu 598733Sgeoffrey.blake@arm.com enum { 602789Sktlim@umich.edu MemoryEnd = 0xffffffffffffffffULL, 612789Sktlim@umich.edu 622789Sktlim@umich.edu NumIntRegs = 32, 632789Sktlim@umich.edu NumFloatRegs = 32, 648832SAli.Saidi@ARM.com NumMiscRegs = 32, 652789Sktlim@umich.edu 662789Sktlim@umich.edu MaxRegsOfAnyType = 32, 672789Sktlim@umich.edu // Static instruction parameters 689176Sandreas.hansson@arm.com MaxInstSrcRegs = 3, 699176Sandreas.hansson@arm.com MaxInstDestRegs = 2, 702789Sktlim@umich.edu 712789Sktlim@umich.edu // semantically meaningful register indices 728733Sgeoffrey.blake@arm.com ZeroReg = 31, // architecturally meaningful 738733Sgeoffrey.blake@arm.com // the rest of these depend on the ABI 742789Sktlim@umich.edu StackPointerReg = 30, 752789Sktlim@umich.edu GlobalPointerReg = 29, 762789Sktlim@umich.edu ReturnAddressReg = 26, 772789Sktlim@umich.edu ReturnValueReg = 0, 782789Sktlim@umich.edu ArgumentReg0 = 16, 792789Sktlim@umich.edu ArgumentReg1 = 17, 802789Sktlim@umich.edu ArgumentReg2 = 18, 8110034SGeoffrey.Blake@arm.com ArgumentReg3 = 19, 822789Sktlim@umich.edu ArgumentReg4 = 20, 832789Sktlim@umich.edu ArgumentReg5 = 21, 842789Sktlim@umich.edu 852789Sktlim@umich.edu LogVMPageSize = 13, // 8K bytes 862789Sktlim@umich.edu VMPageSize = (1 << LogVMPageSize), 878733Sgeoffrey.blake@arm.com 882789Sktlim@umich.edu BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 898733Sgeoffrey.blake@arm.com 902789Sktlim@umich.edu WordBytes = 4, 912789Sktlim@umich.edu HalfwordBytes = 2, 922789Sktlim@umich.edu ByteBytes = 1, 932789Sktlim@umich.edu DepNA = 0, 942789Sktlim@umich.edu }; 952789Sktlim@umich.edu 962789Sktlim@umich.edu // These enumerate all the registers for dependence tracking. 972789Sktlim@umich.edu enum DependenceTags { 982789Sktlim@umich.edu // 0..31 are the integer regs 0..31 999384SAndreas.Sandberg@arm.com // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1009384SAndreas.Sandberg@arm.com FP_Base_DepTag = 32, 1012789Sktlim@umich.edu Ctrl_Base_DepTag = 64, 1022789Sktlim@umich.edu Fpcr_DepTag = 64, // floating point control register 1038887Sgeoffrey.blake@arm.com Uniq_DepTag = 65, 1049384SAndreas.Sandberg@arm.com IPR_Base_DepTag = 66 1059384SAndreas.Sandberg@arm.com }; 1068887Sgeoffrey.blake@arm.com 1078887Sgeoffrey.blake@arm.com typedef uint64_t IntReg; 1088887Sgeoffrey.blake@arm.com typedef IntReg IntRegFile[NumIntRegs]; 1099384SAndreas.Sandberg@arm.com 1108887Sgeoffrey.blake@arm.com // floating point register file entry type 1112789Sktlim@umich.edu typedef union { 1122789Sktlim@umich.edu uint64_t q; 1132789Sktlim@umich.edu double d; 1142789Sktlim@umich.edu } FloatReg; 1158887Sgeoffrey.blake@arm.com 1168887Sgeoffrey.blake@arm.com typedef union { 1172789Sktlim@umich.edu uint64_t q[NumFloatRegs]; // integer qword view 1182789Sktlim@umich.edu double d[NumFloatRegs]; // double-precision floating point view 1192789Sktlim@umich.edu } FloatRegFile; 1209608Sandreas.hansson@arm.com 1212789Sktlim@umich.edu // control register file contents 1222789Sktlim@umich.edu typedef uint64_t MiscReg; 1232789Sktlim@umich.edu typedef struct { 1242789Sktlim@umich.edu uint64_t fpcr; // floating point condition codes 1252789Sktlim@umich.edu uint64_t uniq; // process-unique register 1269608Sandreas.hansson@arm.com bool lock_flag; // lock flag for LL/SC 1272789Sktlim@umich.edu Addr lock_addr; // lock address for LL/SC 1282789Sktlim@umich.edu } MiscRegFile; 1292789Sktlim@umich.edu 1302789Sktlim@umich.edustatic const Addr PageShift = 13; 1312789Sktlim@umich.edustatic const Addr PageBytes = ULL(1) << PageShift; 1322789Sktlim@umich.edustatic const Addr PageMask = ~(PageBytes - 1); 1332789Sktlim@umich.edustatic const Addr PageOffset = PageBytes - 1; 1342789Sktlim@umich.edu 1352789Sktlim@umich.edu#if FULL_SYSTEM 1362789Sktlim@umich.edu 1372789Sktlim@umich.edu typedef uint64_t InternalProcReg; 1382789Sktlim@umich.edu 1392789Sktlim@umich.edu#include "arch/alpha/isa_fullsys_traits.hh" 1402789Sktlim@umich.edu 1412789Sktlim@umich.edu#else 1428733Sgeoffrey.blake@arm.com enum { 1432789Sktlim@umich.edu NumInternalProcRegs = 0 1448733Sgeoffrey.blake@arm.com }; 1458733Sgeoffrey.blake@arm.com#endif 1469814Sandreas.hansson@arm.com 1478733Sgeoffrey.blake@arm.com enum { 1488733Sgeoffrey.blake@arm.com TotalNumRegs = 1498733Sgeoffrey.blake@arm.com NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 1502789Sktlim@umich.edu }; 1512789Sktlim@umich.edu 1528733Sgeoffrey.blake@arm.com enum { 1538733Sgeoffrey.blake@arm.com TotalDataRegs = NumIntRegs + NumFloatRegs 1542789Sktlim@umich.edu }; 1558733Sgeoffrey.blake@arm.com 1568733Sgeoffrey.blake@arm.com typedef union { 1578733Sgeoffrey.blake@arm.com IntReg intreg; 1588887Sgeoffrey.blake@arm.com FloatReg fpreg; 1592789Sktlim@umich.edu MiscReg ctrlreg; 1608733Sgeoffrey.blake@arm.com } AnyReg; 1618733Sgeoffrey.blake@arm.com 1622789Sktlim@umich.edu struct RegFile { 1638733Sgeoffrey.blake@arm.com IntRegFile intRegFile; // (signed) integer register file 1648733Sgeoffrey.blake@arm.com FloatRegFile floatRegFile; // floating point register file 1658733Sgeoffrey.blake@arm.com MiscRegFile miscRegs; // control register file 1668733Sgeoffrey.blake@arm.com Addr pc; // program counter 1678733Sgeoffrey.blake@arm.com Addr npc; // next-cycle program counter 1688733Sgeoffrey.blake@arm.com#if FULL_SYSTEM 1698733Sgeoffrey.blake@arm.com IntReg palregs[NumIntRegs]; // PAL shadow registers 1708733Sgeoffrey.blake@arm.com InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 1718733Sgeoffrey.blake@arm.com int intrflag; // interrupt flag 1728733Sgeoffrey.blake@arm.com bool pal_shadow; // using pal_shadow registers 17310342SCurtis.Dunham@arm.com inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 1748733Sgeoffrey.blake@arm.com inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 1758733Sgeoffrey.blake@arm.com#endif // FULL_SYSTEM 1768733Sgeoffrey.blake@arm.com 1778733Sgeoffrey.blake@arm.com void serialize(std::ostream &os); 1788733Sgeoffrey.blake@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 1798733Sgeoffrey.blake@arm.com }; 1808733Sgeoffrey.blake@arm.com 1818733Sgeoffrey.blake@arm.com static StaticInstPtr<AlphaISA> decodeInst(MachInst); 1828733Sgeoffrey.blake@arm.com 1838733Sgeoffrey.blake@arm.com // return a no-op instruction... used for instruction fetch faults 1848733Sgeoffrey.blake@arm.com static const MachInst NoopMachInst; 1858733Sgeoffrey.blake@arm.com 1868733Sgeoffrey.blake@arm.com enum annotes { 1878733Sgeoffrey.blake@arm.com ANNOTE_NONE = 0, 1888733Sgeoffrey.blake@arm.com // An impossible number for instruction annotations 1898733Sgeoffrey.blake@arm.com ITOUCH_ANNOTE = 0xffffffff, 1908733Sgeoffrey.blake@arm.com }; 1918733Sgeoffrey.blake@arm.com 1928733Sgeoffrey.blake@arm.com static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 1938733Sgeoffrey.blake@arm.com panic("register classification not implemented"); 1948733Sgeoffrey.blake@arm.com return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 1958733Sgeoffrey.blake@arm.com } 1968733Sgeoffrey.blake@arm.com 1978733Sgeoffrey.blake@arm.com static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 1988733Sgeoffrey.blake@arm.com panic("register classification not implemented"); 1998733Sgeoffrey.blake@arm.com return (reg >= 9 && reg <= 15); 2008733Sgeoffrey.blake@arm.com } 2018733Sgeoffrey.blake@arm.com 2028733Sgeoffrey.blake@arm.com static inline bool isCallerSaveFloatRegister(unsigned int reg) { 2038733Sgeoffrey.blake@arm.com panic("register classification not implemented"); 2048733Sgeoffrey.blake@arm.com return false; 2058733Sgeoffrey.blake@arm.com } 2068733Sgeoffrey.blake@arm.com 2078733Sgeoffrey.blake@arm.com static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 2088733Sgeoffrey.blake@arm.com panic("register classification not implemented"); 2098733Sgeoffrey.blake@arm.com return false; 2108733Sgeoffrey.blake@arm.com } 2118733Sgeoffrey.blake@arm.com 2128733Sgeoffrey.blake@arm.com static inline Addr alignAddress(const Addr &addr, 2138733Sgeoffrey.blake@arm.com unsigned int nbytes) { 2142789Sktlim@umich.edu return (addr & ~(nbytes - 1)); 2152789Sktlim@umich.edu } 2168733Sgeoffrey.blake@arm.com 2178733Sgeoffrey.blake@arm.com // Instruction address compression hooks 2188733Sgeoffrey.blake@arm.com static inline Addr realPCToFetchPC(const Addr &addr) { 2198733Sgeoffrey.blake@arm.com return addr; 2208733Sgeoffrey.blake@arm.com } 2218733Sgeoffrey.blake@arm.com 2222789Sktlim@umich.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 2238733Sgeoffrey.blake@arm.com return addr; 2242789Sktlim@umich.edu } 2252789Sktlim@umich.edu 2268733Sgeoffrey.blake@arm.com // the size of "fetched" instructions (not necessarily the size 2278733Sgeoffrey.blake@arm.com // of real instructions for PISA) 2288733Sgeoffrey.blake@arm.com static inline size_t fetchInstSize() { 2298733Sgeoffrey.blake@arm.com return sizeof(MachInst); 2308733Sgeoffrey.blake@arm.com } 2318733Sgeoffrey.blake@arm.com 2328733Sgeoffrey.blake@arm.com static inline MachInst makeRegisterCopy(int dest, int src) { 2338733Sgeoffrey.blake@arm.com panic("makeRegisterCopy not implemented"); 2342789Sktlim@umich.edu return 0; 2358733Sgeoffrey.blake@arm.com } 2362789Sktlim@umich.edu 2379814Sandreas.hansson@arm.com // Machine operations 2382789Sktlim@umich.edu 2398733Sgeoffrey.blake@arm.com static void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 2408733Sgeoffrey.blake@arm.com int regnum); 2412789Sktlim@umich.edu 2428733Sgeoffrey.blake@arm.com static void restoreMachineReg(RegFile ®s, const AnyReg ®, 2438733Sgeoffrey.blake@arm.com int regnum); 2448733Sgeoffrey.blake@arm.com 2458832SAli.Saidi@ARM.com#if 0 2462789Sktlim@umich.edu static void serializeSpecialRegs(const Serializable::Proxy &proxy, 2478733Sgeoffrey.blake@arm.com const RegFile ®s); 2488733Sgeoffrey.blake@arm.com 2492789Sktlim@umich.edu static void unserializeSpecialRegs(const IniFile *db, 2508733Sgeoffrey.blake@arm.com const std::string &category, 2518733Sgeoffrey.blake@arm.com ConfigNode *node, 2528733Sgeoffrey.blake@arm.com RegFile ®s); 2538733Sgeoffrey.blake@arm.com#endif 2548733Sgeoffrey.blake@arm.com 2558733Sgeoffrey.blake@arm.com /** 2568733Sgeoffrey.blake@arm.com * Function to insure ISA semantics about 0 registers. 2578733Sgeoffrey.blake@arm.com * @param xc The execution context. 2588733Sgeoffrey.blake@arm.com */ 2598733Sgeoffrey.blake@arm.com template <class XC> 2608733Sgeoffrey.blake@arm.com static void zeroRegisters(XC *xc); 2618733Sgeoffrey.blake@arm.com}; 2628733Sgeoffrey.blake@arm.com 2638733Sgeoffrey.blake@arm.com 2648990SAli.Saidi@ARM.comtypedef AlphaISA TheISA; 2658733Sgeoffrey.blake@arm.com 2668733Sgeoffrey.blake@arm.comtypedef TheISA::MachInst MachInst; 2678733Sgeoffrey.blake@arm.comtypedef TheISA::Addr Addr; 2688733Sgeoffrey.blake@arm.comtypedef TheISA::RegIndex RegIndex; 2698733Sgeoffrey.blake@arm.comtypedef TheISA::IntReg IntReg; 2708733Sgeoffrey.blake@arm.comtypedef TheISA::IntRegFile IntRegFile; 2718990SAli.Saidi@ARM.comtypedef TheISA::FloatReg FloatReg; 2728733Sgeoffrey.blake@arm.comtypedef TheISA::FloatRegFile FloatRegFile; 2738733Sgeoffrey.blake@arm.comtypedef TheISA::MiscReg MiscReg; 2748733Sgeoffrey.blake@arm.comtypedef TheISA::MiscRegFile MiscRegFile; 2758733Sgeoffrey.blake@arm.comtypedef TheISA::AnyReg AnyReg; 2768733Sgeoffrey.blake@arm.comtypedef TheISA::RegFile RegFile; 2778733Sgeoffrey.blake@arm.com 2788733Sgeoffrey.blake@arm.comconst int NumIntRegs = TheISA::NumIntRegs; 2798733Sgeoffrey.blake@arm.comconst int NumFloatRegs = TheISA::NumFloatRegs; 2808733Sgeoffrey.blake@arm.comconst int NumMiscRegs = TheISA::NumMiscRegs; 2818733Sgeoffrey.blake@arm.comconst int TotalNumRegs = TheISA::TotalNumRegs; 2828733Sgeoffrey.blake@arm.comconst int VMPageSize = TheISA::VMPageSize; 2838733Sgeoffrey.blake@arm.comconst int LogVMPageSize = TheISA::LogVMPageSize; 2848733Sgeoffrey.blake@arm.comconst int ZeroReg = TheISA::ZeroReg; 2858733Sgeoffrey.blake@arm.comconst int StackPointerReg = TheISA::StackPointerReg; 2868733Sgeoffrey.blake@arm.comconst int GlobalPointerReg = TheISA::GlobalPointerReg; 2878733Sgeoffrey.blake@arm.comconst int ReturnAddressReg = TheISA::ReturnAddressReg; 2888733Sgeoffrey.blake@arm.comconst int ReturnValueReg = TheISA::ReturnValueReg; 2898733Sgeoffrey.blake@arm.comconst int ArgumentReg0 = TheISA::ArgumentReg0; 2908733Sgeoffrey.blake@arm.comconst int ArgumentReg1 = TheISA::ArgumentReg1; 2918733Sgeoffrey.blake@arm.comconst int ArgumentReg2 = TheISA::ArgumentReg2; 2928733Sgeoffrey.blake@arm.comconst int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 2938733Sgeoffrey.blake@arm.comconst int MaxAddr = (Addr)-1; 2948733Sgeoffrey.blake@arm.com 2958733Sgeoffrey.blake@arm.com#if !FULL_SYSTEM 2968733Sgeoffrey.blake@arm.comclass SyscallReturn { 2978733Sgeoffrey.blake@arm.com public: 2988733Sgeoffrey.blake@arm.com template <class T> 2998733Sgeoffrey.blake@arm.com SyscallReturn(T v, bool s) 3008733Sgeoffrey.blake@arm.com { 3018733Sgeoffrey.blake@arm.com retval = (uint64_t)v; 3028733Sgeoffrey.blake@arm.com success = s; 3038733Sgeoffrey.blake@arm.com } 3048733Sgeoffrey.blake@arm.com 3058733Sgeoffrey.blake@arm.com template <class T> 3068733Sgeoffrey.blake@arm.com SyscallReturn(T v) 3078733Sgeoffrey.blake@arm.com { 3088733Sgeoffrey.blake@arm.com success = (v >= 0); 3098733Sgeoffrey.blake@arm.com retval = (uint64_t)v; 3108733Sgeoffrey.blake@arm.com } 3118733Sgeoffrey.blake@arm.com 3128733Sgeoffrey.blake@arm.com ~SyscallReturn() {} 3138733Sgeoffrey.blake@arm.com 3148733Sgeoffrey.blake@arm.com SyscallReturn& operator=(const SyscallReturn& s) { 3158733Sgeoffrey.blake@arm.com retval = s.retval; 3162789Sktlim@umich.edu success = s.success; 3172789Sktlim@umich.edu return *this; 3182789Sktlim@umich.edu } 3192789Sktlim@umich.edu 3202789Sktlim@umich.edu bool successful() { return success; } 3212789Sktlim@umich.edu uint64_t value() { return retval; } 3222789Sktlim@umich.edu 3232789Sktlim@umich.edu 3248733Sgeoffrey.blake@arm.com private: 3258733Sgeoffrey.blake@arm.com uint64_t retval; 3268733Sgeoffrey.blake@arm.com bool success; 3272789Sktlim@umich.edu}; 3288733Sgeoffrey.blake@arm.com 3298733Sgeoffrey.blake@arm.com#endif 3302789Sktlim@umich.edu 3318733Sgeoffrey.blake@arm.com 3328733Sgeoffrey.blake@arm.com#if FULL_SYSTEM 3338733Sgeoffrey.blake@arm.comtypedef TheISA::InternalProcReg InternalProcReg; 3348733Sgeoffrey.blake@arm.comconst int NumInternalProcRegs = TheISA::NumInternalProcRegs; 3358733Sgeoffrey.blake@arm.comconst int NumInterruptLevels = TheISA::NumInterruptLevels; 3368733Sgeoffrey.blake@arm.com 3378733Sgeoffrey.blake@arm.com#include "arch/alpha/ev5.hh" 3382789Sktlim@umich.edu#endif 3392789Sktlim@umich.edu 3408733Sgeoffrey.blake@arm.com#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 3418733Sgeoffrey.blake@arm.com