isa_traits.hh revision 1858 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32#include "arch/alpha/faults.hh"
33#include "base/misc.hh"
34#include "config/full_system.hh"
35#include "sim/host.hh"
36
37class FastCPU;
38class FullCPU;
39class Checkpoint;
40
41#define TARGET_ALPHA
42
43template <class ISA> class StaticInst;
44template <class ISA> class StaticInstPtr;
45
46namespace EV5 {
47int DTB_ASN_ASN(uint64_t reg);
48int ITB_ASN_ASN(uint64_t reg);
49}
50
51class AlphaISA
52{
53  public:
54
55    typedef uint32_t MachInst;
56    typedef uint64_t Addr;
57    typedef uint8_t  RegIndex;
58
59    enum {
60        MemoryEnd = 0xffffffffffffffffULL,
61
62        NumIntRegs = 32,
63        NumFloatRegs = 32,
64        NumMiscRegs = 32,
65
66        MaxRegsOfAnyType = 32,
67        // Static instruction parameters
68        MaxInstSrcRegs = 3,
69        MaxInstDestRegs = 2,
70
71        // semantically meaningful register indices
72        ZeroReg = 31,	// architecturally meaningful
73        // the rest of these depend on the ABI
74        StackPointerReg = 30,
75        GlobalPointerReg = 29,
76        ReturnAddressReg = 26,
77        ReturnValueReg = 0,
78        ArgumentReg0 = 16,
79        ArgumentReg1 = 17,
80        ArgumentReg2 = 18,
81        ArgumentReg3 = 19,
82        ArgumentReg4 = 20,
83        ArgumentReg5 = 21,
84
85        LogVMPageSize = 13,	// 8K bytes
86        VMPageSize = (1 << LogVMPageSize),
87
88        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
89
90        WordBytes = 4,
91        HalfwordBytes = 2,
92        ByteBytes = 1,
93        DepNA = 0,
94    };
95
96    // These enumerate all the registers for dependence tracking.
97    enum DependenceTags {
98        // 0..31 are the integer regs 0..31
99        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
100        FP_Base_DepTag = 32,
101        Ctrl_Base_DepTag = 64,
102        Fpcr_DepTag = 64,		// floating point control register
103        Uniq_DepTag = 65,
104        IPR_Base_DepTag = 66
105    };
106
107    typedef uint64_t IntReg;
108    typedef IntReg IntRegFile[NumIntRegs];
109
110    // floating point register file entry type
111    typedef union {
112        uint64_t q;
113        double d;
114    } FloatReg;
115
116    typedef union {
117        uint64_t q[NumFloatRegs];	// integer qword view
118        double d[NumFloatRegs];		// double-precision floating point view
119    } FloatRegFile;
120
121    // control register file contents
122    typedef uint64_t MiscReg;
123    typedef struct {
124        uint64_t	fpcr;		// floating point condition codes
125        uint64_t	uniq;		// process-unique register
126        bool		lock_flag;	// lock flag for LL/SC
127        Addr		lock_addr;	// lock address for LL/SC
128    } MiscRegFile;
129
130static const Addr PageShift = 13;
131static const Addr PageBytes = ULL(1) << PageShift;
132static const Addr PageMask = ~(PageBytes - 1);
133static const Addr PageOffset = PageBytes - 1;
134
135#if FULL_SYSTEM
136
137    typedef uint64_t InternalProcReg;
138
139#include "arch/alpha/isa_fullsys_traits.hh"
140
141#else
142    enum {
143        NumInternalProcRegs = 0
144    };
145#endif
146
147    enum {
148        TotalNumRegs =
149        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
150    };
151
152    enum {
153        TotalDataRegs = NumIntRegs + NumFloatRegs
154    };
155
156    typedef union {
157        IntReg  intreg;
158        FloatReg   fpreg;
159        MiscReg ctrlreg;
160    } AnyReg;
161
162    struct RegFile {
163        IntRegFile intRegFile;		// (signed) integer register file
164        FloatRegFile floatRegFile;	// floating point register file
165        MiscRegFile miscRegs;		// control register file
166        Addr pc;			// program counter
167        Addr npc;			// next-cycle program counter
168#if FULL_SYSTEM
169        IntReg palregs[NumIntRegs];	// PAL shadow registers
170        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
171        int intrflag;			// interrupt flag
172        bool pal_shadow;		// using pal_shadow registers
173        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
174        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
175#endif // FULL_SYSTEM
176
177        void serialize(std::ostream &os);
178        void unserialize(Checkpoint *cp, const std::string &section);
179    };
180
181    static StaticInstPtr<AlphaISA> decodeInst(MachInst);
182
183    // return a no-op instruction... used for instruction fetch faults
184    static const MachInst NoopMachInst;
185
186    enum annotes {
187        ANNOTE_NONE = 0,
188        // An impossible number for instruction annotations
189        ITOUCH_ANNOTE = 0xffffffff,
190    };
191
192    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
193        panic("register classification not implemented");
194        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
195    }
196
197    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
198        panic("register classification not implemented");
199        return (reg >= 9 && reg <= 15);
200    }
201
202    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
203        panic("register classification not implemented");
204        return false;
205    }
206
207    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
208        panic("register classification not implemented");
209        return false;
210    }
211
212    static inline Addr alignAddress(const Addr &addr,
213                                         unsigned int nbytes) {
214        return (addr & ~(nbytes - 1));
215    }
216
217    // Instruction address compression hooks
218    static inline Addr realPCToFetchPC(const Addr &addr) {
219        return addr;
220    }
221
222    static inline Addr fetchPCToRealPC(const Addr &addr) {
223        return addr;
224    }
225
226    // the size of "fetched" instructions (not necessarily the size
227    // of real instructions for PISA)
228    static inline size_t fetchInstSize() {
229        return sizeof(MachInst);
230    }
231
232    static inline MachInst makeRegisterCopy(int dest, int src) {
233        panic("makeRegisterCopy not implemented");
234        return 0;
235    }
236
237    // Machine operations
238
239    static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
240                               int regnum);
241
242    static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
243                                  int regnum);
244
245#if 0
246    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
247                                     const RegFile &regs);
248
249    static void unserializeSpecialRegs(const IniFile *db,
250                                       const std::string &category,
251                                       ConfigNode *node,
252                                       RegFile &regs);
253#endif
254
255    /**
256     * Function to insure ISA semantics about 0 registers.
257     * @param xc The execution context.
258     */
259    template <class XC>
260    static void zeroRegisters(XC *xc);
261};
262
263
264typedef AlphaISA TheISA;
265
266typedef TheISA::MachInst MachInst;
267typedef TheISA::Addr Addr;
268typedef TheISA::RegIndex RegIndex;
269typedef TheISA::IntReg IntReg;
270typedef TheISA::IntRegFile IntRegFile;
271typedef TheISA::FloatReg FloatReg;
272typedef TheISA::FloatRegFile FloatRegFile;
273typedef TheISA::MiscReg MiscReg;
274typedef TheISA::MiscRegFile MiscRegFile;
275typedef TheISA::AnyReg AnyReg;
276typedef TheISA::RegFile RegFile;
277
278const int NumIntRegs   = TheISA::NumIntRegs;
279const int NumFloatRegs = TheISA::NumFloatRegs;
280const int NumMiscRegs  = TheISA::NumMiscRegs;
281const int TotalNumRegs = TheISA::TotalNumRegs;
282const int VMPageSize   = TheISA::VMPageSize;
283const int LogVMPageSize   = TheISA::LogVMPageSize;
284const int ZeroReg = TheISA::ZeroReg;
285const int StackPointerReg = TheISA::StackPointerReg;
286const int GlobalPointerReg = TheISA::GlobalPointerReg;
287const int ReturnAddressReg = TheISA::ReturnAddressReg;
288const int ReturnValueReg = TheISA::ReturnValueReg;
289const int ArgumentReg0 = TheISA::ArgumentReg0;
290const int ArgumentReg1 = TheISA::ArgumentReg1;
291const int ArgumentReg2 = TheISA::ArgumentReg2;
292const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
293const int MaxAddr = (Addr)-1;
294
295#if !FULL_SYSTEM
296class SyscallReturn {
297        public:
298           template <class T>
299           SyscallReturn(T v, bool s)
300           {
301               retval = (uint64_t)v;
302               success = s;
303           }
304
305           template <class T>
306           SyscallReturn(T v)
307           {
308               success = (v >= 0);
309               retval = (uint64_t)v;
310           }
311
312           ~SyscallReturn() {}
313
314           SyscallReturn& operator=(const SyscallReturn& s) {
315               retval = s.retval;
316               success = s.success;
317               return *this;
318           }
319
320           bool successful() { return success; }
321           uint64_t value() { return retval; }
322
323
324       private:
325           uint64_t retval;
326           bool success;
327};
328
329#endif
330
331
332#if FULL_SYSTEM
333typedef TheISA::InternalProcReg InternalProcReg;
334const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
335const int NumInterruptLevels = TheISA::NumInterruptLevels;
336
337#include "arch/alpha/ev5.hh"
338#endif
339
340#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
341