FSConfig.py revision 8929
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 448528SAli.Saidi@ARM.comfrom m5.util import convert 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 536122SSteve.Reinhardt@amd.comclass MemBus(Bus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 584520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598713Sandreas.hansson@arm.com IO_address_space_base = 0x80000000000 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 702934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 716122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 728713Sandreas.hansson@arm.com # By default the bridge responds to all addresses above the I/O 738713Sandreas.hansson@arm.com # base address (including the PCI config space) 748713Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns', 758713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 765266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 778839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 788839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 798839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 802934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 812934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 822995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 832934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 842934Sktlim@umich.edu self.tsunami = BaseTsunami() 852934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 868839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.iobus.master 878839Sandreas.hansson@arm.com self.tsunami.ide.config = self.iobus.master 888839Sandreas.hansson@arm.com self.tsunami.ide.dma = self.iobus.slave 898839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.iobus.master 908839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.iobus.master 918839Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.iobus.slave 922995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 932934Sktlim@umich.edu read_only = True)) 942934Sktlim@umich.edu self.intrctrl = IntrControl() 952953Sktlim@umich.edu self.mem_mode = mem_mode 965478Snate@binkert.org self.terminal = Terminal() 972934Sktlim@umich.edu self.kernel = binary('vmlinux') 983449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 992934Sktlim@umich.edu self.console = binary('console') 1002934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1012934Sktlim@umich.edu 1028839Sandreas.hansson@arm.com self.system_port = self.membus.slave 1038706Sandreas.hansson@arm.com 1042934Sktlim@umich.edu return self 1052934Sktlim@umich.edu 1067014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1076765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1086765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1096765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1106765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1116765SBrad.Beckmann@amd.com 1127014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1137014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1146765SBrad.Beckmann@amd.com if not mdesc: 1156765SBrad.Beckmann@amd.com # generic system 1166765SBrad.Beckmann@amd.com mdesc = SysConfig() 1176765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1186765SBrad.Beckmann@amd.com 1196765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1206765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1216893SBrad.Beckmann@amd.com 1226893SBrad.Beckmann@amd.com # 1236893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1246893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1256893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1266893SBrad.Beckmann@amd.com # 1278898Snilay@cs.wisc.edu self.piobus.master = physmem.port 1286893SBrad.Beckmann@amd.com 1296765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1306765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1316765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1326765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1336765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1346765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1358839Sandreas.hansson@arm.com self.tsunami.ide.pio = self.piobus.master 1368839Sandreas.hansson@arm.com self.tsunami.ide.config = self.piobus.master 1378839Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.piobus.master 1388839Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.piobus.master 1396765SBrad.Beckmann@amd.com 1406893SBrad.Beckmann@amd.com # 1417633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1427633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1436893SBrad.Beckmann@amd.com # 1448929Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1456765SBrad.Beckmann@amd.com 1466765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1476765SBrad.Beckmann@amd.com read_only = True)) 1486765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1496765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1506765SBrad.Beckmann@amd.com self.terminal = Terminal() 1516765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1526765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1536765SBrad.Beckmann@amd.com self.console = binary('console') 1546765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1556765SBrad.Beckmann@amd.com 1566765SBrad.Beckmann@amd.com return self 1576765SBrad.Beckmann@amd.com 1583584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1598713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1608713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1618713Sandreas.hansson@arm.com uart_pio_size = 8 1628713Sandreas.hansson@arm.com 1634486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1644486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1654486Sbinkertn@umich.edu read_only=False) 1664486Sbinkertn@umich.edu 1674486Sbinkertn@umich.edu def childImage(self, ci): 1684486Sbinkertn@umich.edu self.image.child.image_file = ci 1694486Sbinkertn@umich.edu 1703584Ssaidi@eecs.umich.edu self = SparcSystem() 1713584Ssaidi@eecs.umich.edu if not mdesc: 1723584Ssaidi@eecs.umich.edu # generic system 1733584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1743584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1753743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1766122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1774972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1783743Sgblack@eecs.umich.edu self.t1000 = T1000() 1794104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1803743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1813823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1823814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1838839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1848839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1858839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 1868839Sandreas.hansson@arm.com self.physmem2.port = self.membus.master 1878839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1888839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1898839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1908839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1913584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1923898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1933898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1948839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1958713Sandreas.hansson@arm.com 1968713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1978713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1988713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1998713Sandreas.hansson@arm.com self.bridge.ranges = \ 2008713Sandreas.hansson@arm.com [ 2018713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 2028713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 2038713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 2048713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 2058713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 2068713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 2078713Sandreas.hansson@arm.com iob_man_addr - 1), 2088713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 2098713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 2108713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 2118713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 2128713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2138713Sandreas.hansson@arm.com ] 2144103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 2154103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 2164103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 2173745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2183745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2193745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2203584Ssaidi@eecs.umich.edu 2218839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2228706Sandreas.hansson@arm.com 2233584Ssaidi@eecs.umich.edu return self 2243584Ssaidi@eecs.umich.edu 2258061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 2268061SAli.Saidi@ARM.com assert machine_type 2278061SAli.Saidi@ARM.com 2287586SAli.Saidi@arm.com if bare_metal: 2297586SAli.Saidi@arm.com self = ArmSystem() 2307586SAli.Saidi@arm.com else: 2317586SAli.Saidi@arm.com self = LinuxArmSystem() 2327586SAli.Saidi@arm.com 2337586SAli.Saidi@arm.com if not mdesc: 2347586SAli.Saidi@arm.com # generic system 2357586SAli.Saidi@arm.com mdesc = SysConfig() 2367586SAli.Saidi@arm.com 2377586SAli.Saidi@arm.com self.readfile = mdesc.script() 2387586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 2397586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2407586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2417586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2428839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2438839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2447586SAli.Saidi@arm.com 2457586SAli.Saidi@arm.com self.mem_mode = mem_mode 2467586SAli.Saidi@arm.com 2477586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2487586SAli.Saidi@arm.com self.realview = RealViewPBX() 2497586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2507586SAli.Saidi@arm.com self.realview = RealViewEB() 2518525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2528525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2538870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2548870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 2558870SAli.Saidi@ARM.com self.load_addr_mask = 0xffffffff 2567586SAli.Saidi@arm.com else: 2577586SAli.Saidi@arm.com print "Unknown Machine Type" 2587586SAli.Saidi@arm.com sys.exit(1) 2597586SAli.Saidi@arm.com 2608528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2618528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2628528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 2638528SAli.Saidi@ARM.com # assuming we've got one 2648528SAli.Saidi@ARM.com try: 2658528SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 2668528SAli.Saidi@ARM.com except: 2678528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2688528SAli.Saidi@ARM.com 2698061SAli.Saidi@ARM.com if bare_metal: 2708061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2718061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2728528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2738212SAli.Saidi@ARM.com zero = True) 2748061SAli.Saidi@ARM.com else: 2758528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2767586SAli.Saidi@arm.com self.machine_type = machine_type 2778894Ssaidi@eecs.umich.edu if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2788870SAli.Saidi@ARM.com print "The currently selected ARM platforms doesn't support" 2798870SAli.Saidi@ARM.com print " the amount of DRAM you've selected. Please try" 2808870SAli.Saidi@ARM.com print " another platform" 2818894Ssaidi@eecs.umich.edu sys.exit(1) 2828528SAli.Saidi@ARM.com 2838212SAli.Saidi@ARM.com boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2848528SAli.Saidi@ARM.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2858528SAli.Saidi@ARM.com 2868870SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr, 2878870SAli.Saidi@ARM.com size = mdesc.mem())) 2888870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2898528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2908528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2918287SAli.Saidi@ARM.com 2928643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2938595SAli.Saidi@ARM.com boot_flags += " init=/init " 2948212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2957586SAli.Saidi@arm.com 2968839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 2978713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 2987586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2997586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3007586SAli.Saidi@arm.com self.terminal = Terminal() 3017949SAli.Saidi@ARM.com self.vncserver = VncServer() 3027586SAli.Saidi@arm.com 3038839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3048706Sandreas.hansson@arm.com 3057586SAli.Saidi@arm.com return self 3067586SAli.Saidi@arm.com 3077586SAli.Saidi@arm.com 3085222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 3095222Sksewell@umich.edu class BaseMalta(Malta): 3105222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3115222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3125222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3135222Sksewell@umich.edu 3145222Sksewell@umich.edu self = LinuxMipsSystem() 3155222Sksewell@umich.edu if not mdesc: 3165222Sksewell@umich.edu # generic system 3175222Sksewell@umich.edu mdesc = SysConfig() 3185222Sksewell@umich.edu self.readfile = mdesc.script() 3195222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 3206122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 3215222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 3225222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 3238839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3248839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3258839Sandreas.hansson@arm.com self.physmem.port = self.membus.master 3265222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3275222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3285222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3295222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3305222Sksewell@umich.edu self.malta = BaseMalta() 3315222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3328839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3338839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3348839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3358839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3368839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3378839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3385222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3395222Sksewell@umich.edu read_only = True)) 3405222Sksewell@umich.edu self.intrctrl = IntrControl() 3415222Sksewell@umich.edu self.mem_mode = mem_mode 3425478Snate@binkert.org self.terminal = Terminal() 3435222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3445222Sksewell@umich.edu self.console = binary('mips/console') 3455222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3465222Sksewell@umich.edu 3478839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3488706Sandreas.hansson@arm.com 3495222Sksewell@umich.edu return self 3505222Sksewell@umich.edu 3515323Sgblack@eecs.umich.edudef x86IOAddress(port): 3525357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3538323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3545323Sgblack@eecs.umich.edu 3558858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3568713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3578713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3588713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3598713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3608713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3618713Sandreas.hansson@arm.com 3627905SBrad.Beckmann@amd.com x86_sys.membus = MemBus(bus_id=1) 3638839Sandreas.hansson@arm.com x86_sys.physmem.port = x86_sys.membus.master 3647905SBrad.Beckmann@amd.com 3657905SBrad.Beckmann@amd.com # North Bridge 3667905SBrad.Beckmann@amd.com x86_sys.iobus = Bus(bus_id=0) 3677905SBrad.Beckmann@amd.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 3688839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3698839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 3708713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3718713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3728713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3738713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3748713Sandreas.hansson@arm.com [ 3758713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3768713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3778713Sandreas.hansson@arm.com APIC_range_size - 1), 3788713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3798713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3808713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3818713Sandreas.hansson@arm.com Addr.max) 3828713Sandreas.hansson@arm.com ] 3838713Sandreas.hansson@arm.com 3848713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3858713Sandreas.hansson@arm.com # the local APIC (two pages) 3868815Sgblack@eecs.umich.edu x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns') 3878839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 3888839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 3898815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3908815Sgblack@eecs.umich.edu interrupts_address_space_base + 3918858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 3928858Sgblack@eecs.umich.edu - 1)] 3937905SBrad.Beckmann@amd.com 3947905SBrad.Beckmann@amd.com # connect the io bus 3957905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3967905SBrad.Beckmann@amd.com 3978839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 3988706Sandreas.hansson@arm.com 3997905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4007905SBrad.Beckmann@amd.com # North Bridge 4017905SBrad.Beckmann@amd.com x86_sys.piobus = Bus(bus_id=0) 4027905SBrad.Beckmann@amd.com 4037905SBrad.Beckmann@amd.com # 4047905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 4057905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 4067905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 4077905SBrad.Beckmann@amd.com # 4088839Sandreas.hansson@arm.com x86_sys.piobus.master = x86_sys.physmem.port 4098929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4108929Snilay@cs.wisc.edu # dma controllers 4118929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 4128929Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 4137905SBrad.Beckmann@amd.com 4147905SBrad.Beckmann@amd.com 4157905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 4165613Sgblack@eecs.umich.edu if self == None: 4175613Sgblack@eecs.umich.edu self = X86System() 4185613Sgblack@eecs.umich.edu 4195133Sgblack@eecs.umich.edu if not mdesc: 4205133Sgblack@eecs.umich.edu # generic system 4215133Sgblack@eecs.umich.edu mdesc = SysConfig() 4225133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4235133Sgblack@eecs.umich.edu 4246802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4256802Sgblack@eecs.umich.edu 4265133Sgblack@eecs.umich.edu # Physical memory 4275450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 4285613Sgblack@eecs.umich.edu 4295613Sgblack@eecs.umich.edu # Platform 4305638Sgblack@eecs.umich.edu self.pc = Pc() 4317905SBrad.Beckmann@amd.com 4327905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4337905SBrad.Beckmann@amd.com if Ruby: 4347905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4357905SBrad.Beckmann@amd.com else: 4368858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4375613Sgblack@eecs.umich.edu 4385613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4395613Sgblack@eecs.umich.edu 4405841Sgblack@eecs.umich.edu # Disks 4415841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4425841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4435841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4445841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4455841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4465841Sgblack@eecs.umich.edu 4475615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4485615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4495615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4505615Sgblack@eecs.umich.edu 4515641Sgblack@eecs.umich.edu # Set up the Intel MP table 4528323Ssteve.reinhardt@amd.com base_entries = [] 4538323Ssteve.reinhardt@amd.com ext_entries = [] 4546135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4556135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4566135Sgblack@eecs.umich.edu local_apic_id = i, 4576135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4586135Sgblack@eecs.umich.edu enable = True, 4596135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4608323Ssteve.reinhardt@amd.com base_entries.append(bp) 4615644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4626135Sgblack@eecs.umich.edu id = numCPUs, 4635644Sgblack@eecs.umich.edu version = 0x11, 4645644Sgblack@eecs.umich.edu enable = True, 4655644Sgblack@eecs.umich.edu address = 0xfec00000) 4666135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4678323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4685644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4698323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4705843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4718323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4725843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4735843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4748323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4755843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4765843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4775843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4785843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4795843Sgblack@eecs.umich.edu source_bus_id = 1, 4805843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4816044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4825843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4838323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4846135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4856135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4866135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4876135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4886135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4896135Sgblack@eecs.umich.edu source_bus_id = 0, 4906135Sgblack@eecs.umich.edu source_bus_irq = irq, 4916135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4926135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4938323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4946135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4956135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4966135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4976135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4986135Sgblack@eecs.umich.edu source_bus_id = 0, 4996135Sgblack@eecs.umich.edu source_bus_irq = irq, 5006135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5016135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5028323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5036135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5046135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5056135Sgblack@eecs.umich.edu for i in range(3, 15): 5066135Sgblack@eecs.umich.edu assignISAInt(i, i) 5078323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5088323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5095641Sgblack@eecs.umich.edu 5107925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 5115613Sgblack@eecs.umich.edu self = LinuxX86System() 5125613Sgblack@eecs.umich.edu 5137905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5147905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5155613Sgblack@eecs.umich.edu 5165450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5175450Sgblack@eecs.umich.edu # just to avoid corner cases. 5187069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 5195450Sgblack@eecs.umich.edu 5208323Ssteve.reinhardt@amd.com self.e820_table.entries = \ 5218323Ssteve.reinhardt@amd.com [ 5228323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5238323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 5248323Ssteve.reinhardt@amd.com # Mark the rest as available 5258323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 5266072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 5278323Ssteve.reinhardt@amd.com range_type = 1) 5288323Ssteve.reinhardt@amd.com ] 5295450Sgblack@eecs.umich.edu 5305330Sgblack@eecs.umich.edu # Command line 5315847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5325845Sgblack@eecs.umich.edu 'root=/dev/hda1' 5335133Sgblack@eecs.umich.edu return self 5345133Sgblack@eecs.umich.edu 5353584Ssaidi@eecs.umich.edu 5368801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5378801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 5382995Ssaidi@eecs.umich.edu self.testsys = testSystem 5392995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5404981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5414981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5424981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5434981Ssaidi@eecs.umich.edu 5448661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5458661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5468661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5478661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5488661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5498661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5508661SAli.Saidi@ARM.com else: 5518661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5528661SAli.Saidi@ARM.com 5533025Ssaidi@eecs.umich.edu if dumpfile: 5543025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5553025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5562934Sktlim@umich.edu 5572934Sktlim@umich.edu return self 5585253Sksewell@umich.edu 5595263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 5605253Sksewell@umich.edu #CP0 Configuration 5615253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 5625253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 5635253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 5645253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 5655253Sksewell@umich.edu 5665253Sksewell@umich.edu #CP0 Interrupt Control 5675253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 5685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 5695253Sksewell@umich.edu 5705253Sksewell@umich.edu # Config Register 5715253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 5725253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 5735253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 5745253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 5755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 5765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 5775253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 5785253Sksewell@umich.edu 5795253Sksewell@umich.edu #Config 1 Register 5805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 5815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 5825253Sksewell@umich.edu # ***VERY IMPORTANT*** 5835253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 5845253Sksewell@umich.edu # Examine file ../common/Cache.py 5855253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 5865253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 5875253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 5885253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 5895253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 5905253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 5915253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 5925253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 5935253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 5945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 5955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 5965253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 5975253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 5985253Sksewell@umich.edu 5995253Sksewell@umich.edu #Config 2 Register 6005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 6015253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 6025253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 6035253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 6045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 6055253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 6065253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 6075253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 6085253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 6095253Sksewell@umich.edu 6105253Sksewell@umich.edu 6115253Sksewell@umich.edu #Config 3 Register 6125253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 6135253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 6145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 6155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 6165253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 6175253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 6185253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 6195253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 6205253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 6215253Sksewell@umich.edu 6225253Sksewell@umich.edu #SRS Ctl - HSS 6235253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 6245253Sksewell@umich.edu 6255253Sksewell@umich.edu 6265253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 6275253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 628