FSConfig.py revision 8929
110037SARM gem5 Developers# Copyright (c) 2010-2012 ARM Limited 210037SARM gem5 Developers# All rights reserved. 314127Sgiacomo.travaglini@arm.com# 410037SARM gem5 Developers# The license below extends only to copyright in the software and shall 510037SARM gem5 Developers# not be construed as granting a license to any other intellectual 610037SARM gem5 Developers# property including but not limited to intellectual property relating 710037SARM gem5 Developers# to a hardware implementation of the functionality of the software 810037SARM gem5 Developers# licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers# terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers# unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers# modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers# 1310037SARM gem5 Developers# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 1410037SARM gem5 Developers# Copyright (c) 2006-2008 The Regents of The University of Michigan 1510037SARM gem5 Developers# All rights reserved. 1610037SARM gem5 Developers# 1710037SARM gem5 Developers# Redistribution and use in source and binary forms, with or without 1810037SARM gem5 Developers# modification, are permitted provided that the following conditions are 1910037SARM gem5 Developers# met: redistributions of source code must retain the above copyright 2010037SARM gem5 Developers# notice, this list of conditions and the following disclaimer; 2110037SARM gem5 Developers# redistributions in binary form must reproduce the above copyright 2210037SARM gem5 Developers# notice, this list of conditions and the following disclaimer in the 2310037SARM gem5 Developers# documentation and/or other materials provided with the distribution; 2410037SARM gem5 Developers# neither the name of the copyright holders nor the names of its 2510037SARM gem5 Developers# contributors may be used to endorse or promote products derived from 2610037SARM gem5 Developers# this software without specific prior written permission. 2710037SARM gem5 Developers# 2810037SARM gem5 Developers# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910037SARM gem5 Developers# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010037SARM gem5 Developers# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110037SARM gem5 Developers# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210037SARM gem5 Developers# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310037SARM gem5 Developers# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410037SARM gem5 Developers# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510037SARM gem5 Developers# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610037SARM gem5 Developers# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710037SARM gem5 Developers# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810037SARM gem5 Developers# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910037SARM gem5 Developers# 4010037SARM gem5 Developers# Authors: Kevin Lim 4110037SARM gem5 Developers 4210037SARM gem5 Developersfrom m5.objects import * 4310037SARM gem5 Developersfrom Benchmarks import * 4410037SARM gem5 Developersfrom m5.util import convert 4510037SARM gem5 Developers 4610037SARM gem5 Developersclass CowIdeDisk(IdeDisk): 4710037SARM gem5 Developers image = CowDiskImage(child=RawDiskImage(read_only=True), 4810037SARM gem5 Developers read_only=False) 4910037SARM gem5 Developers 5010037SARM gem5 Developers def childImage(self, ci): 5110037SARM gem5 Developers self.image.child.image_file = ci 5210037SARM gem5 Developers 5311862Snikos.nikoleris@arm.comclass MemBus(Bus): 5410037SARM gem5 Developers badaddr_responder = BadAddr() 5510037SARM gem5 Developers default = Self.badaddr_responder.pio 5610037SARM gem5 Developers 5710037SARM gem5 Developers 5810037SARM gem5 Developersdef makeLinuxAlphaSystem(mem_mode, mdesc = None): 5910037SARM gem5 Developers IO_address_space_base = 0x80000000000 6010037SARM gem5 Developers class BaseTsunami(Tsunami): 6110037SARM gem5 Developers ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 6210037SARM gem5 Developers ide = IdeController(disks=[Parent.disk0, Parent.disk2], 6310037SARM gem5 Developers pci_func=0, pci_dev=0, pci_bus=0) 6410037SARM gem5 Developers 6510037SARM gem5 Developers self = LinuxAlphaSystem() 6610037SARM gem5 Developers if not mdesc: 6710037SARM gem5 Developers # generic system 6810037SARM gem5 Developers mdesc = SysConfig() 6910037SARM gem5 Developers self.readfile = mdesc.script() 7010037SARM gem5 Developers self.iobus = Bus(bus_id=0) 7110037SARM gem5 Developers self.membus = MemBus(bus_id=1) 7210037SARM gem5 Developers # By default the bridge responds to all addresses above the I/O 7310037SARM gem5 Developers # base address (including the PCI config space) 7410037SARM gem5 Developers self.bridge = Bridge(delay='50ns', nack_delay='4ns', 7510037SARM gem5 Developers ranges = [AddrRange(IO_address_space_base, Addr.max)]) 7610037SARM gem5 Developers self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 7710037SARM gem5 Developers self.bridge.master = self.iobus.slave 7810037SARM gem5 Developers self.bridge.slave = self.membus.master 7910037SARM gem5 Developers self.physmem.port = self.membus.master 8010037SARM gem5 Developers self.disk0 = CowIdeDisk(driveID='master') 8110037SARM gem5 Developers self.disk2 = CowIdeDisk(driveID='master') 8210037SARM gem5 Developers self.disk0.childImage(mdesc.disk()) 8310037SARM gem5 Developers self.disk2.childImage(disk('linux-bigswap2.img')) 8410037SARM gem5 Developers self.tsunami = BaseTsunami() 8510037SARM gem5 Developers self.tsunami.attachIO(self.iobus) 8610037SARM gem5 Developers self.tsunami.ide.pio = self.iobus.master 8710037SARM gem5 Developers self.tsunami.ide.config = self.iobus.master 8810037SARM gem5 Developers self.tsunami.ide.dma = self.iobus.slave 8910037SARM gem5 Developers self.tsunami.ethernet.pio = self.iobus.master 9010037SARM gem5 Developers self.tsunami.ethernet.config = self.iobus.master 9110037SARM gem5 Developers self.tsunami.ethernet.dma = self.iobus.slave 9210037SARM gem5 Developers self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 9310037SARM gem5 Developers read_only = True)) 9410037SARM gem5 Developers self.intrctrl = IntrControl() 9510037SARM gem5 Developers self.mem_mode = mem_mode 9610037SARM gem5 Developers self.terminal = Terminal() 9710037SARM gem5 Developers self.kernel = binary('vmlinux') 9810037SARM gem5 Developers self.pal = binary('ts_osfpal') 9910037SARM gem5 Developers self.console = binary('console') 10010037SARM gem5 Developers self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 10110037SARM gem5 Developers 10210037SARM gem5 Developers self.system_port = self.membus.slave 10310037SARM gem5 Developers 10410037SARM gem5 Developers return self 10510037SARM gem5 Developers 10610037SARM gem5 Developersdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 10710037SARM gem5 Developers class BaseTsunami(Tsunami): 10810037SARM gem5 Developers ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 10910037SARM gem5 Developers ide = IdeController(disks=[Parent.disk0, Parent.disk2], 11010037SARM gem5 Developers pci_func=0, pci_dev=0, pci_bus=0) 11110037SARM gem5 Developers 11210037SARM gem5 Developers physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 11310037SARM gem5 Developers self = LinuxAlphaSystem(physmem = physmem) 11410037SARM gem5 Developers if not mdesc: 11510037SARM gem5 Developers # generic system 11610037SARM gem5 Developers mdesc = SysConfig() 11710037SARM gem5 Developers self.readfile = mdesc.script() 11810037SARM gem5 Developers 11910037SARM gem5 Developers # Create pio bus to connect all device pio ports to rubymem's pio port 12010037SARM gem5 Developers self.piobus = Bus(bus_id=0) 12110037SARM gem5 Developers 12210037SARM gem5 Developers # 12310037SARM gem5 Developers # Pio functional accesses from devices need direct access to memory 12410037SARM gem5 Developers # RubyPort currently does support functional accesses. Therefore provide 12510037SARM gem5 Developers # the piobus a direct connection to physical memory 12610037SARM gem5 Developers # 12710037SARM gem5 Developers self.piobus.master = physmem.port 12810037SARM gem5 Developers 12910037SARM gem5 Developers self.disk0 = CowIdeDisk(driveID='master') 13010037SARM gem5 Developers self.disk2 = CowIdeDisk(driveID='master') 13110037SARM gem5 Developers self.disk0.childImage(mdesc.disk()) 13210037SARM gem5 Developers self.disk2.childImage(disk('linux-bigswap2.img')) 13310037SARM gem5 Developers self.tsunami = BaseTsunami() 13410037SARM gem5 Developers self.tsunami.attachIO(self.piobus) 13510037SARM gem5 Developers self.tsunami.ide.pio = self.piobus.master 13610037SARM gem5 Developers self.tsunami.ide.config = self.piobus.master 13710037SARM gem5 Developers self.tsunami.ethernet.pio = self.piobus.master 13810037SARM gem5 Developers self.tsunami.ethernet.config = self.piobus.master 13910037SARM gem5 Developers 14010037SARM gem5 Developers # 14110037SARM gem5 Developers # Store the dma devices for later connection to dma ruby ports. 14210037SARM gem5 Developers # Append an underscore to dma_devices to avoid the SimObjectVector check. 14310037SARM gem5 Developers # 14410037SARM gem5 Developers self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 14510037SARM gem5 Developers 14610037SARM gem5 Developers self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 14710037SARM gem5 Developers read_only = True)) 14810037SARM gem5 Developers self.intrctrl = IntrControl() 14910037SARM gem5 Developers self.mem_mode = mem_mode 15010037SARM gem5 Developers self.terminal = Terminal() 15110037SARM gem5 Developers self.kernel = binary('vmlinux') 15210037SARM gem5 Developers self.pal = binary('ts_osfpal') 15310037SARM gem5 Developers self.console = binary('console') 15410037SARM gem5 Developers self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 15510037SARM gem5 Developers 15610037SARM gem5 Developers return self 15710037SARM gem5 Developers 15810037SARM gem5 Developersdef makeSparcSystem(mem_mode, mdesc = None): 15910037SARM gem5 Developers # Constants from iob.cc and uart8250.cc 16010037SARM gem5 Developers iob_man_addr = 0x9800000000 16110037SARM gem5 Developers uart_pio_size = 8 16210037SARM gem5 Developers 16310037SARM gem5 Developers class CowMmDisk(MmDisk): 16410037SARM gem5 Developers image = CowDiskImage(child=RawDiskImage(read_only=True), 16510037SARM gem5 Developers read_only=False) 16610037SARM gem5 Developers 16710037SARM gem5 Developers def childImage(self, ci): 16810037SARM gem5 Developers self.image.child.image_file = ci 16910037SARM gem5 Developers 17010037SARM gem5 Developers self = SparcSystem() 17110037SARM gem5 Developers if not mdesc: 17210037SARM gem5 Developers # generic system 17310037SARM gem5 Developers mdesc = SysConfig() 17410037SARM gem5 Developers self.readfile = mdesc.script() 17510037SARM gem5 Developers self.iobus = Bus(bus_id=0) 17610037SARM gem5 Developers self.membus = MemBus(bus_id=1) 17710037SARM gem5 Developers self.bridge = Bridge(delay='50ns', nack_delay='4ns') 17810037SARM gem5 Developers self.t1000 = T1000() 17910037SARM gem5 Developers self.t1000.attachOnChipIO(self.membus) 18010037SARM gem5 Developers self.t1000.attachIO(self.iobus) 18110037SARM gem5 Developers self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 18210037SARM gem5 Developers self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 18310037SARM gem5 Developers self.bridge.master = self.iobus.slave 18410037SARM gem5 Developers self.bridge.slave = self.membus.master 18510037SARM gem5 Developers self.physmem.port = self.membus.master 18610037SARM gem5 Developers self.physmem2.port = self.membus.master 18710037SARM gem5 Developers self.rom.port = self.membus.master 18810037SARM gem5 Developers self.nvram.port = self.membus.master 18910037SARM gem5 Developers self.hypervisor_desc.port = self.membus.master 19010037SARM gem5 Developers self.partition_desc.port = self.membus.master 19110037SARM gem5 Developers self.intrctrl = IntrControl() 19210037SARM gem5 Developers self.disk0 = CowMmDisk() 19310037SARM gem5 Developers self.disk0.childImage(disk('disk.s10hw2')) 19410037SARM gem5 Developers self.disk0.pio = self.iobus.master 19510037SARM gem5 Developers 19610037SARM gem5 Developers # The puart0 and hvuart are placed on the IO bus, so create ranges 19710037SARM gem5 Developers # for them. The remaining IO range is rather fragmented, so poke 19810037SARM gem5 Developers # holes for the iob and partition descriptors etc. 19910037SARM gem5 Developers self.bridge.ranges = \ 20010037SARM gem5 Developers [ 20110037SARM gem5 Developers AddrRange(self.t1000.puart0.pio_addr, 20210037SARM gem5 Developers self.t1000.puart0.pio_addr + uart_pio_size - 1), 20310037SARM gem5 Developers AddrRange(self.disk0.pio_addr, 20410037SARM gem5 Developers self.t1000.fake_jbi.pio_addr + 20510037SARM gem5 Developers self.t1000.fake_jbi.pio_size - 1), 20610037SARM gem5 Developers AddrRange(self.t1000.fake_clk.pio_addr, 20710037SARM gem5 Developers iob_man_addr - 1), 20810037SARM gem5 Developers AddrRange(self.t1000.fake_l2_1.pio_addr, 20910037SARM gem5 Developers self.t1000.fake_ssi.pio_addr + 21010037SARM gem5 Developers self.t1000.fake_ssi.pio_size - 1), 21110037SARM gem5 Developers AddrRange(self.t1000.hvuart.pio_addr, 21210037SARM gem5 Developers self.t1000.hvuart.pio_addr + uart_pio_size - 1) 21310037SARM gem5 Developers ] 21410037SARM gem5 Developers self.reset_bin = binary('reset_new.bin') 21510037SARM gem5 Developers self.hypervisor_bin = binary('q_new.bin') 21610037SARM gem5 Developers self.openboot_bin = binary('openboot_new.bin') 21710037SARM gem5 Developers self.nvram_bin = binary('nvram1') 21810037SARM gem5 Developers self.hypervisor_desc_bin = binary('1up-hv.bin') 21910037SARM gem5 Developers self.partition_desc_bin = binary('1up-md.bin') 22010037SARM gem5 Developers 22110037SARM gem5 Developers self.system_port = self.membus.slave 22210037SARM gem5 Developers 22310037SARM gem5 Developers return self 22410037SARM gem5 Developers 22510037SARM gem5 Developersdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 22610037SARM gem5 Developers assert machine_type 22710037SARM gem5 Developers 22810037SARM gem5 Developers if bare_metal: 22912258Sgiacomo.travaglini@arm.com self = ArmSystem() 23012258Sgiacomo.travaglini@arm.com else: 23112258Sgiacomo.travaglini@arm.com self = LinuxArmSystem() 23212258Sgiacomo.travaglini@arm.com 23312258Sgiacomo.travaglini@arm.com if not mdesc: 23412258Sgiacomo.travaglini@arm.com # generic system 23512258Sgiacomo.travaglini@arm.com mdesc = SysConfig() 23612258Sgiacomo.travaglini@arm.com 23712258Sgiacomo.travaglini@arm.com self.readfile = mdesc.script() 23812258Sgiacomo.travaglini@arm.com self.iobus = Bus(bus_id=0) 23912258Sgiacomo.travaglini@arm.com self.membus = MemBus(bus_id=1) 24012258Sgiacomo.travaglini@arm.com self.membus.badaddr_responder.warn_access = "warn" 24112258Sgiacomo.travaglini@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 24212258Sgiacomo.travaglini@arm.com self.bridge.master = self.iobus.slave 24312258Sgiacomo.travaglini@arm.com self.bridge.slave = self.membus.master 24412258Sgiacomo.travaglini@arm.com 24512258Sgiacomo.travaglini@arm.com self.mem_mode = mem_mode 24612258Sgiacomo.travaglini@arm.com 24712258Sgiacomo.travaglini@arm.com if machine_type == "RealView_PBX": 24812258Sgiacomo.travaglini@arm.com self.realview = RealViewPBX() 24912258Sgiacomo.travaglini@arm.com elif machine_type == "RealView_EB": 25012258Sgiacomo.travaglini@arm.com self.realview = RealViewEB() 25112258Sgiacomo.travaglini@arm.com elif machine_type == "VExpress_ELT": 25212258Sgiacomo.travaglini@arm.com self.realview = VExpress_ELT() 25312258Sgiacomo.travaglini@arm.com elif machine_type == "VExpress_EMM": 25412258Sgiacomo.travaglini@arm.com self.realview = VExpress_EMM() 25512258Sgiacomo.travaglini@arm.com self.load_addr_mask = 0xffffffff 25612258Sgiacomo.travaglini@arm.com else: 25712258Sgiacomo.travaglini@arm.com print "Unknown Machine Type" 25812258Sgiacomo.travaglini@arm.com sys.exit(1) 25912258Sgiacomo.travaglini@arm.com 26012258Sgiacomo.travaglini@arm.com self.cf0 = CowIdeDisk(driveID='master') 26112258Sgiacomo.travaglini@arm.com self.cf0.childImage(mdesc.disk()) 26212258Sgiacomo.travaglini@arm.com # default to an IDE controller rather than a CF one 26312258Sgiacomo.travaglini@arm.com # assuming we've got one 26412258Sgiacomo.travaglini@arm.com try: 26510037SARM gem5 Developers self.realview.ide.disks = [self.cf0] 26610037SARM gem5 Developers except: 26710037SARM gem5 Developers self.realview.cf_ctrl.disks = [self.cf0] 26810037SARM gem5 Developers 26910037SARM gem5 Developers if bare_metal: 27010037SARM gem5 Developers # EOT character on UART will end the simulation 27110037SARM gem5 Developers self.realview.uart.end_on_eot = True 27210037SARM gem5 Developers self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 27310037SARM gem5 Developers zero = True) 27410037SARM gem5 Developers else: 27510037SARM gem5 Developers self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 27610037SARM gem5 Developers self.machine_type = machine_type 27710037SARM gem5 Developers if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 27810037SARM gem5 Developers print "The currently selected ARM platforms doesn't support" 27910037SARM gem5 Developers print " the amount of DRAM you've selected. Please try" 28010037SARM gem5 Developers print " another platform" 28110037SARM gem5 Developers sys.exit(1) 28210037SARM gem5 Developers 28310037SARM gem5 Developers boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 28410037SARM gem5 Developers 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 28510037SARM gem5 Developers 28610037SARM gem5 Developers self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr, 28712227Sgiacomo.travaglini@arm.com size = mdesc.mem())) 28810037SARM gem5 Developers self.realview.setupBootLoader(self.membus, self, binary) 28910037SARM gem5 Developers self.gic_cpu_addr = self.realview.gic.cpu_addr 29010037SARM gem5 Developers self.flags_addr = self.realview.realview_io.pio_addr + 0x30 29110037SARM gem5 Developers 29210037SARM gem5 Developers if mdesc.disk().lower().count('android'): 29310037SARM gem5 Developers boot_flags += " init=/init " 29410037SARM gem5 Developers self.boot_osflags = boot_flags 29510037SARM gem5 Developers 29610037SARM gem5 Developers self.physmem.port = self.membus.master 29710037SARM gem5 Developers self.realview.attachOnChipIO(self.membus, self.bridge) 29810037SARM gem5 Developers self.realview.attachIO(self.iobus) 29910037SARM gem5 Developers self.intrctrl = IntrControl() 30010037SARM gem5 Developers self.terminal = Terminal() 30110037SARM gem5 Developers self.vncserver = VncServer() 30210037SARM gem5 Developers 30310037SARM gem5 Developers self.system_port = self.membus.slave 30410037SARM gem5 Developers 30510037SARM gem5 Developers return self 30610037SARM gem5 Developers 30710037SARM gem5 Developers 30810037SARM gem5 Developersdef makeLinuxMipsSystem(mem_mode, mdesc = None): 30910037SARM gem5 Developers class BaseMalta(Malta): 31010037SARM gem5 Developers ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 31110037SARM gem5 Developers ide = IdeController(disks=[Parent.disk0, Parent.disk2], 31210037SARM gem5 Developers pci_func=0, pci_dev=0, pci_bus=0) 31310037SARM gem5 Developers 31410037SARM gem5 Developers self = LinuxMipsSystem() 31510037SARM gem5 Developers if not mdesc: 31610037SARM gem5 Developers # generic system 31710037SARM gem5 Developers mdesc = SysConfig() 31810037SARM gem5 Developers self.readfile = mdesc.script() 31910037SARM gem5 Developers self.iobus = Bus(bus_id=0) 32012508Snikos.nikoleris@arm.com self.membus = MemBus(bus_id=1) 32110037SARM gem5 Developers self.bridge = Bridge(delay='50ns', nack_delay='4ns') 32210474Sandreas.hansson@arm.com self.physmem = PhysicalMemory(range = AddrRange('1GB')) 32310474Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 32410205SAli.Saidi@ARM.com self.bridge.slave = self.membus.master 32510474Sandreas.hansson@arm.com self.physmem.port = self.membus.master 32610474Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 32710037SARM gem5 Developers self.disk2 = CowIdeDisk(driveID='master') 32810037SARM gem5 Developers self.disk0.childImage(mdesc.disk()) 32913364Sgiacomo.travaglini@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 33013364Sgiacomo.travaglini@arm.com self.malta = BaseMalta() 33110037SARM gem5 Developers self.malta.attachIO(self.iobus) 33210037SARM gem5 Developers self.malta.ide.pio = self.iobus.master 33314241Sgiacomo.travaglini@arm.com self.malta.ide.config = self.iobus.master 33414241Sgiacomo.travaglini@arm.com self.malta.ide.dma = self.iobus.slave 33514241Sgiacomo.travaglini@arm.com self.malta.ethernet.pio = self.iobus.master 33614241Sgiacomo.travaglini@arm.com self.malta.ethernet.config = self.iobus.master 33714241Sgiacomo.travaglini@arm.com self.malta.ethernet.dma = self.iobus.slave 33814241Sgiacomo.travaglini@arm.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 33914241Sgiacomo.travaglini@arm.com read_only = True)) 34014241Sgiacomo.travaglini@arm.com self.intrctrl = IntrControl() 34114241Sgiacomo.travaglini@arm.com self.mem_mode = mem_mode 34210037SARM gem5 Developers self.terminal = Terminal() 34312106SRekai.GonzalezAlberquilla@arm.com self.kernel = binary('mips/vmlinux') 34410037SARM gem5 Developers self.console = binary('mips/console') 34510037SARM gem5 Developers self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 34610037SARM gem5 Developers 34713364Sgiacomo.travaglini@arm.com self.system_port = self.membus.slave 34812280Sgiacomo.travaglini@arm.com 34914241Sgiacomo.travaglini@arm.com return self 35014241Sgiacomo.travaglini@arm.com 35114241Sgiacomo.travaglini@arm.comdef x86IOAddress(port): 35214241Sgiacomo.travaglini@arm.com IO_address_space_base = 0x8000000000000000 35312280Sgiacomo.travaglini@arm.com return IO_address_space_base + port 35412280Sgiacomo.travaglini@arm.com 35512280Sgiacomo.travaglini@arm.comdef connectX86ClassicSystem(x86_sys, numCPUs): 35612280Sgiacomo.travaglini@arm.com # Constants similar to x86_traits.hh 35712280Sgiacomo.travaglini@arm.com IO_address_space_base = 0x8000000000000000 35812280Sgiacomo.travaglini@arm.com pci_config_address_space_base = 0xc000000000000000 35910037SARM gem5 Developers interrupts_address_space_base = 0xa000000000000000 36010037SARM gem5 Developers APIC_range_size = 1 << 12; 36110037SARM gem5 Developers 36210037SARM gem5 Developers x86_sys.membus = MemBus(bus_id=1) 36310037SARM gem5 Developers x86_sys.physmem.port = x86_sys.membus.master 36410037SARM gem5 Developers 36510037SARM gem5 Developers # North Bridge 36610037SARM gem5 Developers x86_sys.iobus = Bus(bus_id=0) 36710037SARM gem5 Developers x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 36814241Sgiacomo.travaglini@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 36910037SARM gem5 Developers x86_sys.bridge.slave = x86_sys.membus.master 37014241Sgiacomo.travaglini@arm.com # Allow the bridge to pass through the IO APIC (two pages), 37112280Sgiacomo.travaglini@arm.com # everything in the IO address range up to the local APIC, and 37212280Sgiacomo.travaglini@arm.com # then the entire PCI address space and beyond 37312280Sgiacomo.travaglini@arm.com x86_sys.bridge.ranges = \ 37412280Sgiacomo.travaglini@arm.com [ 37512280Sgiacomo.travaglini@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 37612280Sgiacomo.travaglini@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 37712280Sgiacomo.travaglini@arm.com APIC_range_size - 1), 37810037SARM gem5 Developers AddrRange(IO_address_space_base, 37910037SARM gem5 Developers interrupts_address_space_base - 1), 38010037SARM gem5 Developers AddrRange(pci_config_address_space_base, 38110037SARM gem5 Developers Addr.max) 38210037SARM gem5 Developers ] 38310037SARM gem5 Developers 38410037SARM gem5 Developers # Create a bridge from the IO bus to the memory bus to allow access to 38510037SARM gem5 Developers # the local APIC (two pages) 38612507Snikos.nikoleris@arm.com x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns') 38712507Snikos.nikoleris@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 38810037SARM gem5 Developers x86_sys.apicbridge.master = x86_sys.membus.slave 38912507Snikos.nikoleris@arm.com x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 39012507Snikos.nikoleris@arm.com interrupts_address_space_base + 39110037SARM gem5 Developers numCPUs * APIC_range_size 39210037SARM gem5 Developers - 1)] 39310037SARM gem5 Developers 39410037SARM gem5 Developers # connect the io bus 39510037SARM gem5 Developers x86_sys.pc.attachIO(x86_sys.iobus) 39610037SARM gem5 Developers 39710037SARM gem5 Developers x86_sys.system_port = x86_sys.membus.slave 39812504Snikos.nikoleris@arm.com 39912507Snikos.nikoleris@arm.comdef connectX86RubySystem(x86_sys): 40012507Snikos.nikoleris@arm.com # North Bridge 40112507Snikos.nikoleris@arm.com x86_sys.piobus = Bus(bus_id=0) 40212507Snikos.nikoleris@arm.com 40312507Snikos.nikoleris@arm.com # 40412507Snikos.nikoleris@arm.com # Pio functional accesses from devices need direct access to memory 40510037SARM gem5 Developers # RubyPort currently does support functional accesses. Therefore provide 40610037SARM gem5 Developers # the piobus a direct connection to physical memory 40710037SARM gem5 Developers # 40810037SARM gem5 Developers x86_sys.piobus.master = x86_sys.physmem.port 40910037SARM gem5 Developers # add the ide to the list of dma devices that later need to attach to 41010037SARM gem5 Developers # dma controllers 41110037SARM gem5 Developers x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 41212507Snikos.nikoleris@arm.com x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 41312359Snikos.nikoleris@arm.com 41412359Snikos.nikoleris@arm.com 41512359Snikos.nikoleris@arm.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 41612359Snikos.nikoleris@arm.com if self == None: 41712359Snikos.nikoleris@arm.com self = X86System() 41812359Snikos.nikoleris@arm.com 41912359Snikos.nikoleris@arm.com if not mdesc: 42012359Snikos.nikoleris@arm.com # generic system 42112359Snikos.nikoleris@arm.com mdesc = SysConfig() 42212359Snikos.nikoleris@arm.com self.readfile = mdesc.script() 42312507Snikos.nikoleris@arm.com 42412507Snikos.nikoleris@arm.com self.mem_mode = mem_mode 42512507Snikos.nikoleris@arm.com 42612507Snikos.nikoleris@arm.com # Physical memory 42712507Snikos.nikoleris@arm.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 42812359Snikos.nikoleris@arm.com 42912359Snikos.nikoleris@arm.com # Platform 43012359Snikos.nikoleris@arm.com self.pc = Pc() 43112359Snikos.nikoleris@arm.com 43212359Snikos.nikoleris@arm.com # Create and connect the busses required by each memory system 43312359Snikos.nikoleris@arm.com if Ruby: 43412359Snikos.nikoleris@arm.com connectX86RubySystem(self) 43512507Snikos.nikoleris@arm.com else: 43612359Snikos.nikoleris@arm.com connectX86ClassicSystem(self, numCPUs) 43712359Snikos.nikoleris@arm.com 43812359Snikos.nikoleris@arm.com self.intrctrl = IntrControl() 43912359Snikos.nikoleris@arm.com 44012359Snikos.nikoleris@arm.com # Disks 44112359Snikos.nikoleris@arm.com disk0 = CowIdeDisk(driveID='master') 44212359Snikos.nikoleris@arm.com disk2 = CowIdeDisk(driveID='master') 44312359Snikos.nikoleris@arm.com disk0.childImage(mdesc.disk()) 44412359Snikos.nikoleris@arm.com disk2.childImage(disk('linux-bigswap2.img')) 44512359Snikos.nikoleris@arm.com self.pc.south_bridge.ide.disks = [disk0, disk2] 44612507Snikos.nikoleris@arm.com 44712507Snikos.nikoleris@arm.com # Add in a Bios information structure. 44812507Snikos.nikoleris@arm.com structures = [X86SMBiosBiosInformation()] 44912507Snikos.nikoleris@arm.com self.smbios_table.structures = structures 45012507Snikos.nikoleris@arm.com 45112359Snikos.nikoleris@arm.com # Set up the Intel MP table 45212359Snikos.nikoleris@arm.com base_entries = [] 45312359Snikos.nikoleris@arm.com ext_entries = [] 45412359Snikos.nikoleris@arm.com for i in xrange(numCPUs): 45512359Snikos.nikoleris@arm.com bp = X86IntelMPProcessor( 45612359Snikos.nikoleris@arm.com local_apic_id = i, 45712359Snikos.nikoleris@arm.com local_apic_version = 0x14, 45812507Snikos.nikoleris@arm.com enable = True, 45912359Snikos.nikoleris@arm.com bootstrap = (i == 0)) 46012359Snikos.nikoleris@arm.com base_entries.append(bp) 46112359Snikos.nikoleris@arm.com io_apic = X86IntelMPIOAPIC( 46212359Snikos.nikoleris@arm.com id = numCPUs, 46312359Snikos.nikoleris@arm.com version = 0x11, 46412359Snikos.nikoleris@arm.com enable = True, 46512359Snikos.nikoleris@arm.com address = 0xfec00000) 46612359Snikos.nikoleris@arm.com self.pc.south_bridge.io_apic.apic_id = io_apic.id 46712359Snikos.nikoleris@arm.com base_entries.append(io_apic) 46812359Snikos.nikoleris@arm.com isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 46912507Snikos.nikoleris@arm.com base_entries.append(isa_bus) 47012507Snikos.nikoleris@arm.com pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 47112507Snikos.nikoleris@arm.com base_entries.append(pci_bus) 47212507Snikos.nikoleris@arm.com connect_busses = X86IntelMPBusHierarchy(bus_id=0, 47312507Snikos.nikoleris@arm.com subtractive_decode=True, parent_bus=1) 47412359Snikos.nikoleris@arm.com ext_entries.append(connect_busses) 47512359Snikos.nikoleris@arm.com pci_dev4_inta = X86IntelMPIOIntAssignment( 47612359Snikos.nikoleris@arm.com interrupt_type = 'INT', 47712359Snikos.nikoleris@arm.com polarity = 'ConformPolarity', 47812359Snikos.nikoleris@arm.com trigger = 'ConformTrigger', 47912359Snikos.nikoleris@arm.com source_bus_id = 1, 48012359Snikos.nikoleris@arm.com source_bus_irq = 0 + (4 << 2), 48112507Snikos.nikoleris@arm.com dest_io_apic_id = io_apic.id, 48212359Snikos.nikoleris@arm.com dest_io_apic_intin = 16) 48312359Snikos.nikoleris@arm.com base_entries.append(pci_dev4_inta) 48412359Snikos.nikoleris@arm.com def assignISAInt(irq, apicPin): 48512359Snikos.nikoleris@arm.com assign_8259_to_apic = X86IntelMPIOIntAssignment( 48612505Snikos.nikoleris@arm.com interrupt_type = 'ExtInt', 48712505Snikos.nikoleris@arm.com polarity = 'ConformPolarity', 48812505Snikos.nikoleris@arm.com trigger = 'ConformTrigger', 48912505Snikos.nikoleris@arm.com source_bus_id = 0, 49012505Snikos.nikoleris@arm.com source_bus_irq = irq, 49112505Snikos.nikoleris@arm.com dest_io_apic_id = io_apic.id, 49212359Snikos.nikoleris@arm.com dest_io_apic_intin = 0) 49312359Snikos.nikoleris@arm.com base_entries.append(assign_8259_to_apic) 49412359Snikos.nikoleris@arm.com assign_to_apic = X86IntelMPIOIntAssignment( 49512359Snikos.nikoleris@arm.com interrupt_type = 'INT', 49612359Snikos.nikoleris@arm.com polarity = 'ConformPolarity', 49712359Snikos.nikoleris@arm.com trigger = 'ConformTrigger', 49812507Snikos.nikoleris@arm.com source_bus_id = 0, 49912507Snikos.nikoleris@arm.com source_bus_irq = irq, 50012507Snikos.nikoleris@arm.com dest_io_apic_id = io_apic.id, 50112507Snikos.nikoleris@arm.com dest_io_apic_intin = apicPin) 50212507Snikos.nikoleris@arm.com base_entries.append(assign_to_apic) 50312359Snikos.nikoleris@arm.com assignISAInt(0, 2) 50412359Snikos.nikoleris@arm.com assignISAInt(1, 1) 50512359Snikos.nikoleris@arm.com for i in range(3, 15): 50612359Snikos.nikoleris@arm.com assignISAInt(i, i) 50712359Snikos.nikoleris@arm.com self.intel_mp_table.base_entries = base_entries 50812359Snikos.nikoleris@arm.com self.intel_mp_table.ext_entries = ext_entries 50914127Sgiacomo.travaglini@arm.com 51014127Sgiacomo.travaglini@arm.comdef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 51114127Sgiacomo.travaglini@arm.com self = LinuxX86System() 51214128Sgiacomo.travaglini@arm.com 51314128Sgiacomo.travaglini@arm.com # Build up the x86 system and then specialize it for Linux 51414128Sgiacomo.travaglini@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 51514128Sgiacomo.travaglini@arm.com 51614128Sgiacomo.travaglini@arm.com # We assume below that there's at least 1MB of memory. We'll require 2 51714128Sgiacomo.travaglini@arm.com # just to avoid corner cases. 51814128Sgiacomo.travaglini@arm.com assert(self.physmem.range.second.getValue() >= 0x200000) 51914128Sgiacomo.travaglini@arm.com 52014128Sgiacomo.travaglini@arm.com self.e820_table.entries = \ 52114128Sgiacomo.travaglini@arm.com [ 52214128Sgiacomo.travaglini@arm.com # Mark the first megabyte of memory as reserved 52314128Sgiacomo.travaglini@arm.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 52414128Sgiacomo.travaglini@arm.com # Mark the rest as available 52514128Sgiacomo.travaglini@arm.com X86E820Entry(addr = 0x100000, 52614128Sgiacomo.travaglini@arm.com size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 52714127Sgiacomo.travaglini@arm.com range_type = 1) 52810037SARM gem5 Developers ] 52914127Sgiacomo.travaglini@arm.com 53014127Sgiacomo.travaglini@arm.com # Command line 53114127Sgiacomo.travaglini@arm.com self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 53214127Sgiacomo.travaglini@arm.com 'root=/dev/hda1' 53314127Sgiacomo.travaglini@arm.com return self 53414127Sgiacomo.travaglini@arm.com 53514127Sgiacomo.travaglini@arm.com 53610037SARM gem5 Developersdef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 53714127Sgiacomo.travaglini@arm.com self = Root(full_system = full_system) 53814127Sgiacomo.travaglini@arm.com self.testsys = testSystem 53914127Sgiacomo.travaglini@arm.com self.drivesys = driveSystem 54014127Sgiacomo.travaglini@arm.com self.etherlink = EtherLink() 54114127Sgiacomo.travaglini@arm.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 54214127Sgiacomo.travaglini@arm.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 54314127Sgiacomo.travaglini@arm.com 54410037SARM gem5 Developers if hasattr(testSystem, 'realview'): 54510037SARM gem5 Developers self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 54610037SARM gem5 Developers self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 54714127Sgiacomo.travaglini@arm.com elif hasattr(testSystem, 'tsunami'): 54810037SARM gem5 Developers self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 54914127Sgiacomo.travaglini@arm.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 55010037SARM gem5 Developers else: 55110037SARM gem5 Developers fatal("Don't know how to connect these system together") 55210037SARM gem5 Developers 55314127Sgiacomo.travaglini@arm.com if dumpfile: 55410037SARM gem5 Developers self.etherdump = EtherDump(file=dumpfile) 55510037SARM gem5 Developers self.etherlink.dump = Parent.etherdump 55610037SARM gem5 Developers 55710037SARM gem5 Developers return self 55810037SARM gem5 Developers 55910037SARM gem5 Developersdef setMipsOptions(TestCPUClass): 56010037SARM gem5 Developers #CP0 Configuration 56110037SARM gem5 Developers TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 56210037SARM gem5 Developers TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 56310037SARM gem5 Developers TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 56410037SARM gem5 Developers TestCPUClass.CoreParams.CP0_PRId_Revision = 0 56510037SARM gem5 Developers 56610037SARM gem5 Developers #CP0 Interrupt Control 56710037SARM gem5 Developers TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 56810037SARM gem5 Developers TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 56910037SARM gem5 Developers 57010037SARM gem5 Developers # Config Register 57110037SARM gem5 Developers #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 57210037SARM gem5 Developers #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 57310037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 57410037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 57510037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 57610037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 57710037SARM gem5 Developers #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 57810037SARM gem5 Developers 57910037SARM gem5 Developers #Config 1 Register 58010037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 58110037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 58210037SARM gem5 Developers # ***VERY IMPORTANT*** 58310037SARM gem5 Developers # Remember to modify CP0_Config1 according to cache specs 58410037SARM gem5 Developers # Examine file ../common/Cache.py 58510037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 58610037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 58710037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 58810037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 58910037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 59010037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 59110037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 59210037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 59310037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 59410037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 59510037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 59610037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 59710037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 59810037SARM gem5 Developers 59910037SARM gem5 Developers #Config 2 Register 60010037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 60110037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 60210037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 60310037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 604 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 605 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 606 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 607 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 608 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 609 610 611 #Config 3 Register 612 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 613 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 614 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 615 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 616 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 617 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 618 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 619 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 620 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 621 622 #SRS Ctl - HSS 623 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 624 625 626 #TestCPUClass.CoreParams.tlb = TLB() 627 #TestCPUClass.CoreParams.UnifiedTLB = 1 628