FSConfig.py revision 12564
112067Snikos.nikoleris@arm.com# Copyright (c) 2010-2012, 2015-2017 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 4212564Sgabeblack@google.comfrom __future__ import print_function 4312564Sgabeblack@google.com 442934Sktlim@umich.edufrom m5.objects import * 452995Ssaidi@eecs.umich.edufrom Benchmarks import * 4610046Snilay@cs.wisc.edufrom m5.util import * 4711688Sandreas.hansson@arm.comfrom common import PlatformConfig 482934Sktlim@umich.edu 4910747SChris.Emmons@arm.com# Populate to reflect supported os types per target ISA 5010747SChris.Emmons@arm.comos_types = { 'alpha' : [ 'linux' ], 5110747SChris.Emmons@arm.com 'mips' : [ 'linux' ], 5210747SChris.Emmons@arm.com 'sparc' : [ 'linux' ], 5310747SChris.Emmons@arm.com 'x86' : [ 'linux' ], 5410747SChris.Emmons@arm.com 'arm' : [ 'linux', 5510747SChris.Emmons@arm.com 'android-gingerbread', 5610747SChris.Emmons@arm.com 'android-ics', 5710747SChris.Emmons@arm.com 'android-jellybean', 5812026Sweipingliao@google.com 'android-kitkat', 5912026Sweipingliao@google.com 'android-nougat', ], 6010747SChris.Emmons@arm.com } 6110747SChris.Emmons@arm.com 622934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 632934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 642934Sktlim@umich.edu read_only=False) 652934Sktlim@umich.edu 662934Sktlim@umich.edu def childImage(self, ci): 672934Sktlim@umich.edu self.image.child.image_file = ci 682934Sktlim@umich.edu 6910720Sandreas.hansson@arm.comclass MemBus(SystemXBar): 706122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 716122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 726122SSteve.Reinhardt@amd.com 7310594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 7410594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 7510697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 7610594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 7710594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 7810594Sgabeblack@google.com return template % kwargs 7910594Sgabeblack@google.com 8010594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 8110118Snilay@cs.wisc.edu 824520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 834982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 844520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 854520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 862934Sktlim@umich.edu 872934Sktlim@umich.edu self = LinuxAlphaSystem() 883005Sstever@eecs.umich.edu if not mdesc: 893005Sstever@eecs.umich.edu # generic system 903304Sstever@eecs.umich.edu mdesc = SysConfig() 912995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 9210118Snilay@cs.wisc.edu 9310118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 9410118Snilay@cs.wisc.edu 9510118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 9610720Sandreas.hansson@arm.com self.iobus = IOXBar() 9710118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 9810118Snilay@cs.wisc.edu 9910118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 10210118Snilay@cs.wisc.edu 10310118Snilay@cs.wisc.edu if ruby: 10410118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 10510118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 10610118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 10710118Snilay@cs.wisc.edu else: 10810118Snilay@cs.wisc.edu self.membus = MemBus() 10910118Snilay@cs.wisc.edu 11010118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 11110118Snilay@cs.wisc.edu # base address (including the PCI config space) 11210118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 11310118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1148713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 11510118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 11610118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 11710118Snilay@cs.wisc.edu 11810118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 11910118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 12010118Snilay@cs.wisc.edu 12110118Snilay@cs.wisc.edu self.system_port = self.membus.slave 12210118Snilay@cs.wisc.edu 1239826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1242934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1252934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1262995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1272934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1286765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1296765SBrad.Beckmann@amd.com read_only = True)) 1306765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1316765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1326765SBrad.Beckmann@amd.com self.terminal = Terminal() 1336765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1346765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1356765SBrad.Beckmann@amd.com self.console = binary('console') 13610594Sgabeblack@google.com if not cmdline: 13710594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 13810594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1396765SBrad.Beckmann@amd.com 1406765SBrad.Beckmann@amd.com return self 1416765SBrad.Beckmann@amd.com 14211182Spalle@lyckegaard.dkdef makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 1438713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1448713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1458713Sandreas.hansson@arm.com uart_pio_size = 8 1468713Sandreas.hansson@arm.com 1474486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1484486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1494486Sbinkertn@umich.edu read_only=False) 1504486Sbinkertn@umich.edu 1514486Sbinkertn@umich.edu def childImage(self, ci): 1524486Sbinkertn@umich.edu self.image.child.image_file = ci 1534486Sbinkertn@umich.edu 1543584Ssaidi@eecs.umich.edu self = SparcSystem() 1553584Ssaidi@eecs.umich.edu if not mdesc: 1563584Ssaidi@eecs.umich.edu # generic system 1573584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1583584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 15910720Sandreas.hansson@arm.com self.iobus = IOXBar() 1609036Sandreas.hansson@arm.com self.membus = MemBus() 1619164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1623743Sgblack@eecs.umich.edu self.t1000 = T1000() 1634104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1643743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1659826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1669826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1678839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1688839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1698839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1708839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1718839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1728839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1733584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1743898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 17511563Sjakub@jermar.eu self.disk0.childImage(mdesc.disk()) 1768839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1778713Sandreas.hansson@arm.com 1788713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1798713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1808713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1818713Sandreas.hansson@arm.com self.bridge.ranges = \ 1828713Sandreas.hansson@arm.com [ 1838713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1848713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1858713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1868713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1878713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1888713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1898713Sandreas.hansson@arm.com iob_man_addr - 1), 1908713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1918713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1928713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1938713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1948713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1958713Sandreas.hansson@arm.com ] 1964103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1974103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1984103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1993745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2003745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2013745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2023584Ssaidi@eecs.umich.edu 2038839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2048706Sandreas.hansson@arm.com 2053584Ssaidi@eecs.umich.edu return self 2063584Ssaidi@eecs.umich.edu 20710588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 20810780SCurtis.Dunham@arm.com dtb_filename=None, bare_metal=False, cmdline=None, 20912475Sglenn.bergmans@arm.com external_memory="", ruby=False, security=False, 21012475Sglenn.bergmans@arm.com ignore_dtb=False): 2118061SAli.Saidi@ARM.com assert machine_type 2128061SAli.Saidi@ARM.com 21311238Sandreas.sandberg@arm.com default_dtbs = { 21411238Sandreas.sandberg@arm.com "RealViewEB": None, 21511238Sandreas.sandberg@arm.com "RealViewPBX": None, 21611238Sandreas.sandberg@arm.com "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 21711238Sandreas.sandberg@arm.com "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 21811238Sandreas.sandberg@arm.com } 21911238Sandreas.sandberg@arm.com 22011238Sandreas.sandberg@arm.com default_kernels = { 22111238Sandreas.sandberg@arm.com "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 22211238Sandreas.sandberg@arm.com "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 22311238Sandreas.sandberg@arm.com "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 22411238Sandreas.sandberg@arm.com "VExpress_EMM64": "vmlinux.aarch64.20140821", 22511238Sandreas.sandberg@arm.com } 22611238Sandreas.sandberg@arm.com 22711297Sandreas.sandberg@arm.com pci_devices = [] 22811297Sandreas.sandberg@arm.com 2297586SAli.Saidi@arm.com if bare_metal: 2307586SAli.Saidi@arm.com self = ArmSystem() 2317586SAli.Saidi@arm.com else: 2327586SAli.Saidi@arm.com self = LinuxArmSystem() 2337586SAli.Saidi@arm.com 2347586SAli.Saidi@arm.com if not mdesc: 2357586SAli.Saidi@arm.com # generic system 2367586SAli.Saidi@arm.com mdesc = SysConfig() 2377586SAli.Saidi@arm.com 2387586SAli.Saidi@arm.com self.readfile = mdesc.script() 23910720Sandreas.hansson@arm.com self.iobus = IOXBar() 24011598Sandreas.sandberg@arm.com if not ruby: 24111598Sandreas.sandberg@arm.com self.bridge = Bridge(delay='50ns') 24211598Sandreas.sandberg@arm.com self.bridge.master = self.iobus.slave 24311598Sandreas.sandberg@arm.com self.membus = MemBus() 24411598Sandreas.sandberg@arm.com self.membus.badaddr_responder.warn_access = "warn" 24511598Sandreas.sandberg@arm.com self.bridge.slave = self.membus.master 2467586SAli.Saidi@arm.com 2477586SAli.Saidi@arm.com self.mem_mode = mem_mode 2487586SAli.Saidi@arm.com 24911238Sandreas.sandberg@arm.com platform_class = PlatformConfig.get(machine_type) 25011238Sandreas.sandberg@arm.com # Resolve the real platform name, the original machine_type 25111238Sandreas.sandberg@arm.com # variable might have been an alias. 25211238Sandreas.sandberg@arm.com machine_type = platform_class.__name__ 25311238Sandreas.sandberg@arm.com self.realview = platform_class() 25411238Sandreas.sandberg@arm.com 25512475Sglenn.bergmans@arm.com if not dtb_filename and not (bare_metal or ignore_dtb): 25611238Sandreas.sandberg@arm.com try: 25711238Sandreas.sandberg@arm.com dtb_filename = default_dtbs[machine_type] 25811238Sandreas.sandberg@arm.com except KeyError: 25911238Sandreas.sandberg@arm.com fatal("No DTB specified and no default DTB known for '%s'" % \ 26011238Sandreas.sandberg@arm.com machine_type) 26111238Sandreas.sandberg@arm.com 26211238Sandreas.sandberg@arm.com if isinstance(self.realview, VExpress_EMM64): 26310512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 26412564Sgabeblack@google.com print("Selected 64-bit ARM architecture, updating default " 26512564Sgabeblack@google.com "disk image...") 26610512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 2677586SAli.Saidi@arm.com 26810353SGeoffrey.Blake@arm.com 26910353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 27010353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 27111297Sandreas.sandberg@arm.com 27211297Sandreas.sandberg@arm.com self.cf0 = CowIdeDisk(driveID='master') 27311297Sandreas.sandberg@arm.com self.cf0.childImage(mdesc.disk()) 27411297Sandreas.sandberg@arm.com # Old platforms have a built-in IDE or CF controller. Default to 27511297Sandreas.sandberg@arm.com # the IDE controller if both exist. New platforms expect the 27611297Sandreas.sandberg@arm.com # storage controller to be added from the config script. 27711297Sandreas.sandberg@arm.com if hasattr(self.realview, "ide"): 27810357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 27911297Sandreas.sandberg@arm.com elif hasattr(self.realview, "cf_ctrl"): 2808528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 28111297Sandreas.sandberg@arm.com else: 28211297Sandreas.sandberg@arm.com self.pci_ide = IdeController(disks=[self.cf0]) 28311297Sandreas.sandberg@arm.com pci_devices.append(self.pci_ide) 2848528SAli.Saidi@ARM.com 28510507SAli.Saidi@ARM.com self.mem_ranges = [] 28610507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 28710507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 28810507SAli.Saidi@ARM.com if size_remain > long(region[1]): 28910507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 29010507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 29110507SAli.Saidi@ARM.com else: 29210507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 29310507SAli.Saidi@ARM.com size_remain = 0 29410507SAli.Saidi@ARM.com break 29510507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 29610507SAli.Saidi@ARM.com " another memory controller for that range.") 29710507SAli.Saidi@ARM.com 29810507SAli.Saidi@ARM.com if size_remain > 0: 29910507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 30010507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 30110507SAli.Saidi@ARM.com " another platform") 30210507SAli.Saidi@ARM.com 30312079Sgedare@rtems.org self.have_security = security 30412079Sgedare@rtems.org 3058061SAli.Saidi@ARM.com if bare_metal: 3068061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 3078061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 3088061SAli.Saidi@ARM.com else: 30911238Sandreas.sandberg@arm.com if machine_type in default_kernels: 31011238Sandreas.sandberg@arm.com self.kernel = binary(default_kernels[machine_type]) 31110161Satgutier@umich.edu 31212475Sglenn.bergmans@arm.com if dtb_filename and not ignore_dtb: 3139929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 31411238Sandreas.sandberg@arm.com 31511238Sandreas.sandberg@arm.com self.machine_type = machine_type if machine_type in ArmMachineType.map \ 31611238Sandreas.sandberg@arm.com else "DTOnly" 31711238Sandreas.sandberg@arm.com 31810071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 31910594Sgabeblack@google.com if not cmdline: 32010594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 32110594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 32210697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 32310071Satgutier@umich.edu 32410780SCurtis.Dunham@arm.com # When using external memory, gem5 writes the boot loader to nvmem 32510780SCurtis.Dunham@arm.com # and then SST will read from it, but SST can only get to nvmem from 32610780SCurtis.Dunham@arm.com # iobus, as gem5's membus is only used for initialization and 32710780SCurtis.Dunham@arm.com # SST doesn't use it. Attaching nvmem to iobus solves this issue. 32810780SCurtis.Dunham@arm.com # During initialization, system_port -> membus -> iobus -> nvmem. 32911598Sandreas.sandberg@arm.com if external_memory or ruby: 33010780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.iobus, self, binary) 33110780SCurtis.Dunham@arm.com else: 33210780SCurtis.Dunham@arm.com self.realview.setupBootLoader(self.membus, self, binary) 3338528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 3348528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 3358287SAli.Saidi@ARM.com 33610747SChris.Emmons@arm.com # This check is for users who have previously put 'android' in 33710747SChris.Emmons@arm.com # the disk image filename to tell the config scripts to 33810747SChris.Emmons@arm.com # prepare the kernel with android-specific boot options. That 33910747SChris.Emmons@arm.com # behavior has been replaced with a more explicit option per 34010747SChris.Emmons@arm.com # the error message below. The disk can have any name now and 34110747SChris.Emmons@arm.com # doesn't need to include 'android' substring. 34210735Srb639@drexel.edu if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 34310747SChris.Emmons@arm.com if 'android' not in mdesc.os_type(): 34410747SChris.Emmons@arm.com fatal("It looks like you are trying to boot an Android " \ 34510747SChris.Emmons@arm.com "platform. To boot Android, you must specify " \ 34610747SChris.Emmons@arm.com "--os-type with an appropriate Android release on " \ 34710747SChris.Emmons@arm.com "the command line.") 34810747SChris.Emmons@arm.com 34910747SChris.Emmons@arm.com # android-specific tweaks 35010747SChris.Emmons@arm.com if 'android' in mdesc.os_type(): 35110747SChris.Emmons@arm.com # generic tweaks 35210747SChris.Emmons@arm.com cmdline += " init=/init" 35310747SChris.Emmons@arm.com 35410747SChris.Emmons@arm.com # release-specific tweaks 35510747SChris.Emmons@arm.com if 'kitkat' in mdesc.os_type(): 35610747SChris.Emmons@arm.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 35712026Sweipingliao@google.com "android.bootanim=0 " 35812026Sweipingliao@google.com elif 'nougat' in mdesc.os_type(): 35912026Sweipingliao@google.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 36012026Sweipingliao@google.com "android.bootanim=0 " + \ 36112026Sweipingliao@google.com "vmalloc=640MB " + \ 36212026Sweipingliao@google.com "android.early.fstab=/fstab.gem5 " + \ 36312026Sweipingliao@google.com "androidboot.selinux=permissive " + \ 36412026Sweipingliao@google.com "video=Virtual-1:1920x1080-16" 36510747SChris.Emmons@arm.com 36610594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 36710747SChris.Emmons@arm.com 36810780SCurtis.Dunham@arm.com if external_memory: 36910780SCurtis.Dunham@arm.com # I/O traffic enters iobus 37010780SCurtis.Dunham@arm.com self.external_io = ExternalMaster(port_data="external_io", 37110780SCurtis.Dunham@arm.com port_type=external_memory) 37210780SCurtis.Dunham@arm.com self.external_io.port = self.iobus.slave 37310780SCurtis.Dunham@arm.com 37410780SCurtis.Dunham@arm.com # Ensure iocache only receives traffic destined for (actual) memory. 37510780SCurtis.Dunham@arm.com self.iocache = ExternalSlave(port_data="iocache", 37610780SCurtis.Dunham@arm.com port_type=external_memory, 37710780SCurtis.Dunham@arm.com addr_ranges=self.mem_ranges) 37810780SCurtis.Dunham@arm.com self.iocache.port = self.iobus.master 37910780SCurtis.Dunham@arm.com 38010780SCurtis.Dunham@arm.com # Let system_port get to nvmem and nothing else. 38110780SCurtis.Dunham@arm.com self.bridge.ranges = [self.realview.nvmem.range] 38210780SCurtis.Dunham@arm.com 38310780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.iobus) 38411598Sandreas.sandberg@arm.com # Attach off-chip devices 38511598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus) 38611598Sandreas.sandberg@arm.com elif ruby: 38711598Sandreas.sandberg@arm.com self._dma_ports = [ ] 38811598Sandreas.sandberg@arm.com self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 38911598Sandreas.sandberg@arm.com # Force Ruby to treat the boot ROM as an IO device. 39011598Sandreas.sandberg@arm.com self.realview.nvmem.in_addr_map = False 39111598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 39210780SCurtis.Dunham@arm.com else: 39310780SCurtis.Dunham@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 39411598Sandreas.sandberg@arm.com # Attach off-chip devices 39511598Sandreas.sandberg@arm.com self.realview.attachIO(self.iobus) 39611297Sandreas.sandberg@arm.com 39711297Sandreas.sandberg@arm.com for dev_id, dev in enumerate(pci_devices): 39811297Sandreas.sandberg@arm.com dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 39911598Sandreas.sandberg@arm.com self.realview.attachPciDevice( 40011598Sandreas.sandberg@arm.com dev, self.iobus, 40111598Sandreas.sandberg@arm.com dma_ports=self._dma_ports if ruby else None) 40211297Sandreas.sandberg@arm.com 4037586SAli.Saidi@arm.com self.intrctrl = IntrControl() 4047586SAli.Saidi@arm.com self.terminal = Terminal() 4057949SAli.Saidi@ARM.com self.vncserver = VncServer() 4067586SAli.Saidi@arm.com 40711598Sandreas.sandberg@arm.com if not ruby: 40811598Sandreas.sandberg@arm.com self.system_port = self.membus.slave 4098706Sandreas.hansson@arm.com 41011599Sandreas.sandberg@arm.com if ruby: 41112067Snikos.nikoleris@arm.com if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 41212067Snikos.nikoleris@arm.com fatal("The MI_example protocol cannot implement Load/Store " 41312067Snikos.nikoleris@arm.com "Exclusive operations. Multicore ARM systems configured " 41412067Snikos.nikoleris@arm.com "with the MI_example protocol will not work properly.") 41512067Snikos.nikoleris@arm.com warn("You are trying to use Ruby on ARM, which is not working " 41612067Snikos.nikoleris@arm.com "properly yet.") 41711599Sandreas.sandberg@arm.com 4187586SAli.Saidi@arm.com return self 4197586SAli.Saidi@arm.com 4207586SAli.Saidi@arm.com 42110594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 4225222Sksewell@umich.edu class BaseMalta(Malta): 4235222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 4245222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 4255222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 4265222Sksewell@umich.edu 4275222Sksewell@umich.edu self = LinuxMipsSystem() 4285222Sksewell@umich.edu if not mdesc: 4295222Sksewell@umich.edu # generic system 4305222Sksewell@umich.edu mdesc = SysConfig() 4315222Sksewell@umich.edu self.readfile = mdesc.script() 43210720Sandreas.hansson@arm.com self.iobus = IOXBar() 4339036Sandreas.hansson@arm.com self.membus = MemBus() 4349164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 4359826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 4368839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 4378839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 4385222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 4395222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 4405222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 4415222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 4425222Sksewell@umich.edu self.malta = BaseMalta() 4435222Sksewell@umich.edu self.malta.attachIO(self.iobus) 4448839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 4458839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 4468839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 4478839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 4485222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 4495222Sksewell@umich.edu read_only = True)) 4505222Sksewell@umich.edu self.intrctrl = IntrControl() 4515222Sksewell@umich.edu self.mem_mode = mem_mode 4525478Snate@binkert.org self.terminal = Terminal() 4535222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 4545222Sksewell@umich.edu self.console = binary('mips/console') 45510594Sgabeblack@google.com if not cmdline: 45610594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 45710594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 4585222Sksewell@umich.edu 4598839Sandreas.hansson@arm.com self.system_port = self.membus.slave 4608706Sandreas.hansson@arm.com 4615222Sksewell@umich.edu return self 4625222Sksewell@umich.edu 4635323Sgblack@eecs.umich.edudef x86IOAddress(port): 4645357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 4658323Ssteve.reinhardt@amd.com return IO_address_space_base + port 4665323Sgblack@eecs.umich.edu 4678858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 4688713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 4698713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 4708713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 4718713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 4728713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 4738713Sandreas.hansson@arm.com 4749036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 4757905SBrad.Beckmann@amd.com 4767905SBrad.Beckmann@amd.com # North Bridge 47710720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4789164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 4798839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 4808839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 48110438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 48210438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 48310438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 48410438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 48510438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 48610438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 4878713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 4888713Sandreas.hansson@arm.com [ 48910438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 4908713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 4918713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 4928713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 4938713Sandreas.hansson@arm.com Addr.max) 4948713Sandreas.hansson@arm.com ] 4958713Sandreas.hansson@arm.com 4968713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4978713Sandreas.hansson@arm.com # the local APIC (two pages) 4989164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4998839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 5008839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 5018815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 5028815Sgblack@eecs.umich.edu interrupts_address_space_base + 5038858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 5048858Sgblack@eecs.umich.edu - 1)] 5057905SBrad.Beckmann@amd.com 5067905SBrad.Beckmann@amd.com # connect the io bus 5077905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 5087905SBrad.Beckmann@amd.com 5098839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 5108706Sandreas.hansson@arm.com 5117905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 5127905SBrad.Beckmann@amd.com # North Bridge 51310720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 5147905SBrad.Beckmann@amd.com 5158929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 5168929Snilay@cs.wisc.edu # dma controllers 5178929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 51810118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 5197905SBrad.Beckmann@amd.com 5207905SBrad.Beckmann@amd.com 52110588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 5225613Sgblack@eecs.umich.edu if self == None: 5235613Sgblack@eecs.umich.edu self = X86System() 5245613Sgblack@eecs.umich.edu 5255133Sgblack@eecs.umich.edu if not mdesc: 5265133Sgblack@eecs.umich.edu # generic system 5275133Sgblack@eecs.umich.edu mdesc = SysConfig() 5285133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 5295133Sgblack@eecs.umich.edu 5306802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 5316802Sgblack@eecs.umich.edu 5325133Sgblack@eecs.umich.edu # Physical memory 53310041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 53410041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 53510041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 53610041Snilay@cs.wisc.edu excess_mem_size = \ 53710041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 53810041Snilay@cs.wisc.edu if excess_mem_size <= 0: 53910041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 54010041Snilay@cs.wisc.edu else: 54110046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 54210046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 54310046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 54410046Snilay@cs.wisc.edu 54510041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 54610041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 5475613Sgblack@eecs.umich.edu 5485613Sgblack@eecs.umich.edu # Platform 5495638Sgblack@eecs.umich.edu self.pc = Pc() 5507905SBrad.Beckmann@amd.com 5517905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 5527905SBrad.Beckmann@amd.com if Ruby: 5537905SBrad.Beckmann@amd.com connectX86RubySystem(self) 5547905SBrad.Beckmann@amd.com else: 5558858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 5565613Sgblack@eecs.umich.edu 5575613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 5585613Sgblack@eecs.umich.edu 5595841Sgblack@eecs.umich.edu # Disks 5605841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 5615841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 5625841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 5635841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 5645841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 5655841Sgblack@eecs.umich.edu 5665615Sgblack@eecs.umich.edu # Add in a Bios information structure. 5675615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 5685615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 5695615Sgblack@eecs.umich.edu 5705641Sgblack@eecs.umich.edu # Set up the Intel MP table 5718323Ssteve.reinhardt@amd.com base_entries = [] 5728323Ssteve.reinhardt@amd.com ext_entries = [] 5736135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 5746135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 5756135Sgblack@eecs.umich.edu local_apic_id = i, 5766135Sgblack@eecs.umich.edu local_apic_version = 0x14, 5776135Sgblack@eecs.umich.edu enable = True, 5786135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 5798323Ssteve.reinhardt@amd.com base_entries.append(bp) 5805644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 5816135Sgblack@eecs.umich.edu id = numCPUs, 5825644Sgblack@eecs.umich.edu version = 0x11, 5835644Sgblack@eecs.umich.edu enable = True, 5845644Sgblack@eecs.umich.edu address = 0xfec00000) 5856135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5868323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 58710437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 58810437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 58910437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 59011481Sbaz21@cam.ac.uk pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 59110437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 59211481Sbaz21@cam.ac.uk isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 5938323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 59410437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 59510437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 5968323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 5975843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5985843Sgblack@eecs.umich.edu interrupt_type = 'INT', 5995843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 6005843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 60110437Smajiuyue@ncic.ac.cn source_bus_id = 0, 6025843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 6036044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 6045843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 6058323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 6066135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 6076135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 6086135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 6096135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 6106135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 61110437Smajiuyue@ncic.ac.cn source_bus_id = 1, 6126135Sgblack@eecs.umich.edu source_bus_irq = irq, 6136135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 6146135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 6158323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 6166135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 6176135Sgblack@eecs.umich.edu interrupt_type = 'INT', 6186135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 6196135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 62010437Smajiuyue@ncic.ac.cn source_bus_id = 1, 6216135Sgblack@eecs.umich.edu source_bus_irq = irq, 6226135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 6236135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 6248323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 6256135Sgblack@eecs.umich.edu assignISAInt(0, 2) 6266135Sgblack@eecs.umich.edu assignISAInt(1, 1) 6276135Sgblack@eecs.umich.edu for i in range(3, 15): 6286135Sgblack@eecs.umich.edu assignISAInt(i, i) 6298323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 6308323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 6315641Sgblack@eecs.umich.edu 63210594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 63310594Sgabeblack@google.com cmdline=None): 6345613Sgblack@eecs.umich.edu self = LinuxX86System() 6355613Sgblack@eecs.umich.edu 6367905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 6379826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 6385613Sgblack@eecs.umich.edu 6395450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 6405450Sgblack@eecs.umich.edu # just to avoid corner cases. 6419826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 6429232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 64310041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 6445450Sgblack@eecs.umich.edu 64510041Snilay@cs.wisc.edu entries = \ 6468323Ssteve.reinhardt@amd.com [ 6478323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 6489622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 6499622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 65010041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 6518323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 65210041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 6539898Sandreas@sandberg.pp.se range_type = 1), 6548323Ssteve.reinhardt@amd.com ] 6555450Sgblack@eecs.umich.edu 65610438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 65710438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 65810438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 65910438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 66010438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 66110438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 66210438Smajiuyue@ncic.ac.cn range_type=2)) 66310438Smajiuyue@ncic.ac.cn 66410438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 66510438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 66610438Smajiuyue@ncic.ac.cn 66710041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 66810041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 66910041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 67010041Snilay@cs.wisc.edu # reserved for devices. 67110041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 67210041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 67310041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 67410041Snilay@cs.wisc.edu 67510041Snilay@cs.wisc.edu self.e820_table.entries = entries 67610041Snilay@cs.wisc.edu 6775330Sgblack@eecs.umich.edu # Command line 67810594Sgabeblack@google.com if not cmdline: 67910594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 68010594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 68110003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 6825133Sgblack@eecs.umich.edu return self 6835133Sgblack@eecs.umich.edu 6843584Ssaidi@eecs.umich.edu 6858801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6868801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 6872995Ssaidi@eecs.umich.edu self.testsys = testSystem 6882995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 6894981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 6904981Ssaidi@eecs.umich.edu 6918661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 6928661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6938661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6948661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 6958661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6968661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6978661SAli.Saidi@ARM.com else: 6988661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 6998661SAli.Saidi@ARM.com 7003025Ssaidi@eecs.umich.edu if dumpfile: 7013025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 7023025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 7032934Sktlim@umich.edu 7042934Sktlim@umich.edu return self 70511291Sgabor.dozsa@arm.com 70611291Sgabor.dozsa@arm.com 70711291Sgabor.dozsa@arm.comdef makeDistRoot(testSystem, 70811291Sgabor.dozsa@arm.com rank, 70911291Sgabor.dozsa@arm.com size, 71011291Sgabor.dozsa@arm.com server_name, 71111291Sgabor.dozsa@arm.com server_port, 71211291Sgabor.dozsa@arm.com sync_repeat, 71311291Sgabor.dozsa@arm.com sync_start, 71411291Sgabor.dozsa@arm.com linkspeed, 71511291Sgabor.dozsa@arm.com linkdelay, 71611291Sgabor.dozsa@arm.com dumpfile): 71711291Sgabor.dozsa@arm.com self = Root(full_system = True) 71811291Sgabor.dozsa@arm.com self.testsys = testSystem 71911291Sgabor.dozsa@arm.com 72011291Sgabor.dozsa@arm.com self.etherlink = DistEtherLink(speed = linkspeed, 72111291Sgabor.dozsa@arm.com delay = linkdelay, 72211291Sgabor.dozsa@arm.com dist_rank = rank, 72311291Sgabor.dozsa@arm.com dist_size = size, 72411291Sgabor.dozsa@arm.com server_name = server_name, 72511291Sgabor.dozsa@arm.com server_port = server_port, 72611291Sgabor.dozsa@arm.com sync_start = sync_start, 72711291Sgabor.dozsa@arm.com sync_repeat = sync_repeat) 72811291Sgabor.dozsa@arm.com 72911291Sgabor.dozsa@arm.com if hasattr(testSystem, 'realview'): 73011291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 73111291Sgabor.dozsa@arm.com elif hasattr(testSystem, 'tsunami'): 73211291Sgabor.dozsa@arm.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 73311291Sgabor.dozsa@arm.com else: 73411291Sgabor.dozsa@arm.com fatal("Don't know how to connect DistEtherLink to this system") 73511291Sgabor.dozsa@arm.com 73611291Sgabor.dozsa@arm.com if dumpfile: 73711291Sgabor.dozsa@arm.com self.etherdump = EtherDump(file=dumpfile) 73811291Sgabor.dozsa@arm.com self.etherlink.dump = Parent.etherdump 73911291Sgabor.dozsa@arm.com 74011291Sgabor.dozsa@arm.com return self 741