FSConfig.py revision 10747
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 4410046Snilay@cs.wisc.edufrom m5.util import * 452934Sktlim@umich.edu 4610747SChris.Emmons@arm.com# Populate to reflect supported os types per target ISA 4710747SChris.Emmons@arm.comos_types = { 'alpha' : [ 'linux' ], 4810747SChris.Emmons@arm.com 'mips' : [ 'linux' ], 4910747SChris.Emmons@arm.com 'sparc' : [ 'linux' ], 5010747SChris.Emmons@arm.com 'x86' : [ 'linux' ], 5110747SChris.Emmons@arm.com 'arm' : [ 'linux', 5210747SChris.Emmons@arm.com 'android-gingerbread', 5310747SChris.Emmons@arm.com 'android-ics', 5410747SChris.Emmons@arm.com 'android-jellybean', 5510747SChris.Emmons@arm.com 'android-kitkat' ], 5610747SChris.Emmons@arm.com } 5710747SChris.Emmons@arm.com 582934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 592934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 602934Sktlim@umich.edu read_only=False) 612934Sktlim@umich.edu 622934Sktlim@umich.edu def childImage(self, ci): 632934Sktlim@umich.edu self.image.child.image_file = ci 642934Sktlim@umich.edu 6510720Sandreas.hansson@arm.comclass MemBus(SystemXBar): 666122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 676122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 686122SSteve.Reinhardt@amd.com 6910594Sgabeblack@google.comdef fillInCmdline(mdesc, template, **kwargs): 7010594Sgabeblack@google.com kwargs.setdefault('disk', mdesc.disk()) 7110697SCurtis.Dunham@arm.com kwargs.setdefault('rootdev', mdesc.rootdev()) 7210594Sgabeblack@google.com kwargs.setdefault('mem', mdesc.mem()) 7310594Sgabeblack@google.com kwargs.setdefault('script', mdesc.script()) 7410594Sgabeblack@google.com return template % kwargs 7510594Sgabeblack@google.com 7610594Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 7710118Snilay@cs.wisc.edu 784520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 794982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 804520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 814520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 822934Sktlim@umich.edu 832934Sktlim@umich.edu self = LinuxAlphaSystem() 843005Sstever@eecs.umich.edu if not mdesc: 853005Sstever@eecs.umich.edu # generic system 863304Sstever@eecs.umich.edu mdesc = SysConfig() 872995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 8810118Snilay@cs.wisc.edu 8910118Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 9010118Snilay@cs.wisc.edu 9110118Snilay@cs.wisc.edu # Create the io bus to connect all device ports 9210720Sandreas.hansson@arm.com self.iobus = IOXBar() 9310118Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 9410118Snilay@cs.wisc.edu 9510118Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 9610118Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 9710118Snilay@cs.wisc.edu 9810118Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 9910118Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 10010118Snilay@cs.wisc.edu 10110118Snilay@cs.wisc.edu if ruby: 10210118Snilay@cs.wisc.edu # Store the dma devices for later connection to dma ruby ports. 10310118Snilay@cs.wisc.edu # Append an underscore to dma_ports to avoid the SimObjectVector check. 10410118Snilay@cs.wisc.edu self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 10510118Snilay@cs.wisc.edu else: 10610118Snilay@cs.wisc.edu self.membus = MemBus() 10710118Snilay@cs.wisc.edu 10810118Snilay@cs.wisc.edu # By default the bridge responds to all addresses above the I/O 10910118Snilay@cs.wisc.edu # base address (including the PCI config space) 11010118Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 11110118Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 1128713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 11310118Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 11410118Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 11510118Snilay@cs.wisc.edu 11610118Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 11710118Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 11810118Snilay@cs.wisc.edu 11910118Snilay@cs.wisc.edu self.system_port = self.membus.slave 12010118Snilay@cs.wisc.edu 1219826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 1222934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 1232934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 1242995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 1252934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1266765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1276765SBrad.Beckmann@amd.com read_only = True)) 1286765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1296765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1306765SBrad.Beckmann@amd.com self.terminal = Terminal() 1316765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1326765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1336765SBrad.Beckmann@amd.com self.console = binary('console') 13410594Sgabeblack@google.com if not cmdline: 13510594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 13610594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 1376765SBrad.Beckmann@amd.com 1386765SBrad.Beckmann@amd.com return self 1396765SBrad.Beckmann@amd.com 14010588Sgabeblack@google.comdef makeSparcSystem(mem_mode, mdesc=None): 1418713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1428713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1438713Sandreas.hansson@arm.com uart_pio_size = 8 1448713Sandreas.hansson@arm.com 1454486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1464486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1474486Sbinkertn@umich.edu read_only=False) 1484486Sbinkertn@umich.edu 1494486Sbinkertn@umich.edu def childImage(self, ci): 1504486Sbinkertn@umich.edu self.image.child.image_file = ci 1514486Sbinkertn@umich.edu 1523584Ssaidi@eecs.umich.edu self = SparcSystem() 1533584Ssaidi@eecs.umich.edu if not mdesc: 1543584Ssaidi@eecs.umich.edu # generic system 1553584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1563584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 15710720Sandreas.hansson@arm.com self.iobus = IOXBar() 1589036Sandreas.hansson@arm.com self.membus = MemBus() 1599164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 1603743Sgblack@eecs.umich.edu self.t1000 = T1000() 1614104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1623743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1639826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 1649826Sandreas.hansson@arm.com AddrRange(Addr('2GB'), size ='256MB')] 1658839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 1668839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 1678839Sandreas.hansson@arm.com self.rom.port = self.membus.master 1688839Sandreas.hansson@arm.com self.nvram.port = self.membus.master 1698839Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.master 1708839Sandreas.hansson@arm.com self.partition_desc.port = self.membus.master 1713584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1723898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1733898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1748839Sandreas.hansson@arm.com self.disk0.pio = self.iobus.master 1758713Sandreas.hansson@arm.com 1768713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1778713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 1788713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 1798713Sandreas.hansson@arm.com self.bridge.ranges = \ 1808713Sandreas.hansson@arm.com [ 1818713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 1828713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 1838713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 1848713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 1858713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 1868713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 1878713Sandreas.hansson@arm.com iob_man_addr - 1), 1888713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 1898713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 1908713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 1918713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 1928713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 1938713Sandreas.hansson@arm.com ] 1944103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1954103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1964103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1973745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1983745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1993745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2003584Ssaidi@eecs.umich.edu 2018839Sandreas.hansson@arm.com self.system_port = self.membus.slave 2028706Sandreas.hansson@arm.com 2033584Ssaidi@eecs.umich.edu return self 2043584Ssaidi@eecs.umich.edu 20510588Sgabeblack@google.comdef makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 20610594Sgabeblack@google.com dtb_filename=None, bare_metal=False, cmdline=None): 2078061SAli.Saidi@ARM.com assert machine_type 2088061SAli.Saidi@ARM.com 2097586SAli.Saidi@arm.com if bare_metal: 2107586SAli.Saidi@arm.com self = ArmSystem() 2117586SAli.Saidi@arm.com else: 2127586SAli.Saidi@arm.com self = LinuxArmSystem() 2137586SAli.Saidi@arm.com 2147586SAli.Saidi@arm.com if not mdesc: 2157586SAli.Saidi@arm.com # generic system 2167586SAli.Saidi@arm.com mdesc = SysConfig() 2177586SAli.Saidi@arm.com 2187586SAli.Saidi@arm.com self.readfile = mdesc.script() 21910720Sandreas.hansson@arm.com self.iobus = IOXBar() 2209036Sandreas.hansson@arm.com self.membus = MemBus() 2217586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2229164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 2238839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 2248839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 2257586SAli.Saidi@arm.com 2267586SAli.Saidi@arm.com self.mem_mode = mem_mode 2277586SAli.Saidi@arm.com 2287586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2297586SAli.Saidi@arm.com self.realview = RealViewPBX() 2307586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2317586SAli.Saidi@arm.com self.realview = RealViewEB() 2328870SAli.Saidi@ARM.com elif machine_type == "VExpress_EMM": 2338870SAli.Saidi@ARM.com self.realview = VExpress_EMM() 23410512SAli.Saidi@ARM.com if not dtb_filename: 23510512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus 23610037SARM gem5 Developers elif machine_type == "VExpress_EMM64": 23710037SARM gem5 Developers self.realview = VExpress_EMM64() 23810512SAli.Saidi@ARM.com if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 23910512SAli.Saidi@ARM.com print "Selected 64-bit ARM architecture, updating default disk image..." 24010512SAli.Saidi@ARM.com mdesc.diskname = 'linaro-minimal-aarch64.img' 24110512SAli.Saidi@ARM.com if not dtb_filename: 24210512SAli.Saidi@ARM.com dtb_filename = 'vexpress.aarch64.20140821.dtb' 2437586SAli.Saidi@arm.com else: 2447586SAli.Saidi@arm.com print "Unknown Machine Type" 2457586SAli.Saidi@arm.com sys.exit(1) 2467586SAli.Saidi@arm.com 2478528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2488528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 24910353SGeoffrey.Blake@arm.com 25010353SGeoffrey.Blake@arm.com # Attach any PCI devices this platform supports 25110353SGeoffrey.Blake@arm.com self.realview.attachPciDevices() 2528528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 25310357SAli.Saidi@ARM.com try: 25410357SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 25510357SAli.Saidi@ARM.com except: 2568528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2578528SAli.Saidi@ARM.com 25810507SAli.Saidi@ARM.com self.mem_ranges = [] 25910507SAli.Saidi@ARM.com size_remain = long(Addr(mdesc.mem())) 26010507SAli.Saidi@ARM.com for region in self.realview._mem_regions: 26110507SAli.Saidi@ARM.com if size_remain > long(region[1]): 26210507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=region[1])) 26310507SAli.Saidi@ARM.com size_remain = size_remain - long(region[1]) 26410507SAli.Saidi@ARM.com else: 26510507SAli.Saidi@ARM.com self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 26610507SAli.Saidi@ARM.com size_remain = 0 26710507SAli.Saidi@ARM.com break 26810507SAli.Saidi@ARM.com warn("Memory size specified spans more than one region. Creating" \ 26910507SAli.Saidi@ARM.com " another memory controller for that range.") 27010507SAli.Saidi@ARM.com 27110507SAli.Saidi@ARM.com if size_remain > 0: 27210507SAli.Saidi@ARM.com fatal("The currently selected ARM platforms doesn't support" \ 27310507SAli.Saidi@ARM.com " the amount of DRAM you've selected. Please try" \ 27410507SAli.Saidi@ARM.com " another platform") 27510507SAli.Saidi@ARM.com 2768061SAli.Saidi@ARM.com if bare_metal: 2778061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2788061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2798061SAli.Saidi@ARM.com else: 28010161Satgutier@umich.edu if machine_type == "VExpress_EMM64": 28110512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch64.20140821') 28210161Satgutier@umich.edu elif machine_type == "VExpress_EMM": 28310512SAli.Saidi@ARM.com self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5') 28410161Satgutier@umich.edu else: 28510161Satgutier@umich.edu self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 28610161Satgutier@umich.edu 2879929SAli.Saidi@ARM.com if dtb_filename: 2889929SAli.Saidi@ARM.com self.dtb_filename = binary(dtb_filename) 2897586SAli.Saidi@arm.com self.machine_type = machine_type 29010071Satgutier@umich.edu # Ensure that writes to the UART actually go out early in the boot 29110594Sgabeblack@google.com if not cmdline: 29210594Sgabeblack@google.com cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 29310594Sgabeblack@google.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 29410697SCurtis.Dunham@arm.com 'mem=%(mem)s root=%(rootdev)s' 29510071Satgutier@umich.edu 2968870SAli.Saidi@ARM.com self.realview.setupBootLoader(self.membus, self, binary) 2978528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2988528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2998287SAli.Saidi@ARM.com 30010747SChris.Emmons@arm.com # This check is for users who have previously put 'android' in 30110747SChris.Emmons@arm.com # the disk image filename to tell the config scripts to 30210747SChris.Emmons@arm.com # prepare the kernel with android-specific boot options. That 30310747SChris.Emmons@arm.com # behavior has been replaced with a more explicit option per 30410747SChris.Emmons@arm.com # the error message below. The disk can have any name now and 30510747SChris.Emmons@arm.com # doesn't need to include 'android' substring. 30610735Srb639@drexel.edu if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 30710747SChris.Emmons@arm.com if 'android' not in mdesc.os_type(): 30810747SChris.Emmons@arm.com fatal("It looks like you are trying to boot an Android " \ 30910747SChris.Emmons@arm.com "platform. To boot Android, you must specify " \ 31010747SChris.Emmons@arm.com "--os-type with an appropriate Android release on " \ 31110747SChris.Emmons@arm.com "the command line.") 31210747SChris.Emmons@arm.com 31310747SChris.Emmons@arm.com # android-specific tweaks 31410747SChris.Emmons@arm.com if 'android' in mdesc.os_type(): 31510747SChris.Emmons@arm.com # generic tweaks 31610747SChris.Emmons@arm.com cmdline += " init=/init" 31710747SChris.Emmons@arm.com 31810747SChris.Emmons@arm.com # release-specific tweaks 31910747SChris.Emmons@arm.com if 'kitkat' in mdesc.os_type(): 32010747SChris.Emmons@arm.com cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 32110747SChris.Emmons@arm.com "android.bootanim=0" 32210747SChris.Emmons@arm.com 32310594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 32410747SChris.Emmons@arm.com 3258713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 3267586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 3277586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3287586SAli.Saidi@arm.com self.terminal = Terminal() 3297949SAli.Saidi@ARM.com self.vncserver = VncServer() 3307586SAli.Saidi@arm.com 3318839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3328706Sandreas.hansson@arm.com 3337586SAli.Saidi@arm.com return self 3347586SAli.Saidi@arm.com 3357586SAli.Saidi@arm.com 33610594Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 3375222Sksewell@umich.edu class BaseMalta(Malta): 3385222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3395222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3405222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3415222Sksewell@umich.edu 3425222Sksewell@umich.edu self = LinuxMipsSystem() 3435222Sksewell@umich.edu if not mdesc: 3445222Sksewell@umich.edu # generic system 3455222Sksewell@umich.edu mdesc = SysConfig() 3465222Sksewell@umich.edu self.readfile = mdesc.script() 34710720Sandreas.hansson@arm.com self.iobus = IOXBar() 3489036Sandreas.hansson@arm.com self.membus = MemBus() 3499164Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns') 3509826Sandreas.hansson@arm.com self.mem_ranges = [AddrRange('1GB')] 3518839Sandreas.hansson@arm.com self.bridge.master = self.iobus.slave 3528839Sandreas.hansson@arm.com self.bridge.slave = self.membus.master 3535222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3545222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3555222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3565222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3575222Sksewell@umich.edu self.malta = BaseMalta() 3585222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3598839Sandreas.hansson@arm.com self.malta.ide.pio = self.iobus.master 3608839Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.master 3618839Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.slave 3628839Sandreas.hansson@arm.com self.malta.ethernet.pio = self.iobus.master 3638839Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.master 3648839Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.slave 3655222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3665222Sksewell@umich.edu read_only = True)) 3675222Sksewell@umich.edu self.intrctrl = IntrControl() 3685222Sksewell@umich.edu self.mem_mode = mem_mode 3695478Snate@binkert.org self.terminal = Terminal() 3705222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3715222Sksewell@umich.edu self.console = binary('mips/console') 37210594Sgabeblack@google.com if not cmdline: 37310594Sgabeblack@google.com cmdline = 'root=/dev/hda1 console=ttyS0' 37410594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 3755222Sksewell@umich.edu 3768839Sandreas.hansson@arm.com self.system_port = self.membus.slave 3778706Sandreas.hansson@arm.com 3785222Sksewell@umich.edu return self 3795222Sksewell@umich.edu 3805323Sgblack@eecs.umich.edudef x86IOAddress(port): 3815357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3828323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3835323Sgblack@eecs.umich.edu 3848858Sgblack@eecs.umich.edudef connectX86ClassicSystem(x86_sys, numCPUs): 3858713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3868713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3878713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3888713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3898713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3908713Sandreas.hansson@arm.com 3919036Sandreas.hansson@arm.com x86_sys.membus = MemBus() 3927905SBrad.Beckmann@amd.com 3937905SBrad.Beckmann@amd.com # North Bridge 39410720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 3959164Sandreas.hansson@arm.com x86_sys.bridge = Bridge(delay='50ns') 3968839Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.slave 3978839Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.master 39810438Smajiuyue@ncic.ac.cn # Allow the bridge to pass through: 39910438Smajiuyue@ncic.ac.cn # 1) kernel configured PCI device memory map address: address range 40010438Smajiuyue@ncic.ac.cn # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 40110438Smajiuyue@ncic.ac.cn # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 40210438Smajiuyue@ncic.ac.cn # 3) everything in the IO address range up to the local APIC, and 40310438Smajiuyue@ncic.ac.cn # 4) then the entire PCI address space and beyond. 4048713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 4058713Sandreas.hansson@arm.com [ 40610438Smajiuyue@ncic.ac.cn AddrRange(0xC0000000, 0xFFFF0000), 4078713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 4088713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 4098713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 4108713Sandreas.hansson@arm.com Addr.max) 4118713Sandreas.hansson@arm.com ] 4128713Sandreas.hansson@arm.com 4138713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 4148713Sandreas.hansson@arm.com # the local APIC (two pages) 4159164Sandreas.hansson@arm.com x86_sys.apicbridge = Bridge(delay='50ns') 4168839Sandreas.hansson@arm.com x86_sys.apicbridge.slave = x86_sys.iobus.master 4178839Sandreas.hansson@arm.com x86_sys.apicbridge.master = x86_sys.membus.slave 4188815Sgblack@eecs.umich.edu x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 4198815Sgblack@eecs.umich.edu interrupts_address_space_base + 4208858Sgblack@eecs.umich.edu numCPUs * APIC_range_size 4218858Sgblack@eecs.umich.edu - 1)] 4227905SBrad.Beckmann@amd.com 4237905SBrad.Beckmann@amd.com # connect the io bus 4247905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 4257905SBrad.Beckmann@amd.com 4268839Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.slave 4278706Sandreas.hansson@arm.com 4287905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4297905SBrad.Beckmann@amd.com # North Bridge 43010720Sandreas.hansson@arm.com x86_sys.iobus = IOXBar() 4317905SBrad.Beckmann@amd.com 4328929Snilay@cs.wisc.edu # add the ide to the list of dma devices that later need to attach to 4338929Snilay@cs.wisc.edu # dma controllers 4348929Snilay@cs.wisc.edu x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 43510118Snilay@cs.wisc.edu x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 4367905SBrad.Beckmann@amd.com 4377905SBrad.Beckmann@amd.com 43810588Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 4395613Sgblack@eecs.umich.edu if self == None: 4405613Sgblack@eecs.umich.edu self = X86System() 4415613Sgblack@eecs.umich.edu 4425133Sgblack@eecs.umich.edu if not mdesc: 4435133Sgblack@eecs.umich.edu # generic system 4445133Sgblack@eecs.umich.edu mdesc = SysConfig() 4455133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4465133Sgblack@eecs.umich.edu 4476802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4486802Sgblack@eecs.umich.edu 4495133Sgblack@eecs.umich.edu # Physical memory 45010041Snilay@cs.wisc.edu # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 45110041Snilay@cs.wisc.edu # for various devices. Hence, if the physical memory size is greater than 45210041Snilay@cs.wisc.edu # 3GB, we need to split it into two parts. 45310041Snilay@cs.wisc.edu excess_mem_size = \ 45410041Snilay@cs.wisc.edu convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 45510041Snilay@cs.wisc.edu if excess_mem_size <= 0: 45610041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange(mdesc.mem())] 45710041Snilay@cs.wisc.edu else: 45810046Snilay@cs.wisc.edu warn("Physical memory size specified is %s which is greater than " \ 45910046Snilay@cs.wisc.edu "3GB. Twice the number of memory controllers would be " \ 46010046Snilay@cs.wisc.edu "created." % (mdesc.mem())) 46110046Snilay@cs.wisc.edu 46210041Snilay@cs.wisc.edu self.mem_ranges = [AddrRange('3GB'), 46310041Snilay@cs.wisc.edu AddrRange(Addr('4GB'), size = excess_mem_size)] 4645613Sgblack@eecs.umich.edu 4655613Sgblack@eecs.umich.edu # Platform 4665638Sgblack@eecs.umich.edu self.pc = Pc() 4677905SBrad.Beckmann@amd.com 4687905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4697905SBrad.Beckmann@amd.com if Ruby: 4707905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4717905SBrad.Beckmann@amd.com else: 4728858Sgblack@eecs.umich.edu connectX86ClassicSystem(self, numCPUs) 4735613Sgblack@eecs.umich.edu 4745613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4755613Sgblack@eecs.umich.edu 4765841Sgblack@eecs.umich.edu # Disks 4775841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4785841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4795841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4805841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4815841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4825841Sgblack@eecs.umich.edu 4835615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4845615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4855615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4865615Sgblack@eecs.umich.edu 4875641Sgblack@eecs.umich.edu # Set up the Intel MP table 4888323Ssteve.reinhardt@amd.com base_entries = [] 4898323Ssteve.reinhardt@amd.com ext_entries = [] 4906135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4916135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4926135Sgblack@eecs.umich.edu local_apic_id = i, 4936135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4946135Sgblack@eecs.umich.edu enable = True, 4956135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4968323Ssteve.reinhardt@amd.com base_entries.append(bp) 4975644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4986135Sgblack@eecs.umich.edu id = numCPUs, 4995644Sgblack@eecs.umich.edu version = 0x11, 5005644Sgblack@eecs.umich.edu enable = True, 5015644Sgblack@eecs.umich.edu address = 0xfec00000) 5026135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 5038323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 50410437Smajiuyue@ncic.ac.cn # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 50510437Smajiuyue@ncic.ac.cn # but linux kernel cannot config PCI device if it was not connected to PCI bus, 50610437Smajiuyue@ncic.ac.cn # so we fix PCI bus id to 0, and ISA bus id to 1. 50710437Smajiuyue@ncic.ac.cn pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') 50810437Smajiuyue@ncic.ac.cn base_entries.append(pci_bus) 50910437Smajiuyue@ncic.ac.cn isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') 5108323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 51110437Smajiuyue@ncic.ac.cn connect_busses = X86IntelMPBusHierarchy(bus_id=1, 51210437Smajiuyue@ncic.ac.cn subtractive_decode=True, parent_bus=0) 5138323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 5145843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 5155843Sgblack@eecs.umich.edu interrupt_type = 'INT', 5165843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5175843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 51810437Smajiuyue@ncic.ac.cn source_bus_id = 0, 5195843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 5206044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5215843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 5228323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 5236135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 5246135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 5256135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 5266135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5276135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 52810437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5296135Sgblack@eecs.umich.edu source_bus_irq = irq, 5306135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5316135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 5328323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 5336135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 5346135Sgblack@eecs.umich.edu interrupt_type = 'INT', 5356135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 5366135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 53710437Smajiuyue@ncic.ac.cn source_bus_id = 1, 5386135Sgblack@eecs.umich.edu source_bus_irq = irq, 5396135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5406135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5418323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5426135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5436135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5446135Sgblack@eecs.umich.edu for i in range(3, 15): 5456135Sgblack@eecs.umich.edu assignISAInt(i, i) 5468323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5478323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5485641Sgblack@eecs.umich.edu 54910594Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 55010594Sgabeblack@google.com cmdline=None): 5515613Sgblack@eecs.umich.edu self = LinuxX86System() 5525613Sgblack@eecs.umich.edu 5537905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5549826Sandreas.hansson@arm.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5555613Sgblack@eecs.umich.edu 5565450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5575450Sgblack@eecs.umich.edu # just to avoid corner cases. 5589826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 5599232Sandreas.hansson@arm.com assert(phys_mem_size >= 0x200000) 56010041Snilay@cs.wisc.edu assert(len(self.mem_ranges) <= 2) 5615450Sgblack@eecs.umich.edu 56210041Snilay@cs.wisc.edu entries = \ 5638323Ssteve.reinhardt@amd.com [ 5648323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5659622Snilay@cs.wisc.edu X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5669622Snilay@cs.wisc.edu X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 56710041Snilay@cs.wisc.edu # Mark the rest of physical memory as available 5688323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 56910041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 5709898Sandreas@sandberg.pp.se range_type = 1), 5718323Ssteve.reinhardt@amd.com ] 5725450Sgblack@eecs.umich.edu 57310438Smajiuyue@ncic.ac.cn # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 57410438Smajiuyue@ncic.ac.cn # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 57510438Smajiuyue@ncic.ac.cn # specific range can pass though bridge to iobus. 57610438Smajiuyue@ncic.ac.cn if len(self.mem_ranges) == 1: 57710438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 57810438Smajiuyue@ncic.ac.cn size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 57910438Smajiuyue@ncic.ac.cn range_type=2)) 58010438Smajiuyue@ncic.ac.cn 58110438Smajiuyue@ncic.ac.cn # Reserve the last 16kB of the 32-bit address space for the m5op interface 58210438Smajiuyue@ncic.ac.cn entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 58310438Smajiuyue@ncic.ac.cn 58410041Snilay@cs.wisc.edu # In case the physical memory is greater than 3GB, we split it into two 58510041Snilay@cs.wisc.edu # parts and add a separate e820 entry for the second part. This entry 58610041Snilay@cs.wisc.edu # starts at 0x100000000, which is the first address after the space 58710041Snilay@cs.wisc.edu # reserved for devices. 58810041Snilay@cs.wisc.edu if len(self.mem_ranges) == 2: 58910041Snilay@cs.wisc.edu entries.append(X86E820Entry(addr = 0x100000000, 59010041Snilay@cs.wisc.edu size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 59110041Snilay@cs.wisc.edu 59210041Snilay@cs.wisc.edu self.e820_table.entries = entries 59310041Snilay@cs.wisc.edu 5945330Sgblack@eecs.umich.edu # Command line 59510594Sgabeblack@google.com if not cmdline: 59610594Sgabeblack@google.com cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 59710594Sgabeblack@google.com self.boot_osflags = fillInCmdline(mdesc, cmdline) 59810003Ssteve.reinhardt@amd.com self.kernel = binary('x86_64-vmlinux-2.6.22.9') 5995133Sgblack@eecs.umich.edu return self 6005133Sgblack@eecs.umich.edu 6013584Ssaidi@eecs.umich.edu 6028801Sgblack@eecs.umich.edudef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 6038801Sgblack@eecs.umich.edu self = Root(full_system = full_system) 6042995Ssaidi@eecs.umich.edu self.testsys = testSystem 6052995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 6064981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 6074981Ssaidi@eecs.umich.edu 6088661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 6098661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 6108661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 6118661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 6128661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 6138661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 6148661SAli.Saidi@ARM.com else: 6158661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 6168661SAli.Saidi@ARM.com 6173025Ssaidi@eecs.umich.edu if dumpfile: 6183025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 6193025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 6202934Sktlim@umich.edu 6212934Sktlim@umich.edu return self 622